URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 345 to Rev 346
- ↔ Reverse comparison
Rev 345 → Rev 346
/ethmac/trunk/bench/verilog/eth_host.v
3,7 → 3,7
//// eth_host.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/bench/verilog/eth_phy_defines.v
3,7 → 3,7
//// File name: eth_phy_defines.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Tadej Markovic, tadej@opencores.org //// |
/ethmac/trunk/bench/verilog/wb_slave_behavioral.v
3,7 → 3,7
//// File name: wb_slave_behavioral.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Tadej Markovic, tadej@opencores.org //// |
/ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v
3,7 → 3,7
//// tb_ethernet_with_cop.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/bench/verilog/wb_master_behavioral.v
3,7 → 3,7
//// File name "wb_master_behavioral.v" //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Miha Dolenc (mihad@opencores.org) //// |
/ethmac/trunk/bench/verilog/eth_phy.v
3,7 → 3,7
//// File name: eth_phy.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Tadej Markovic, tadej@opencores.org //// |
/ethmac/trunk/bench/verilog/tb_eth_defines.v
3,7 → 3,7
//// tb_eth_defines.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/bench/verilog/tb_ethernet.v
3,7 → 3,7
//// tb_ethernet.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Tadej Markovic, tadej@opencores.org //// |
/ethmac/trunk/bench/verilog/wb_model_defines.v
3,7 → 3,7
//// File name "wb_model_defines.v" //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Miha Dolenc (mihad@opencores.org) //// |
/ethmac/trunk/bench/verilog/tb_eth_top.v
26,7 → 26,7
//// tb_eth_top.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/bench/verilog/eth_memory.v
3,7 → 3,7
//// eth_memory.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/bench/verilog/wb_master32.v
3,7 → 3,7
//// File name "wb_master32.v" //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Miha Dolenc (mihad@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
3,7 → 3,7
//// eth_spram_256x32.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_shiftreg.v
3,7 → 3,7
//// eth_shiftreg.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_rxcounters.v
3,7 → 3,7
//// eth_rxcounters.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_txethmac.v
3,7 → 3,7
//// eth_txethmac.v //// |
/// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_defines.v
3,7 → 3,7
//// eth_defines.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_wishbone.v
3,7 → 3,7
//// eth_wishbone.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_txcounters.v
3,7 → 3,7
//// eth_txcounters.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_random.v
3,7 → 3,7
//// eth_random.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_cop.v
3,7 → 3,7
//// eth_cop.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_fifo.v
3,7 → 3,7
//// eth_fifo.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_receivecontrol.v
3,7 → 3,7
//// eth_receivecontrol.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_register.v
3,7 → 3,7
//// eth_register.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_clockgen.v
3,7 → 3,7
//// eth_clockgen.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_miim.v
3,7 → 3,7
//// eth_miim.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_outputcontrol.v
3,7 → 3,7
//// eth_outputcontrol.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_maccontrol.v
3,7 → 3,7
//// eth_maccontrol.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_top.v
3,7 → 3,7
//// eth_top.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_transmitcontrol.v
3,7 → 3,7
//// eth_transmitcontrol.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_macstatus.v
3,7 → 3,7
//// eth_macstatus.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/timescale.v
3,7 → 3,7
//// timescale.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_registers.v
3,7 → 3,7
//// eth_registers.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_crc.v
3,7 → 3,7
//// eth_crc.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_rxstatem.v
3,7 → 3,7
//// eth_rxstatem.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/ethmac/trunk/rtl/verilog/eth_txstatem.v
3,7 → 3,7
//// eth_txstatem.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |