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Rev 42 → Rev 43

/trunk/rtl/verilog/eth_txethmac.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
83,7 → 86,9
Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
ResetCollision
ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
LateCollision, StartDefer, StatePreamble, StateData
 
);
 
parameter Tp = 1;
121,6 → 126,14
output TxUsedData; // Transmit packet used data (to RISC)
output WillTransmit; // Will transmit (to RxEthMAC)
output ResetCollision; // Reset Collision (for synchronizing collision)
output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
output StartTxDone;
output StartTxAbort;
output MaxCollisionOccured;
output LateCollision;
output StartDefer;
output StatePreamble;
output [1:0] StateData;
 
reg [3:0] MTxD;
reg MTxEn;
137,10 → 150,10
reg StatusLatch;
reg PacketFinished_q;
reg PacketFinished;
reg [3:0] RetryCntLatched;
 
 
wire ExcessiveDeferOccured;
wire StartDefer;
wire StartIPG;
wire StartPreamble;
wire [1:0] StartData;
150,8 → 163,6
wire StateDefer;
wire StateIPG;
wire StateIdle;
wire StatePreamble;
wire [1:0] StateData;
wire StatePAD;
wire StateFCS;
wire StateJam;
158,12 → 169,8
wire StateBackOff;
wire StateSFD;
wire StartTxRetry;
wire StartTxDone;
wire LateCollision;
wire MaxCollisionOccured;
wire UnderRun;
wire TooBig;
wire StartTxAbort;
wire [31:0] Crc;
wire CrcError;
wire [2:0] DlyCrcCnt;
/trunk/rtl/verilog/eth_wishbone.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.4 2002/02/06 14:10:21 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
106,8 → 109,12
// Interrupts
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
// Rx Status
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
ReceivedPacketTooBig, RxLength, LoadRxStatus
ReceivedPacketTooBig, RxLength, LoadRxStatus,
// Tx Status
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost
 
);
 
139,7 → 146,7
 
input Reset; // Reset signal
 
// Status signals
// Rx Status signals
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
input LatchedCrcError; // CRC error
input RxLateCollision; // Late collision occured while receiving frame
149,6 → 156,13
input [15:0] RxLength; // Length of the incoming frame
input LoadRxStatus; // Rx status was loaded
 
// Tx Status signals
input [3:0] RetryCntLatched; // Latched Retry Counter
input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
input LateCollLatched; // Late collision occured
input DeferLatched; // Defer indication (Frame was defered before sucessfully sent)
input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
 
// Tx
input MTxClk; // Transmit clock (from PHY)
input TxUsedData; // Transmit packet used data
195,6 → 209,7
reg [7:0] TxData;
 
reg TxUnderRun;
reg TxUnderRun_wb;
 
reg TxBDRead;
wire TxStatusWrite;
202,9 → 217,10
reg [1:0] TxValidBytesLatched;
 
reg [15:0] TxLength;
reg [15:0] TxStatus;
reg [15:0] LatchedTxLength;
reg [14:11] TxStatus;
 
reg [14:13] RxStatusOld;
reg [14:13] RxStatus;
 
reg TxStartFrm_wb;
reg TxRetry_wb;
572,10 → 588,10
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStatus <=#Tp 15'h0;
TxStatus <=#Tp 4'h0;
else
if(TxEn & TxEn_q & TxBDRead)
TxStatus <=#Tp ram_do[15:0];
TxStatus <=#Tp ram_do[14:11];
end
 
reg ReadTxDataFromMemory;
611,6 → 627,16
end
end
 
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchedTxLength <=#Tp 16'h0;
else
if(TxEn & TxEn_q & TxBDRead)
LatchedTxLength <=#Tp ram_do[31:16];
end
 
assign TxLengthEq0 = TxLength == 0;
assign TxLengthLt4 = TxLength < 4;
 
777,7 → 803,7
 
eth_fifo #(`TX_FIFO_DATA_WIDTH, `TX_FIFO_DEPTH, `TX_FIFO_CNT_WIDTH)
tx_fifo (.data_in(m_wb_dat_i), .data_out(TxData_wb), .clk(WB_CLK_I),
.reset(Reset), .write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb),
.reset(Reset), .write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb),
.clear(TxFifoClear), .full(TxBufferFull), .almost_full(TxBufferAlmostFull),
.almost_empty(TxBufferAlmostEmpty), .empty(TxBufferEmpty));
 
929,18 → 955,18
// bit 10 od tx je last (crc se doda le ce je bit 11 in hkrati bit 10)
// bit 9 od tx je pause request (control frame)
// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
// bit 8 od tx je defer indication
// bit 7 od tx je late collision
// bit 6 od tx je retransmittion limit
// bit 5 od tx je underrun
// bit 8 od tx je defer indication done
// bit 7 od tx je late collision done
// bit 6 od tx je retransmittion limit done
// bit 5 od tx je underrun done
// bit 4 od tx je carrier sense lost
// bit [3:0] od tx je retry count
// bit [3:0] od tx je retry count done
 
//assign TxBDReady = TxStatus[15]; // already used
assign TxIRQEn = TxStatus[14];
assign WrapTxStatusBit = TxStatus[13]; // ok povezan
assign PerPacketPad = TxStatus[12]; // ok povezan
assign PerPacketCrcEn = TxStatus[11] & TxStatus[10]; // When last is also set // ok povezan
assign PerPacketCrcEn = TxStatus[11];
//assign TxPauseRq = TxStatus[9]; // already used Ta gre ven, ker bo stvar izvedena preko registrov
 
 
951,17 → 977,20
// bit 13 od rx je wrap
// bit 12 od rx je reserved
// bit 11 od rx je reserved
// bit 10 od rx je last (crc se doda le ce je bit 11 in hkrati bit 10)
// bit 9 od rx je pause request (control frame)
// Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
// bit 8 od rx je defer indication
// bit 7 od rx je late collision
// bit 6 od rx je retransmittion limit
// bit 5 od rx je underrun
// bit 4 od rx je carrier sense lost
// bit [3:0] od rx je retry count
// bit 10 od rx je reserved
// bit 9 od rx je reserved
// bit 8 od rx je reserved
// bit 7 od rx je reserved
// bit 6 od rx je underrun still missing
// bit 5 od rx je InvalidSymbol
// bit 4 od rx je DribbleNibble
// bit 3 od rx je ReceivedPacketTooBig
// bit 2 od rx je ShortFrame
// bit 1 od rx je LatchedCrcError
// bit 0 od rx je RxLateCollision
assign RxStatusIn = {InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
 
assign WrapRxStatusBit = RxStatusOld[13];
assign WrapRxStatusBit = RxStatus[13];
 
 
// Temporary Tx and Rx buffer descriptor address
994,10 → 1023,12
RxBDAddress <=#Tp TempRxBDAddress;
end
 
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatusOld, 7'h0, RxStatusInLatched}; // tu dopolni, da se bo vpisoval status
assign TxBDDataIn = {32'h004380ef}; // tu dopolni, da se bo vpisoval status
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
 
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 7'h0, RxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
 
 
// Signals used for various purposes
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
1126,13 → 1157,27
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxUnderRun <=#Tp 1'b0;
TxUnderRun_wb <=#Tp 1'b0;
else
if(TxAbortPulse)
TxUnderRun_wb <=#Tp 1'b0;
else
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
TxUnderRun_wb <=#Tp 1'b1;
end
 
 
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUnderRun <=#Tp 1'b0;
else
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
if(TxUnderRun_wb)
TxUnderRun <=#Tp 1'b1;
else
if(BlockingTxStatusWrite)
TxUnderRun <=#Tp 1'b0;
end
 
 
1309,10 → 1354,10
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatusOld <=#Tp 2'h0;
RxStatus <=#Tp 2'h0;
else
if(RxEn & RxEn_q & RxBDRead)
RxStatusOld <=#Tp ram_do[14:13];
RxStatus <=#Tp ram_do[14:13];
end
 
 
1710,6 → 1755,5
end
 
 
 
endmodule
 
/trunk/rtl/verilog/eth_wishbonedma.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.11 2002/02/06 14:10:21 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
127,7 → 130,8
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ,
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
ReceivedPacketTooBig, RxLength, LoadRxStatus
ReceivedPacketTooBig, RxLength, LoadRxStatus, RetryCntLatched, RetryLimit,
LateCollLatched, DeferLatched, CarrierSenseLost
 
 
);
154,7 → 158,7
output [1:0] WB_ND_O; // DMA force new descriptor output
output WB_RD_O; // DMA restart descriptor output
 
// Status
// Rx Status
input InvalidSymbol;
input LatchedCrcError;
input RxLateCollision;
164,6 → 168,14
input [15:0] RxLength;
input LoadRxStatus;
 
// Tx Status
input [3:0] RetryCntLatched;
input RetryLimit;
input LateCollLatched;
input DeferLatched;
input CarrierSenseLost;
 
 
// Tx
input MTxClk; // Transmit clock (from PHY)
input TxUsedData; // Transmit packet used data
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.10 2002/02/06 14:10:21 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
351,7 → 354,16
wire InvalidSymbol;
wire LatchedCrcError;
wire RxLateCollision;
wire [3:0] RetryCntLatched;
wire [3:0] RetryCnt;
wire StartTxDone;
wire StartTxAbort;
wire MaxCollisionOccured;
wire RetryLimit;
wire StatePreamble;
wire [1:0] StateData;
 
 
// Connecting MACControl
eth_maccontrol maccontrol1
(
418,7 → 430,10
.MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
.MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
.TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
.ResetCollision(ResetCollision)
.ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
.StartDefer(StartDefer), .StatePreamble(StatePreamble), .StateData(StateData)
 
);
 
 
589,7 → 604,9
 
.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus)
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
.CarrierSenseLost(CarrierSenseLost)
 
);
 
609,8 → 626,14
.CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
.r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
.DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
.LoadRxStatus(LoadRxStatus)
.LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
.MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
.LateCollLatched(LateCollLatched), .StartDefer(StartDefer), .DeferLatched(DeferLatched),
.TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
.CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn)
);
 
 
 
endmodule
/trunk/rtl/verilog/eth_macstatus.v
41,6 → 41,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
78,7 → 81,9
RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame, ReceivedPauseFrm,
InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
LoadRxStatus
LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
RetryLimit, LateCollision, LateCollLatched, StartDefer, DeferLatched, TxStartFrm,
StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData
);
 
 
109,7 → 114,20
input [15:0] r_MinFL;
input [15:0] r_MaxFL;
input r_HugEn;
input StartTxDone;
input StartTxAbort;
input [3:0] RetryCnt;
input MTxClk;
input MaxCollisionOccured;
input LateCollision;
input StartDefer;
input TxStartFrm;
input StatePreamble;
input [1:0] StateData;
input CarrierSense;
input TxUsedData;
 
 
output ReceivedLengthOK;
output ReceiveEnd;
output ReceivedPacketGood;
120,7 → 138,13
output DribbleNibble;
output ReceivedPacketTooBig;
output LoadRxStatus;
output [3:0] RetryCntLatched;
output RetryLimit;
output LateCollLatched;
output DeferLatched;
output CarrierSenseLost;
 
 
reg ReceiveEnd;
 
reg LatchedCrcError;
127,6 → 151,11
reg LatchedMRxErr;
reg LoadRxStatus;
reg InvalidSymbol;
reg [3:0] RetryCntLatched;
reg RetryLimit;
reg LateCollLatched;
reg DeferLatched;
reg CarrierSenseLost;
 
wire TakeSample;
wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
289,4 → 318,68
ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
end
 
 
 
// Latched Retry counter for tx status
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryCntLatched <=#Tp 4'h0;
else
if(StartTxDone | StartTxAbort)
RetryCntLatched <=#Tp RetryCnt;
end
 
 
// Latched Retransmission limit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryLimit <=#Tp 4'h0;
else
if(StartTxDone | StartTxAbort)
RetryLimit <=#Tp MaxCollisionOccured;
end
 
 
// Latched Late Collision
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
LateCollLatched <=#Tp 1'b0;
else
if(StartTxDone | StartTxAbort)
LateCollLatched <=#Tp LateCollision;
end
 
 
 
// Latched Defer state
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DeferLatched <=#Tp 1'b0;
else
if(StartDefer & TxUsedData)
DeferLatched <=#Tp 1'b1;
else
if(TxStartFrm)
DeferLatched <=#Tp 1'b0;
end
 
 
// CarrierSenseLost
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
CarrierSenseLost <=#Tp 1'b0;
else
if((StatePreamble | (|StateData)) & ~CarrierSense)
CarrierSenseLost <=#Tp 1'b1;
else
if(TxStartFrm)
CarrierSenseLost <=#Tp 1'b0;
end
 
 
endmodule

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