OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

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    from Rev 65 to Rev 66
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Rev 65 → Rev 66

/trunk/bench/verilog/tb_eth_top.v
1,4 → 1,4
///////////3///////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// tb_eth_top.v ////
//// ////
41,6 → 41,12
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9 2002/02/14 20:14:38 billditt
// Added separate tests for Multicast, Unicast, Broadcast
//
// Revision 1.8 2002/02/12 20:24:00 mohor
// HASH0 and HASH1 register read/write added.
//
// Revision 1.7 2002/02/06 14:11:35 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
135,7 → 141,6
reg MRxErr;
reg MColl;
reg MCrs;
reg RxAbort;
 
reg Mdi_I;
wire Mdo_O;
144,8 → 149,6
 
 
 
reg GSR;
 
reg WishboneBusy;
reg StartTB;
reg [9:0] TxBDIndex;
183,8 → 186,6
//RX
.mrx_clk_pad_i(MRxClk), .mrxd_pad_i(MRxD), .mrxdv_pad_i(MRxDV), .mrxerr_pad_i(MRxErr),
.mcoll_pad_i(MColl), .mcrs_pad_i(MCrs),
.RxAbort(RxAbort), // igor !!! Ta se mora preseliti da bo prisel iz enega izmed modulov. Tu je le zaradi
// testiranja. Pove, kdaj adresa ni ustrezala in se paketi sklirajo, stevci pa resetirajo.
// MIIM
.mdc_pad_o(Mdc_O), .md_pad_i(Mdi_I), .md_pad_o(Mdo_O), .md_padoen_o(Mdo_OE),
221,7 → 222,6
MRxErr = 1'b0;
MColl = 1'b0;
MCrs = 1'b0;
RxAbort = 1'b0;
Mdi_I = 1'b0;
 
WishboneBusy = 1'b0;
239,17 → 239,12
mcd2 = $fopen("ethernet_rx.log");
`endif
WB_RST_I = 1'b1;
GSR = 1'b1;
#100 WB_RST_I = 1'b0;
GSR = 1'b0;
#100 StartTB = 1'b1;
end
 
 
//assign glbl.GSR = GSR;
 
 
 
// Generating WB_CLK_I clock
always
begin
287,10 → 282,7
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
WishboneWrite(32'h0040000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
 
 
 
SendPacket(16'h0015, 1'b0);
SendPacket(16'h0043, 1'b1); // Control frame
SendPacket(16'h0025, 1'b0);
297,7 → 289,6
SendPacket(16'h0045, 1'b0);
SendPacket(16'h0025, 1'b0);
 
 
ReceivePacket(16'h0012, 1'b1); // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
ReceivePacket(16'h0011, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0016, 1'b0); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
345,18 → 336,6
WB_STB_I = 1'b1;
WB_SEL_I = 4'hf;
 
// for(ii=0; (ii<20 & ~WB_ACK_O); ii=ii+1) // Response on the WISHBONE is limited to 20 WB_CLK_I cycles
// begin
// @ (posedge WB_CLK_I);
// end
 
// if(ii==20)
// begin
// $display("\nERROR: Task WishboneWrite(Data=0x%0h, Address=0x%0h): Too late or no appeariance of the WB_ACK_O signal, (Time=%0t)",
// Data, Address, $time);
// #50 $stop;
// end
 
wait(WB_ACK_O); // waiting for acknowledge response
 
// Writing information about the access to the screen
545,7 → 524,6
WishboneBusy = 1;
#1;
WB_DAT_I = {a, b, c, d};
// WB_ADR_I = {20'h20, pp[11:0]};
WB_ADR_I = {22'h02, pp[9:0]};
$display("task WaitingForTxDMARequest: pp=%0d, WB_ADR_I=0x%0h, WB_DAT_I=0x%0h", pp, WB_ADR_I, WB_DAT_I);
 
582,7 → 560,6
wait (~WishboneBusy);
WishboneBusy = 1;
#1;
// WB_ADR_I = {20'h20, rr[11:0]};
WB_ADR_I = {22'h02, rr[9:0]};
$display("task WaitingForRxDMARequest: rr=%0d, WB_ADR_I=0x%0h, WB_DAT_O=0x%0h", rr, WB_ADR_I, WB_DAT_O);
 
701,26 → 678,27
initial
begin
wait(StartTB); // Start of testbench
//IGORS_BOILER_PLATE;
// TestUnicast;
// TestBroadcast;
TestMulticast;
InitializeMemory;
 
// Select which test you want to run:
TestTxAndRx;
// TestUnicast;
// TestBroadcast;
// TestMulticast;
end
 
task IGORS_BOILER_PLATE;
task TestTxAndRx;
begin
$display("\nBegin IGORS_BOILER_PLATE \n");
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 1
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 0
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 1
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR<<2}); // r_Rst = 0
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR<<2}); // r_RxBDAddress = 0x80
 
WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
WishboneWrite(32'h00002463, {26'h0, `ETH_MODER_ADR<<2}); // RxEn, Txen, CrcEn, Pad off, full duplex, r_IFG, promisc ON
 
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR<<2}); //r_TxFlow = 1
 
SendPacket(16'h0010, 1'b0);
SendPacket(16'h0007, 1'b0);
SendPacket(16'h0011, 1'b0);
SendPacket(16'h0012, 1'b0);
SendPacket(16'h0013, 1'b0);
735,21 → 713,11
SendPacket(16'h0025, 1'b0);
SendPacket(16'h0017, 1'b0);
 
// ReceivePacket(16'h0012, 1'b1, 1'b0);
// Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
ReceivePacket(16'h0015, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0016, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0017, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0018, 1'b0, `MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
WishboneWrite(32'h00400000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
WishboneRead({26'h0, `ETH_HASH1_ADR}); // read back
$display("\n Set Hash Filter to accept this Multicast packet, send packets\n");
ReceivePacket(16'h0015, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0016, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0017, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0018, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
 
WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
769,12 → 737,12
WishboneRead({22'h01, (10'h85<<2)}); // Read from RxBD register
WishboneRead({22'h01, (10'h86<<2)}); // Read from RxBD register
WishboneRead({22'h01, (10'h87<<2)}); // Read from RxBD register
 
#100000 $stop;
$display("\nEnd IGORS_BOILER_PLATE \n");
end
endtask //IGORS_BOILER_PLATE
end
endtask //TestTxAndRx
 
 
task TestUnicast;
begin
$display("\nBegin TestUnicast \n");
781,55 → 749,27
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 1
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 0
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
 
WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
 
WishboneWrite(32'h00002043, {26'h0, `ETH_MODER_ADR, 2'h0}); // RxEn, Txen, CrcEn, no Pad, r_IFG, promisc off, broadcast on
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
 
$display("\n This Uniicast packet will be rejected, wrong address in MAC Address Regs\n");
ReceivePacket(16'h0014, 1'b0,`UNICAST_XFR);
SendPacket(16'h0010, 1'b0);
SendPacket(16'h0011, 1'b0);
SendPacket(16'h0012, 1'b0);
SendPacket(16'h0013, 1'b0);
SendPacket(16'h0014, 1'b0);
 
SendPacket(16'h0030, 1'b0);
SendPacket(16'h0031, 1'b0);
SendPacket(16'h0032, 1'b0);
SendPacket(16'h0033, 1'b0);
SendPacket(16'h0025, 1'b0);
SendPacket(16'h0045, 1'b0);
SendPacket(16'h0025, 1'b0);
SendPacket(16'h0017, 1'b0);
 
// ReceivePacket(16'h0012, 1'b1, 1'b0); // Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
$display("\n This Uniicast packet will be rejected, wrong address in MAC Address Regs\n");
ReceivePacket(16'h0015, 1'b0, 1'b0,`UNICAST_XFR);
WishboneWrite(32'h04030200, {26'h0,`ETH_MAC_ADDR0_ADR ,2'h0}); // Mac Address
WishboneWrite(32'h00000605, {26'h0,`ETH_MAC_ADDR1_ADR ,2'h0}); // Mac Address
$display("\n Set Proper Unicast Address in MAC_ADDRESS regs, resend packet\n");
ReceivePacket(16'h0015, 1'b0, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0016, 1'b0, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0017, 1'b0, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0018, 1'b0, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0015, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0016, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0017, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0018, 1'b0,`UNICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
 
WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
 
WishboneRead({24'h04, (8'h0<<2)}); // Read from TxBD register
WishboneRead({24'h04, (8'h1<<2)}); // Read from TxBD register
WishboneRead({24'h04, (8'h2<<2)}); // Read from TxBD register
WishboneRead({24'h04, (8'h3<<2)}); // Read from TxBD register
WishboneRead({24'h04, (8'h4<<2)}); // Read from TxBD register
 
WishboneRead({22'h01, (10'h80<<2)}); // Read from RxBD register
WishboneRead({22'h01, (10'h81<<2)}); // Read from RxBD register
WishboneRead({22'h01, (10'h82<<2)}); // Read from RxBD register
838,6 → 778,8
WishboneRead({22'h01, (10'h85<<2)}); // Read from RxBD register
WishboneRead({22'h01, (10'h86<<2)}); // Read from RxBD register
WishboneRead({22'h01, (10'h87<<2)}); // Read from RxBD register
WishboneRead({22'h01, (10'h88<<2)}); // Read from RxBD register
WishboneRead({22'h01, (10'h89<<2)}); // Read from RxBD register
#100000 $stop;
$display("\nEnd TestUnicast \n");
850,56 → 792,27
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 1
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 0
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
 
WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0}); // RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG
 
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
 
WishboneWrite(32'h00002043, {26'h0, `ETH_MODER_ADR, 2'h0}); // RxEn, Txen, CrcEn, No Pad, r_IFG, promiscuos off, broadcast enable
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); // r_TxFlow = 1
SendPacket(16'h0010, 1'b0);
SendPacket(16'h0011, 1'b0);
SendPacket(16'h0012, 1'b0);
SendPacket(16'h0013, 1'b0);
SendPacket(16'h0014, 1'b0);
 
SendPacket(16'h0030, 1'b0);
SendPacket(16'h0031, 1'b0);
SendPacket(16'h0032, 1'b0);
SendPacket(16'h0033, 1'b0);
SendPacket(16'h0025, 1'b0);
SendPacket(16'h0045, 1'b0);
SendPacket(16'h0025, 1'b0);
SendPacket(16'h0017, 1'b0);
 
// ReceivePacket(16'h0012, 1'b1, 1'b0);
// Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
 
$display("\n This Multicast packet will be rejected by Hash Filter\n");
$display("\n This Multicast packet will be rejected by Hash Filter\n");
ReceivePacket(16'h0015, 1'b0, 1'b0,`MULTICAST_XFR);
ReceivePacket(16'h0014, 1'b0,`MULTICAST_XFR);
WishboneWrite(32'h00400000, {26'h0, `ETH_HASH1_ADR,2'h0}); // set bit 16, multicast hash 36
WishboneRead({26'h0, `ETH_HASH1_ADR}); // read back
WishboneRead({26'h0, `ETH_HASH1_ADR, 2'h0}); // read back
$display("\n Set Hash Filter to accept this Multicast packet, resend packet\n");
ReceivePacket(16'h0015, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0016, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0017, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0018, 1'b0, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0015, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0016, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0017, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0018, 1'b0,`MULTICAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
 
WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
 
WishboneRead({24'h04, (8'h0<<2)}); // Read from TxBD register
WishboneRead({24'h04, (8'h1<<2)}); // Read from TxBD register
WishboneRead({24'h04, (8'h2<<2)}); // Read from TxBD register
WishboneRead({24'h04, (8'h3<<2)}); // Read from TxBD register
WishboneRead({24'h04, (8'h4<<2)}); // Read from TxBD register
 
WishboneRead({22'h01, (10'h80<<2)}); // Read from RxBD register
WishboneRead({22'h01, (10'h81<<2)}); // Read from RxBD register
WishboneRead({22'h01, (10'h82<<2)}); // Read from RxBD register
909,8 → 822,8
WishboneRead({22'h01, (10'h86<<2)}); // Read from RxBD register
WishboneRead({22'h01, (10'h87<<2)}); // Read from RxBD register
 
$display("\nEnd TestMulticast \n");
#100000 $stop;
$display("\nEnd TestMulticast \n");
end
endtask //TestMulticast
 
917,62 → 830,34
 
task TestBroadcast;
begin
$display("\nBegin TestBroadcast \n");
$display("\n\n\nBegin TestBroadcast");
WishboneWrite(32'h00000800, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 1
WishboneWrite(32'h00000000, {26'h0, `ETH_MODER_ADR, 2'h0}); // r_Rst = 0
WishboneWrite(32'h00000080, {26'h0, `ETH_TX_BD_NUM_ADR, 2'h0}); // r_RxBDAddress = 0x80
 
WishboneWrite(32'h0002A44b, {26'h0, `ETH_MODER_ADR, 2'h0});
// RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG, r_Bro = 1 (disabled)
WishboneWrite(32'h0000A04b, {26'h0, `ETH_MODER_ADR, 2'h0}); // PadEn, CrcEn, IFG=accept, Reject Broadcast, TxEn, RxEn
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); // r_TxFlow = 1
 
WishboneWrite(32'h00000004, {26'h0, `ETH_CTRLMODER_ADR, 2'h0}); //r_TxFlow = 1
 
$display("\nThis Broadcast packet will be rejected, r_BRO = 1");
ReceivePacket(16'h0014, 1'b0,`BROADCAST_XFR);
SendPacket(16'h0010, 1'b0);
SendPacket(16'h0011, 1'b0);
SendPacket(16'h0012, 1'b0);
SendPacket(16'h0013, 1'b0);
SendPacket(16'h0014, 1'b0);
$display("\nSet r_Bro = 0, resend packet");
WishboneWrite(32'h0000A043, {26'h0, `ETH_MODER_ADR, 2'h0}); // PadEn, CrcEn, IFG=accept, Accept Broadcast, TxEn, RxEn
ReceivePacket(16'h0015, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
SendPacket(16'h0030, 1'b0);
SendPacket(16'h0031, 1'b0);
SendPacket(16'h0032, 1'b0);
SendPacket(16'h0033, 1'b0);
SendPacket(16'h0025, 1'b0);
SendPacket(16'h0045, 1'b0);
SendPacket(16'h0025, 1'b0);
SendPacket(16'h0017, 1'b0);
$display("\n This Broadcast packet will be rejected, r_BRO = 1");
WishboneWrite(32'h0000A04b, {26'h0, `ETH_MODER_ADR, 2'h0}); // PadEn, CrcEn, IFG=accept, Reject Broadcast, TxEn, RxEn
ReceivePacket(16'h0016, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0017, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
// ReceivePacket(16'h0012, 1'b1, 1'b0);
// Initializes RxBD and then Sends a control packet on the MRxD[3:0] signals.
$display("\n Set r_Bro = 0, resend packet");
WishboneWrite(32'h0000A043, {26'h0, `ETH_MODER_ADR, 2'h0}); // PadEn, CrcEn, IFG=accept, Accept Broadcast, TxEn, RxEn
ReceivePacket(16'h0018, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
$display("\n This Broadcast packet will be rejected ,r_BRO set\n");
ReceivePacket(16'h0015, 1'b0, 1'b0,`BROADCAST_XFR);
WishboneWrite(32'h0002A443, {26'h0, `ETH_MODER_ADR, 2'h0});
// RxEn, Txen, FullD, CrcEn, Pad, DmaEn, r_IFG, r_Bro
$display("\n Set r_Bro, resend packet\n");
ReceivePacket(16'h0015, 1'b0, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0016, 1'b0, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0017, 1'b0, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
ReceivePacket(16'h0018, 1'b0, 1'b0,`BROADCAST_XFR); // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
 
repeat(5000) @ (posedge MRxClk); // Waiting some time for all accesses to finish before reading out the statuses.
 
WishboneRead({26'h0, `ETH_MODER_ADR}); // Read from MODER register
 
WishboneRead({24'h04, (8'h0<<2)}); // Read from TxBD register
WishboneRead({24'h04, (8'h1<<2)}); // Read from TxBD register
WishboneRead({24'h04, (8'h2<<2)}); // Read from TxBD register
WishboneRead({24'h04, (8'h3<<2)}); // Read from TxBD register
WishboneRead({24'h04, (8'h4<<2)}); // Read from TxBD register
 
WishboneRead({22'h01, (10'h80<<2)}); // Read from RxBD register
WishboneRead({22'h01, (10'h81<<2)}); // Read from RxBD register
WishboneRead({22'h01, (10'h82<<2)}); // Read from RxBD register
987,12 → 872,7
end
endtask //TestBroadcast
 
//integer ijk;
 
//initial
//ijk = 0; // for stoping generation of the m_wb_ack_i signal at the right moment so we get underrun
 
// Answering to master Wishbone requests
always @ (posedge WB_CLK_I)
begin
if(m_wb_cyc_o & m_wb_stb_o) // Add valid address range
999,17 → 879,11
begin
repeat(3) @ (posedge WB_CLK_I);
begin
// if(ijk==41)
// begin
// repeat(1000) @ (posedge WB_CLK_I);
// end
// else
m_wb_ack_i <=#Tp 1'b1;
m_wb_ack_i <=#Tp 1'b1;
if(~m_wb_we_o)
begin
#Tp m_wb_dat_i = m_wb_adr_o + 1'b1; // For easier following of the data
$fdisplay(mcd1, "(%0t) master read (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_i);
// ijk = ijk + 1;
end
else
$fdisplay(mcd2, "(%0t) master write (0x%0x) = 0x%0x", $time, m_wb_adr_o, m_wb_dat_o);
1059,8 → 933,8
if(Address[9:2] < tb_eth_top.ethtop.r_TxBDNum)
begin
$write("\n(%0t) Write to TxBD (Data: 0x%x, TxBD Addr: 0x%0x)", $time, Data, Address);
if(Data[9])
$write("(%0t) Send Control packet (PAUSE = 0x%0h)\n", $time, Data[31:16]);
if(Address[9:2] == tb_eth_top.ethtop.r_TxBDNum-2'h2)
$write("(%0t) Send Control packet\n", $time);
end
else
$write("\n(%0t) Write to RxBD (Data: 0x%x, RxBD Addr: 0x%0x)", $time, Data, Address);
1139,8 → 1013,7
WishboneWrite(TempData, TempAddr); // buffer pointer
 
 
TempAddr = {22'h01, (TxBDIndex<<2)}; // igor !!! zbrisi spodnjo vrstico
// TempAddr = {22'h01, 10'b1010010100};
TempAddr = {22'h01, (TxBDIndex<<2)};
 
TempData = {Length[15:0], 1'b1, 1'b0, Wrap, 3'h0, ControlFrame, 1'b0, TxBDIndex[7:0]}; // Ready and Wrap = 1
 
1159,7 → 1032,6
task ReceivePacket; // Initializes RxBD and then generates traffic on the MRxD[3:0] signals.
input [15:0] LengthRx;
input RxControlFrame;
input Abort;
input [31:0] TransferType; //Broadcast,Unicast,Multicast
reg WrapRx;
reg [31:0] TempRxAddr;
1195,7 → 1067,7
if(RxControlFrame)
GetControlDataOnMRxD(LengthRx); // LengthRx = PAUSE timer value.
else
GetDataOnMRxD(LengthRx, Abort, TransferType); // LengthRx bytes is comming on MRxD[3:0] signals
GetDataOnMRxD(LengthRx, TransferType); // LengthRx bytes is comming on MRxD[3:0] signals
end
 
end
1204,7 → 1076,6
 
task GetDataOnMRxD;
input [15:0] Len;
input abort;
input [31:0] TransferType;
integer tt;
 
1230,16 → 1101,13
MRxD = 4'hf;
else
MRxD=tt[3:0]; // Multicast transfer
if(tt==9)
RxAbort<=#1 abort;
@ (posedge MRxClk);
 
@ (posedge MRxClk);
if(TransferType == `BROADCAST_XFR && tt < 7)
MRxD = 4'hf;
else
MRxD=tt[7:4];
RxAbort<=#1 0;
end
 
@ (posedge MRxClk);
1256,8 → 1124,7
integer tt;
 
begin
//Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
Packet = 128'h10082C000010_deadbeef0013_8880_0010; // 0180c2000001 + 8808 + 0001
Crc = 32'h6014fe08; // not a correct value
@ (posedge MRxClk);
1310,6 → 1177,17
MRxDV=1'b0;
end
endtask
 
task InitializeMemory;
reg [9:0] mem_addr;
begin
for(mem_addr=0; mem_addr<=10'h0ff; mem_addr=mem_addr+1'b1)
WishboneWrite(32'h0, {22'h01, mem_addr<<2}); // Writing status to RxBD
end
endtask
 
 
`endif
 
 

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