URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 69 to Rev 70
- ↔ Reverse comparison
Rev 69 → Rev 70
/trunk/rtl/verilog/eth_top.v
41,6 → 41,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.19 2002/02/16 14:03:44 mohor |
// Registered trimmed. Unused registers removed. |
// |
// Revision 1.18 2002/02/16 13:06:33 mohor |
// EXTERNAL_DMA used instead of WISHBONE_DMA. |
// |
132,10 → 135,9
|
// WISHBONE slave |
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o, |
wb_ack_i, |
|
`ifdef EXTERNAL_DMA |
wb_req_o, wb_nd_o, wb_rd_o, |
wb_ack_i, wb_req_o, wb_nd_o, wb_rd_o, |
`else |
// WISHBONE master |
m_wb_adr_o, m_wb_sel_o, m_wb_we_o, |
178,6 → 180,7
|
`ifdef EXTERNAL_DMA |
// DMA |
input [1:0] wb_ack_i; // DMA acknowledge input |
output [1:0] wb_req_o; // DMA request output |
output [1:0] wb_nd_o; // DMA force new descriptor output |
output wb_rd_o; // DMA restart descriptor output |
194,7 → 197,6
input m_wb_err_i; |
`endif |
|
input [1:0] wb_ack_i; // DMA acknowledge input |
|
// Tx |
input mtx_clk_pad_i; // Transmit clock (from PHY) |
/trunk/rtl/verilog/eth_macstatus.v
41,6 → 41,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.7 2002/02/15 17:07:39 mohor |
// Status was not written correctly when frames were discarted because of |
// address mismatch. |
// |
// Revision 1.6 2002/02/11 09:18:21 mohor |
// Tx status is written back to the BD. |
// |
308,7 → 312,6
|
|
reg ReceivedPacketTooBig; |
assign ReceivedLengthOK = RxByteCnt[15:0] > 63 & RxByteCnt[15:0] < 1519; |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |