URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
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- This comparison shows the changes necessary to convert path
/ethmac/tags/rel_26/sim/rtl_sim
- from Rev 335 to Rev 338
- ↔ Reverse comparison
Rev 335 → Rev 338
/ncsim_sim/log/eth_tb.log
0,0 → 1,2271
========================== ETHERNET IP Core Testbench results =========================== |
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Heading: ACCESS TO MAC REGISTERS TEST |
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At time: 68509000 |
Test: TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS ) |
reported *SUCCESSFULL*! |
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************************************************************************************* |
At time: 302749000 |
Test: TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
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************************************************************************************* |
At time: 5383309000 |
Test: TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS ) |
reported *SUCCESSFULL*! |
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At time: 5399539000 |
Test: TEST 3: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC |
reported *SUCCESSFULL*! |
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At time: 5645629000 |
Test: TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC |
reported *SUCCESSFULL*! |
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Heading: MIIM MODULE TEST |
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At time: 7595117000 |
Test: TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES |
reported *SUCCESSFULL*! |
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At time: 7622149000 |
Test: TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS |
reported *SUCCESSFULL*! |
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At time: 7655119000 |
Test: TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS ) |
reported *SUCCESSFULL*! |
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************************************************************************************* |
At time: 7673959000 |
Test: TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE |
reported *SUCCESSFULL*! |
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At time: 7749859000 |
Test: TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE ) |
reported *SUCCESSFULL*! |
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************************************************************************************* |
At time: 7825759000 |
Test: TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE ) |
reported *SUCCESSFULL*! |
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************************************************************************************* |
At time: 8067259000 |
Test: TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE ) |
reported *SUCCESSFULL*! |
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************************************************************************************* |
At time: 8071969000 |
Test: TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA ) |
reported *SUCCESSFULL*! |
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************************************************************************************* |
At time: 8081389000 |
Test: TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE |
reported *SUCCESSFULL*! |
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At time: 8976619000 |
Test: TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 9882439000 |
Test: TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 10098649000 |
Test: TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE ) |
reported *SUCCESSFULL*! |
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At time: 10315609000 |
Test: TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE ) |
reported *SUCCESSFULL*! |
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************************************************************************************* |
At time: 10532569000 |
Test: TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE ) |
reported *SUCCESSFULL*! |
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************************************************************************************* |
At time: 10676539000 |
Test: TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE ) |
reported *SUCCESSFULL*! |
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************************************************************************************* |
At time: 12186559000 |
Test: TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 13113619000 |
Test: TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE ) |
reported *SUCCESSFULL*! |
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|
************************************************************************************* |
At time: 14603599000 |
Test: TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
|
NOTE: PHY generates ideal Carrier sense and Collision signals for following tests |
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Heading: MAC FULL DUPLEX TRANSMIT TEST |
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At time: 15302239000 |
Test: TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps ) |
reported *SUCCESSFULL*! |
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************************************************************************************* |
At time: 15936679000 |
Test: TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps ) |
reported *SUCCESSFULL*! |
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|
************************************************************************************* |
At time: 49727119000 |
Test: TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 53442319000 |
Test: TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
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|
************************************************************************************* |
At time: 95351355000 |
Test: TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 99968955000 |
Test: TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 104360595000 |
Test: TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 104966115000 |
Test: TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 108053235000 |
Test: TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 108528075000 |
Test: TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 112357635000 |
Test: TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
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|
************************************************************************************* |
At time: 112755195000 |
Test: TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
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************************************************************************************* |
At time: 113082915000 |
Test: TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 113125035000 |
Test: TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 116433315000 |
Test: TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 116773995000 |
Test: TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 225419715000 |
Test: TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 236329395000 |
Test: TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 238386915000 |
Test: TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 238653435000 |
Test: TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 242447355000 |
Test: TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 242923275000 |
Test: TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
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*************************************************************************************** |
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Heading: MAC FULL DUPLEX RECEIVE TEST |
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*************************************************************************************** |
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************************************************************************************* |
At time: 252557359000 |
Test: TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 254085799000 |
Test: TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 294264649000 |
Test: TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 299591329000 |
Test: TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 333243169000 |
Test: TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 336818689000 |
Test: TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 378320475000 |
Test: TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 382758795000 |
Test: TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 386187495000 |
Test: TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 386657745000 |
Test: TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 387208159000 |
Test: TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
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************************************************************************************* |
At time: 387288679000 |
Test: TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
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************************************************************************************* |
At time: 387359689000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 387423768000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
WB INT signal should not be set |
************************************************************************************* |
|
************************************************************************************* |
At time: 387424129000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Any of interrupts (except Receive Buffer) was set |
************************************************************************************* |
|
************************************************************************************* |
At time: 387487968000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
WB INT signal should not be set |
************************************************************************************* |
|
************************************************************************************* |
At time: 387488329000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Any of interrupts (except Receive Buffer) was set |
************************************************************************************* |
|
************************************************************************************* |
At time: 387492409000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 387492529000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Buffer Error was not set |
************************************************************************************* |
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************************************************************************************* |
At time: 387492529000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Other interrupts (except Receive Buffer Error) were set |
************************************************************************************* |
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************************************************************************************* |
At time: 387562849000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 387562849000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong length of the packet out from PHY |
************************************************************************************* |
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************************************************************************************* |
At time: 387562867000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong data of the received packet |
************************************************************************************* |
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************************************************************************************* |
At time: 387562969000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Buffer was not set |
************************************************************************************* |
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************************************************************************************* |
At time: 387562969000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Other interrupts (except Receive Buffer) were set |
************************************************************************************* |
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************************************************************************************* |
At time: 387633408000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
WB INT signal should not be set |
************************************************************************************* |
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************************************************************************************* |
At time: 387633769000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Any of interrupts (except Receive Buffer) was set |
************************************************************************************* |
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************************************************************************************* |
At time: 387637849000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
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************************************************************************************* |
At time: 387637969000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Buffer Error was not set |
************************************************************************************* |
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************************************************************************************* |
At time: 387637969000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Other interrupts (except Receive Buffer Error) were set |
************************************************************************************* |
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************************************************************************************* |
At time: 387708409000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
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************************************************************************************* |
At time: 387708409000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong length of the packet out from PHY |
************************************************************************************* |
|
************************************************************************************* |
At time: 387708427000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong data of the received packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 387708529000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Buffer was not set |
************************************************************************************* |
|
************************************************************************************* |
At time: 387708529000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Other interrupts (except Receive Buffer) were set |
************************************************************************************* |
|
************************************************************************************* |
At time: 387788208000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
WB INT signal should not be set |
************************************************************************************* |
|
************************************************************************************* |
At time: 387788569000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Any of interrupts (except Receive Buffer) was set |
************************************************************************************* |
|
************************************************************************************* |
At time: 387792649000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 387792769000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Buffer Error was not set |
************************************************************************************* |
|
************************************************************************************* |
At time: 387792769000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Other interrupts (except Receive Buffer Error) were set |
************************************************************************************* |
|
************************************************************************************* |
At time: 387872809000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 387872809000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong length of the packet out from PHY |
************************************************************************************* |
|
************************************************************************************* |
At time: 387872830000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong data of the received packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 387872929000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Buffer was not set |
************************************************************************************* |
|
************************************************************************************* |
At time: 387872929000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Other interrupts (except Receive Buffer) were set |
************************************************************************************* |
|
************************************************************************************* |
At time: 387952849000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 387952849000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong length of the packet out from PHY |
************************************************************************************* |
|
************************************************************************************* |
At time: 387952870000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong data of the received packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 387952969000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Buffer was not set |
************************************************************************************* |
|
************************************************************************************* |
At time: 387952969000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Other interrupts (except Receive Buffer) were set |
************************************************************************************* |
|
************************************************************************************* |
At time: 388115689000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 388234969000 |
Test: TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
*************************************************************************************** |
*************************************************************************************** |
Heading: MAC FULL DUPLEX FLOW CONTROL TEST |
*************************************************************************************** |
*************************************************************************************** |
|
************************************************************************************* |
At time: 397626071000 |
Test: TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 398657171000 |
Test: TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 399868939000 |
Test: TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 400018579000 |
Test: TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 438761899000 |
Test: TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 443750959000 |
Test: TEST 5: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
*************************************************************************************** |
*************************************************************************************** |
Heading: MAC HALF DUPLEX FLOW TEST |
*************************************************************************************** |
*************************************************************************************** |
|
************************************************************************************* |
At time: 443899119000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 444057159000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 444222399000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 444387999000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 444564339000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 444730779000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 444897579000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 445064679000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 445100407000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
************************************************************************************* |
|
************************************************************************************* |
At time: 445293579000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 445319207000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
************************************************************************************* |
|
************************************************************************************* |
At time: 445461579000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 445680339000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 445899039000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 445941549000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 445958709000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 445976589000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 445994469000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446019369000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446037369000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446055369000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446073369000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446098269000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446116269000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446134389000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446152629000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446177769000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446196129000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446214489000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446232849000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446257989000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446276349000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446294709000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446313189000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446338689000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446357289000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446376009000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446394549000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446420169000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446439009000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446457849000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446476689000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446502309000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446521149000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446539989000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446558949000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446584929000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446604009000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446623209000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446642229000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446668329000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446687649000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446706969000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446726289000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446752389000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446771709000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446791029000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446810469000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446836929000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446856489000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446876169000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 446880487000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
************************************************************************************* |
|
************************************************************************************* |
At time: 446895669000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 446906887000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
************************************************************************************* |
|
************************************************************************************* |
At time: 446922249000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 446947089000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 446966889000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
|
NOTE: PHY generates 'real delayed' Carrier sense and Collision signals for following tests |
|
*************************************************************************************** |
*************************************************************************************** |
Heading: MAC FULL DUPLEX TRANSMIT TEST |
*************************************************************************************** |
*************************************************************************************** |
|
************************************************************************************* |
At time: 447667519000 |
Test: TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 448301959000 |
Test: TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 482092399000 |
Test: TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 485807599000 |
Test: TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 527716635000 |
Test: TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 532334235000 |
Test: TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 536725875000 |
Test: TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 537331395000 |
Test: TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 540418515000 |
Test: TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 540893355000 |
Test: TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 544722915000 |
Test: TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 545120475000 |
Test: TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 545448195000 |
Test: TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 545490315000 |
Test: TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 548798595000 |
Test: TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 549139275000 |
Test: TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 657784995000 |
Test: TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 668694675000 |
Test: TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 670752195000 |
Test: TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 671018715000 |
Test: TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 674812635000 |
Test: TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 675288555000 |
Test: TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
*************************************************************************************** |
*************************************************************************************** |
Heading: MAC FULL DUPLEX RECEIVE TEST |
*************************************************************************************** |
*************************************************************************************** |
|
************************************************************************************* |
At time: 684922639000 |
Test: TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 686451079000 |
Test: TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 726629929000 |
Test: TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 731956609000 |
Test: TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 765608449000 |
Test: TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 769183969000 |
Test: TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 810685755000 |
Test: TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 815124075000 |
Test: TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 818552775000 |
Test: TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 819023025000 |
Test: TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 819573439000 |
Test: TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 819653959000 |
Test: TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 819724969000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 819789048000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
WB INT signal should not be set |
************************************************************************************* |
|
************************************************************************************* |
At time: 819789409000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Any of interrupts (except Receive Buffer) was set |
************************************************************************************* |
|
************************************************************************************* |
At time: 819853248000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
WB INT signal should not be set |
************************************************************************************* |
|
************************************************************************************* |
At time: 819853609000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Any of interrupts (except Receive Buffer) was set |
************************************************************************************* |
|
************************************************************************************* |
At time: 819857689000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 819857809000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Buffer Error was not set |
************************************************************************************* |
|
************************************************************************************* |
At time: 819857809000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Other interrupts (except Receive Buffer Error) were set |
************************************************************************************* |
|
************************************************************************************* |
At time: 819928129000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 819928129000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong length of the packet out from PHY |
************************************************************************************* |
|
************************************************************************************* |
At time: 819928147000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong data of the received packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 819928249000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Buffer was not set |
************************************************************************************* |
|
************************************************************************************* |
At time: 819928249000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Other interrupts (except Receive Buffer) were set |
************************************************************************************* |
|
************************************************************************************* |
At time: 819998688000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
WB INT signal should not be set |
************************************************************************************* |
|
************************************************************************************* |
At time: 819999049000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Any of interrupts (except Receive Buffer) was set |
************************************************************************************* |
|
************************************************************************************* |
At time: 820003129000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 820003249000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Buffer Error was not set |
************************************************************************************* |
|
************************************************************************************* |
At time: 820003249000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Other interrupts (except Receive Buffer Error) were set |
************************************************************************************* |
|
************************************************************************************* |
At time: 820073689000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 820073689000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong length of the packet out from PHY |
************************************************************************************* |
|
************************************************************************************* |
At time: 820073707000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong data of the received packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 820073809000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Buffer was not set |
************************************************************************************* |
|
************************************************************************************* |
At time: 820073809000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Other interrupts (except Receive Buffer) were set |
************************************************************************************* |
|
************************************************************************************* |
At time: 820153488000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
WB INT signal should not be set |
************************************************************************************* |
|
************************************************************************************* |
At time: 820153849000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Any of interrupts (except Receive Buffer) was set |
************************************************************************************* |
|
************************************************************************************* |
At time: 820157929000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 820158049000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Buffer Error was not set |
************************************************************************************* |
|
************************************************************************************* |
At time: 820158049000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Other interrupts (except Receive Buffer Error) were set |
************************************************************************************* |
|
************************************************************************************* |
At time: 820238089000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 820238089000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong length of the packet out from PHY |
************************************************************************************* |
|
************************************************************************************* |
At time: 820238110000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong data of the received packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 820238209000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Buffer was not set |
************************************************************************************* |
|
************************************************************************************* |
At time: 820238209000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Other interrupts (except Receive Buffer) were set |
************************************************************************************* |
|
************************************************************************************* |
At time: 820318129000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 820318129000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong length of the packet out from PHY |
************************************************************************************* |
|
************************************************************************************* |
At time: 820318150000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Wrong data of the received packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 820318249000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Buffer was not set |
************************************************************************************* |
|
************************************************************************************* |
At time: 820318249000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
Other interrupts (except Receive Buffer) were set |
************************************************************************************* |
|
************************************************************************************* |
At time: 820480969000 |
Test: TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 820600249000 |
Test: TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
*************************************************************************************** |
*************************************************************************************** |
Heading: MAC FULL DUPLEX FLOW CONTROL TEST |
*************************************************************************************** |
*************************************************************************************** |
|
************************************************************************************* |
At time: 829991351000 |
Test: TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 831022451000 |
Test: TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 832234219000 |
Test: TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 832383859000 |
Test: TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 871127179000 |
Test: TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
************************************************************************************* |
At time: 876116239000 |
Test: TEST 5: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 100Mbps ) |
reported *SUCCESSFULL*! |
************************************************************************************* |
|
*************************************************************************************** |
*************************************************************************************** |
Heading: MAC HALF DUPLEX FLOW TEST |
*************************************************************************************** |
*************************************************************************************** |
|
************************************************************************************* |
At time: 876264399000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 876422439000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 876587679000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 876753279000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 876929619000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 877096059000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 877262859000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 877429959000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 877607619000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 877635687000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
************************************************************************************* |
|
************************************************************************************* |
At time: 877826379000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 877854487000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
************************************************************************************* |
|
************************************************************************************* |
At time: 877994859000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 878163519000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 878264599000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Receive packet should be accepted |
************************************************************************************* |
|
************************************************************************************* |
At time: 878342599000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Wrong length of the packet out from PHY |
************************************************************************************* |
|
************************************************************************************* |
At time: 878342616000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Wrong data of the received packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 878342616000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878342859000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 878342959000 |
Test: TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
*FAILED* because |
Interrupt Receive Error was not set |
************************************************************************************* |
|
************************************************************************************* |
At time: 878385939000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878403099000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878420979000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878438859000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878463639000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878481519000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878499399000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878517399000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878542299000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878560299000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878578419000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878596539000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878621559000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878639799000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878658039000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878676399000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878701539000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878719899000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878738259000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878756739000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878782119000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878800599000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878819199000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878837919000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878863419000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878882139000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878900859000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878919699000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878945439000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878964279000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 878983119000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879002079000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879027939000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879046899000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879065979000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879085059000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879111039000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879130239000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879149439000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879168759000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879194859000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879214179000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879233499000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879252939000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879279279000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879298719000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879318279000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879322807000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
************************************************************************************* |
|
************************************************************************************* |
At time: 879342999000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 879369459000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
TX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879374007000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
************************************************************************************* |
|
************************************************************************************* |
At time: 879389139000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 879408819000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 879420079000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Receive packet should be accepted |
************************************************************************************* |
|
************************************************************************************* |
At time: 879428239000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Wrong length of the packet out from PHY |
************************************************************************************* |
|
************************************************************************************* |
At time: 879428256000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Wrong data of the received packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 879428256000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
RX buffer descriptor status is not correct |
************************************************************************************* |
|
************************************************************************************* |
At time: 879428499000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Wrong data of the transmitted packet |
************************************************************************************* |
|
************************************************************************************* |
At time: 879428599000 |
Test: TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
*FAILED* because |
Interrupt Receive Error was not set |
************************************************************************************* |
|
**************************** Ethernet MAC test summary ********************************** |
Tests performed: 111 |
Failed tests : 6 |
Successfull tests: 105 |
**************************** Ethernet MAC test summary ********************************** |
/ncsim_sim/log/tb_eth_display.log
0,0 → 1,2165
ncsim: 04.10-b001: (c) Copyright 1995-2002 Cadence Design Systems, Inc. |
Loading snapshot worklib.ethernet:fun .................... Done |
ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc |
ncsim> run |
|
ACCESS TO MAC REGISTERS TEST |
Time: 62387000 |
TEST 0: BYTE SELECTS ON 3 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS ) |
Time: 68509000 |
TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS ) |
->registers tested with 0, 1, 2, 3 and 4 bus delay cycles |
Time: 302749000 |
TEST 2: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS ) |
->buffer descriptors tested with 0 bus delay |
->buffer descriptors tested with 1 bus delay cycle |
->buffer descriptors tested with 2 bus delay cycles |
->buffer descriptors tested with 3 bus delay cycles |
Time: 5383309000 |
TEST 3: MAX REG. VALUES AND REG. VALUES AFTER WRITING INVERSE RESET VALUES AND HARD RESET OF THE MAC |
Time: 5399539000 |
TEST 4: BUFFER DESC. RAM PRESERVING VALUES AFTER HARD RESET OF THE MAC AND RESETING THE LOGIC |
|
MIIM MODULE TEST |
Time: 5645717000 |
TEST 0: CLOCK DIVIDER OF MII MANAGEMENT MODULE WITH ALL POSSIBLE FREQUENCES |
Time: 7595117000 |
TEST 1: VARIOUS READINGS FROM 'REAL' PHY REGISTERS |
Time: 7622149000 |
TEST 2: VARIOUS WRITINGS TO 'REAL' PHY REGISTERS ( CONTROL AND NON WRITABLE REGISTERS ) |
Time: 7655119000 |
TEST 3: RESET PHY THROUGH MII MANAGEMENT MODULE |
Time: 7673959000 |
TEST 4: 'WALKING ONE' ACROSS PHY ADDRESS ( WITH AND WITHOUT PREAMBLE ) |
Time: 7749859000 |
TEST 5: 'WALKING ONE' ACROSS PHY'S REGISTER ADDRESS ( WITH AND WITHOUT PREAMBLE ) |
Time: 7825759000 |
TEST 6: 'WALKING ONE' ACROSS PHY'S DATA ( WITH AND WITHOUT PREAMBLE ) |
Time: 8067259000 |
TEST 7: READING FROM PHY WITH WRONG PHY ADDRESS ( HOST READING HIGH 'Z' DATA ) |
=> Two error lines will be displayed from WB Bus Monitor, because correct HIGH Z data was read |
Time: 8071935000 |
tb_ethernet.wb_eth_slave_bus_mon.message_out, Slave provided invalid data during read and qualified it with ACK_I |
Byte select value: SEL_O = 1111, Data bus value: DAT_I = 0000zzzz |
Time: 8071969000 |
TEST 8: WRITING TO PHY WITH WRONG PHY ADDRESS AND READING FROM CORRECT ONE |
Time: 8081389000 |
TEST 9: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER READ REQUEST ( WITH AND WITHOUT PREAMBLE ) |
Time: 8976619000 |
TEST 10: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER WRITE REQUEST ( WITH AND WITHOUT PREAMBLE ) |
Time: 9882439000 |
TEST 11: BUSY AND NVALID STATUS DURATIONS DURING WRITE ( WITH AND WITHOUT PREAMBLE ) |
Time: 10098649000 |
TEST 12: BUSY AND NVALID STATUS DURATIONS DURING READ ( WITH AND WITHOUT PREAMBLE ) |
Time: 10315609000 |
TEST 13: BUSY AND NVALID STATUS DURATIONS DURING SCAN ( WITH AND WITHOUT PREAMBLE ) |
Time: 10532569000 |
TEST 14: SCAN STATUS FROM PHY WITH DETECTING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE ) |
Time: 10676539000 |
TEST 15: SCAN STATUS FROM PHY WITH SLIDING LINK-FAIL BIT ( WITH AND WITHOUT PREAMBLE ) |
Time: 12186559000 |
TEST 16: SLIDING STOP SCAN COMMAND IMMEDIATELY AFTER SCAN REQUEST ( WITH AND WITHOUT PREAMBLE ) |
Time: 13113619000 |
TEST 17: SLIDING STOP SCAN COMMAND AFTER 2. SCAN ( WITH AND WITHOUT PREAMBLE ) |
|
=========================================================================== |
PHY generates ideal Carrier sense and Collision signals for following tests |
=========================================================================== |
|
MAC FULL DUPLEX TRANSMIT TEST |
Time: 14603687000 |
TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps ) |
Time: 15302239000 |
TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps ) |
Time: 15936679000 |
TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps ) |
pads appending to packets is NOT selected |
->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte) |
pads appending to packets is selected |
->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes) |
pads appending to packets is NOT selected |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
Time: 49727119000 |
TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps ) |
pads appending to packets is NOT selected |
->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte) |
pads appending to packets is selected |
->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes) |
pads appending to packets is NOT selected |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
Time: 53442319000 |
TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps ) |
pads appending to packets is NOT selected |
using only TX BD 0 out of 128 BDs assigned to TX (wrap at first BD - TX BD 0) |
->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte) |
->all packets were send from TX BD 0 |
pads appending to packets is NOT selected |
using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127) |
->packets with lengths from 72 to 192 are checked (length increasing by 1 byte) |
->packets were send from TX BD 0 to TX BD 120 respectively |
pads appending to packets is selected |
using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127) |
->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes) |
->packets were send from TX BD 121 to TX BD 127 and from TX BD 0 to TX BD 2 respectively |
pads appending to packets is NOT selected |
using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127) |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
->packets were send from TX BD 3 to TX BD 18 respectively |
Time: 95351355000 |
TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps ) |
pads appending to packets is NOT selected |
using only TX BD 0 out of 128 BDs assigned to TX (wrap at first BD - TX BD 0) |
->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte) |
->all packets were send from TX BD 0 |
pads appending to packets is NOT selected |
using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127) |
->packets with lengths from 72 to 192 are checked (length increasing by 1 byte) |
->packets were send from TX BD 0 to TX BD 120 respectively |
pads appending to packets is selected |
using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127) |
->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes) |
->packets were send from TX BD 121 to TX BD 127 and from TX BD 0 to TX BD 2 respectively |
pads appending to packets is NOT selected |
using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127) |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
->packets were send from TX BD 3 to TX BD 18 respectively |
Time: 99968955000 |
TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps ) |
pads appending to packets is selected |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte) |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packet with length 4 is not transmitted (length increasing by 1 byte) |
->packets with lengths from 5 to 9 are checked (length increasing by 1 byte) |
using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3) |
->packets with lengths from 10 to 17 are checked (length increasing by 1 byte) |
using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4) |
->packets with lengths from 18 to 27 are checked (length increasing by 1 byte) |
using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5) |
->packets with lengths from 28 to 40 are checked (length increasing by 1 byte) |
using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6) |
->packets with lengths from 41 to 54 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7) |
->packets with lengths from 55 to 69 are checked (length increasing by 1 byte) |
Time: 104360595000 |
TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps ) |
pads appending to packets is selected |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte) |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packet with length 4 is not transmitted (length increasing by 1 byte) |
->packets with lengths from 5 to 9 are checked (length increasing by 1 byte) |
using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3) |
->packets with lengths from 10 to 17 are checked (length increasing by 1 byte) |
using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4) |
->packets with lengths from 18 to 27 are checked (length increasing by 1 byte) |
using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5) |
->packets with lengths from 28 to 40 are checked (length increasing by 1 byte) |
using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6) |
->packets with lengths from 41 to 54 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7) |
->packets with lengths from 55 to 69 are checked (length increasing by 1 byte) |
Time: 104966115000 |
TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps ) |
pads appending to packets is not selected (except for 0x23) |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte) |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packet with length 4 is not transmitted (length increasing by 1 byte) |
->packets with lengths from 5 to 9 are checked (length increasing by 1 byte) |
using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3) |
->packets with lengths from 10 to 17 are checked (length increasing by 1 byte) |
using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4) |
->packets with lengths from 18 to 27 are checked (length increasing by 1 byte) |
using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5) |
->packets with lengths from 28 to 40 are checked (length increasing by 1 byte) |
using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6) |
->packets with lengths from 41 to 54 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7) |
->packets with lengths from 55 to 69 are checked (length increasing by 1 byte) |
Time: 108053235000 |
TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps ) |
pads appending to packets is not selected (except for 0x23) |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte) |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packet with length 4 is not transmitted (length increasing by 1 byte) |
->packets with lengths from 5 to 9 are checked (length increasing by 1 byte) |
using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3) |
->packets with lengths from 10 to 17 are checked (length increasing by 1 byte) |
using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4) |
->packets with lengths from 18 to 27 are checked (length increasing by 1 byte) |
using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5) |
->packets with lengths from 28 to 40 are checked (length increasing by 1 byte) |
using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6) |
->packets with lengths from 41 to 54 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7) |
->packets with lengths from 55 to 69 are checked (length increasing by 1 byte) |
Time: 108528075000 |
TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps ) |
->packet with length 1535 sent |
->packet with length 1536 sent |
->packet with length 1537 sent |
->packet with length 104 sent |
Time: 112357635000 |
TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps ) |
->packet with length 1535 sent |
->packet with length 1536 sent |
->packet with length 1537 sent |
->packet with length 104 sent |
Time: 112755195000 |
TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps ) |
->packet with length 116 sent |
->packet with length 117 sent |
->packet with length 118 sent |
Time: 113082915000 |
TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps ) |
->packet with length 116 sent |
->packet with length 117 sent |
->packet with length 118 sent |
Time: 113125035000 |
TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps ) |
->packet with length 1358 sent |
->packet with length 1359 sent |
->packet with length 1360 sent |
Time: 116433315000 |
TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps ) |
->packet with length 1358 sent |
->packet with length 1359 sent |
->packet with length 1360 sent |
Time: 116773995000 |
TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps ) |
i_length = 1531 |
eth_phy length = 1535 |
->packet with length 1535 sent |
i_length = 1532 |
eth_phy length = 1536 |
->packet with length 1536 sent |
i_length = 1533 |
eth_phy length = 1537 |
->packet with length 1537 sent |
i_length = 65530 |
eth_phy length = 65534 |
->packet with length 65534 sent |
i_length = 65531 |
eth_phy length = 65535 |
->packet with length 65535 sent |
Time: 225419715000 |
TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps ) |
i_length = 1531 |
eth_phy length = 1535 |
->packet with length 1535 sent |
i_length = 1532 |
eth_phy length = 1536 |
->packet with length 1536 sent |
i_length = 1533 |
eth_phy length = 1537 |
->packet with length 1537 sent |
i_length = 65530 |
eth_phy length = 65534 |
->packet with length 65534 sent |
i_length = 65531 |
eth_phy length = 65535 |
->packet with length 65535 sent |
Time: 236329395000 |
TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps ) |
->IPG with 8 mtx_clk periods (min 3) between packets with lengths 64 and 65 checked |
->IPG with 8 mtx_clk periods (min 4) between packets with lengths 66 and 67 checked |
->IPG with 8 mtx_clk periods (min 5) between packets with lengths 68 and 69 checked |
->IPG with 8 mtx_clk periods (min 6) between packets with lengths 70 and 71 checked |
->IPG with 7 mtx_clk periods (min 7) between packets with lengths 72 and 73 checked |
->IPG with 8 mtx_clk periods (min 8) between packets with lengths 74 and 75 checked |
->IPG with 9 mtx_clk periods (min 9) between packets with lengths 76 and 77 checked |
->IPG with 10 mtx_clk periods (min 10) between packets with lengths 78 and 79 checked |
->IPG with 17 mtx_clk periods (min 17) between packets with lengths 80 and 81 checked |
->IPG with 24 mtx_clk periods (min 24) between packets with lengths 82 and 83 checked |
->IPG with 38 mtx_clk periods (min 38) between packets with lengths 84 and 85 checked |
->IPG with 72 mtx_clk periods (min 72) between packets with lengths 86 and 87 checked |
->IPG with 130 mtx_clk periods (min 130) between packets with lengths 88 and 89 checked |
Time: 238386915000 |
TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps ) |
->IPG with 47 mtx_clk periods (min 3) between packets with lengths 64 and 65 checked |
->IPG with 47 mtx_clk periods (min 4) between packets with lengths 66 and 67 checked |
->IPG with 44 mtx_clk periods (min 5) between packets with lengths 68 and 69 checked |
->IPG with 45 mtx_clk periods (min 6) between packets with lengths 70 and 71 checked |
->IPG with 44 mtx_clk periods (min 7) between packets with lengths 72 and 73 checked |
->IPG with 43 mtx_clk periods (min 8) between packets with lengths 74 and 75 checked |
->IPG with 45 mtx_clk periods (min 9) between packets with lengths 76 and 77 checked |
->IPG with 44 mtx_clk periods (min 10) between packets with lengths 78 and 79 checked |
->IPG with 43 mtx_clk periods (min 17) between packets with lengths 80 and 81 checked |
->IPG with 45 mtx_clk periods (min 24) between packets with lengths 82 and 83 checked |
->IPG with 44 mtx_clk periods (min 38) between packets with lengths 84 and 85 checked |
->IPG with 72 mtx_clk periods (min 72) between packets with lengths 86 and 87 checked |
->IPG with 130 mtx_clk periods (min 130) between packets with lengths 88 and 89 checked |
Time: 238653435000 |
TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps ) |
->under-run on 61. byte |
->under-run on 62. byte |
->under-run on 63. byte |
->under-run on 64. byte |
->under-run on 65. byte |
->under-run on 66. byte |
->under-run on 67. byte |
->under-run on 68. byte |
->under-run on 69. byte |
->under-run on 70. byte |
->under-run on 71. byte |
->under-run on 72. byte |
->under-run on 73. byte |
->under-run on 74. byte |
->under-run on 75. byte |
->under-run on 76. byte |
->under-run on 77. byte |
->under-run on 78. byte |
->under-run on 79. byte |
->no under-run on 80. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 81. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 82. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 83. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 84. byte, since length of frame (without CRC) is only 80 bytes |
Time: 242447355000 |
TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps ) |
->under-run on 61. byte |
->under-run on 62. byte |
->under-run on 63. byte |
->under-run on 64. byte |
->under-run on 65. byte |
->under-run on 66. byte |
->under-run on 67. byte |
->under-run on 68. byte |
->under-run on 69. byte |
->under-run on 70. byte |
->under-run on 71. byte |
->under-run on 72. byte |
->under-run on 73. byte |
->under-run on 74. byte |
->under-run on 75. byte |
->under-run on 76. byte |
->under-run on 77. byte |
->under-run on 78. byte |
->under-run on 79. byte |
->no under-run on 80. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 81. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 82. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 83. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 84. byte, since length of frame (without CRC) is only 80 bytes |
|
MAC FULL DUPLEX RECEIVE TEST |
Time: 242923367000 |
TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps ) |
Time: 252557359000 |
TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps ) |
Time: 254085799000 |
TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps ) |
8 packets (without this one) are checked - packets are received by two in a set |
From this moment: |
first one of two packets (including this one) is not accepted due to late RX enable |
->RX enable set 3 WB clks after RX_DV |
Time: 294264649000 |
TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps ) |
0 packets (without this one) are checked - packets are received by two in a set |
From this moment: |
first one of two packets (including this one) is not accepted due to late RX enable |
->RX enable set 2 WB clks after RX_DV |
Time: 299591329000 |
TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps ) |
receive small packets is NOT selected |
->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte) |
receive small packets is selected |
->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes) |
receive small packets is NOT selected |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
Time: 333243169000 |
TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps ) |
receive small packets is NOT selected |
->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte) |
receive small packets is selected |
->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes) |
receive small packets is NOT selected |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
Time: 336818689000 |
TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps ) |
receive small packets is NOT selected |
using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0) |
->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte) |
->all packets were received on RX BD 0 |
receive small packets is NOT selected |
using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127) |
->packets with lengths from 72 to 192 are checked (length increasing by 1 byte) |
->packets were received on RX BD 0 to RX BD 120 respectively |
receive small packets is selected |
using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127) |
->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes) |
->packets were received from RX BD 121 to RX BD 127 and from RX BD 0 to RX BD 2 respectively |
receive small packets is NOT selected |
using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127) |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
->packets were received from RX BD 3 to RX BD 18 respectively |
Time: 378320475000 |
TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps ) |
receive small packets is NOT selected |
using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0) |
->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte) |
->all packets were received on RX BD 0 |
receive small packets is NOT selected |
using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127) |
->packets with lengths from 72 to 192 are checked (length increasing by 1 byte) |
->packets were received on RX BD 0 to RX BD 120 respectively |
receive small packets is selected |
using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127) |
->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes) |
->packets were received from RX BD 121 to RX BD 127 and from RX BD 0 to RX BD 2 respectively |
receive small packets is NOT selected |
using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127) |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
->packets were received from RX BD 3 to RX BD 18 respectively |
Time: 382758795000 |
TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps ) |
using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120) |
->packets with lengths from 0 to 3 are not received (length increasing by 1 byte) |
using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120) |
->packet with length 4 is not received (length increasing by 1 byte) |
->packets with lengths from 5 to 9 are checked (length increasing by 1 byte) |
using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123) |
->packets with lengths from 10 to 17 are checked (length increasing by 1 byte) |
using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124) |
->packets with lengths from 18 to 27 are checked (length increasing by 1 byte) |
using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125) |
->packets with lengths from 28 to 40 are checked (length increasing by 1 byte) |
using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126) |
->packets with lengths from 41 to 54 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127) |
->packets with lengths from 55 to 69 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127) |
->packets with lengths from 70 to 77 are checked (length increasing by 1 byte) |
Time: 386187495000 |
TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps ) |
using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120) |
->packets with lengths from 0 to 3 are not received (length increasing by 1 byte) |
using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120) |
->packet with length 4 is not received (length increasing by 1 byte) |
->packets with lengths from 5 to 9 are checked (length increasing by 1 byte) |
using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123) |
->packets with lengths from 10 to 17 are checked (length increasing by 1 byte) |
using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124) |
->packets with lengths from 18 to 27 are checked (length increasing by 1 byte) |
using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125) |
->packets with lengths from 28 to 40 are checked (length increasing by 1 byte) |
using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126) |
->packets with lengths from 41 to 54 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127) |
->packets with lengths from 55 to 69 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127) |
->packets with lengths from 70 to 77 are checked (length increasing by 1 byte) |
Time: 386657745000 |
TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps ) |
Unicast packet is going to be received with PRO bit (wrap at 1st BD) |
->packet received |
Unicast packet is going to be received without PRO bit (wrap at 1st BD) |
->packet received |
non Unicast packet is going to be received with PRO bit (wrap at 1st BD) |
->packet received |
non Unicast packet is NOT going to be received without PRO bit (wrap at 1st BD) |
->packet NOT received |
Broadcast packet is going to be received with PRO & without Reject_BRO bit (wrap at 1st BD) |
->packet received |
Broadcast packet is going to be received without Reject_BRO bit (wrap at 1st BD) |
->packet received |
Broadcast packet is going to be received with PRO & with Reject_BRO bit (wrap at 1st BD) |
->packet received |
Broadcast packet is NOT going to be received with Reject_BRO bit (wrap at 1st BD) |
->packet NOT received |
Time: 387208159000 |
TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps ) |
Unicast packet is going to be received with PRO bit (wrap at 1st BD) |
->packet received |
Unicast packet is going to be received without PRO bit (wrap at 1st BD) |
->packet received |
non Unicast packet is going to be received with PRO bit (wrap at 1st BD) |
->packet received |
non Unicast packet is NOT going to be received without PRO bit (wrap at 1st BD) |
->packet NOT received |
Broadcast packet is going to be received with PRO & without Reject_BRO bit (wrap at 1st BD) |
->packet received |
Broadcast packet is going to be received without Reject_BRO bit (wrap at 1st BD) |
->packet received |
Broadcast packet is going to be received with PRO & with Reject_BRO bit (wrap at 1st BD) |
->packet received |
Broadcast packet is NOT going to be received with Reject_BRO bit (wrap at 1st BD) |
->packet NOT received |
Time: 387288679000 |
TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
packet shoud be successfuly received |
->packet received |
Time: 387359689000 |
*E RX buffer descriptor status is not correct: 6000 instead of 4000 |
packet (64Bytes) should be retained in RX FIFO and written to MEM after next RX FIFO overrun |
->packet NOT received |
Time: 387423768000 |
*E WB INT signal should not be set |
Time: 387424129000 |
*E Any of interrupts was set, interrupt reg: 10, len: 0 |
packet should NOT be received - RX FIFO overrun |
->packet NOT received |
Time: 387487968000 |
*E WB INT signal should not be set |
Time: 387488329000 |
*E Any of interrupts was set, interrupt reg: 10, len: 0 |
->previous packet written into MEM |
Time: 387492409000 |
*E RX buffer descriptor status is not correct: c000 instead of 4000 |
Time: 387492529000 |
*E Interrupt Receive Buffer Error was not set, interrupt reg: 10 |
Time: 387492529000 |
*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: 10 |
packet shoud be successfuly received |
->packet NOT received |
Time: 387562849000 |
*E RX buffer descriptor status is not correct: c000 instead of 4000 |
Time: 387562849000 |
*E Wrong length of the packet out from PHY (0 instead of 72) |
Time: 387562867000 |
*E Wrong data of the received packet |
Time: 387562969000 |
*E Interrupt Receive Buffer was not set, interrupt reg: 10 |
Time: 387562969000 |
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10 |
packet should NOT be received - RX FIFO overrun |
->packet NOT received |
Time: 387633408000 |
*E WB INT signal should not be set |
Time: 387633769000 |
*E Any of interrupts was set, interrupt reg: 10, len: 0 |
Time: 387637849000 |
*E RX buffer descriptor status is not correct: c000 instead of 4040 |
Time: 387637969000 |
*E Interrupt Receive Buffer Error was not set, interrupt reg: 10 |
Time: 387637969000 |
*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: 10 |
packet shoud be successfuly received |
->packet NOT received |
Time: 387708409000 |
*E RX buffer descriptor status is not correct: c000 instead of 4000 |
Time: 387708409000 |
*E Wrong length of the packet out from PHY (0 instead of 72) |
Time: 387708427000 |
*E Wrong data of the received packet |
Time: 387708529000 |
*E Interrupt Receive Buffer was not set, interrupt reg: 10 |
Time: 387708529000 |
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10 |
packet should NOT be received - RX FIFO overrun |
->packet NOT received |
Time: 387788208000 |
*E WB INT signal should not be set |
Time: 387788569000 |
*E Any of interrupts was set, interrupt reg: 10, len: 0 |
Time: 387792649000 |
*E RX buffer descriptor status is not correct: c000 instead of 4040 |
Time: 387792769000 |
*E Interrupt Receive Buffer Error was not set, interrupt reg: 10 |
Time: 387792769000 |
*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: 10 |
packet shoud be successfuly received |
->packet NOT received |
Time: 387872809000 |
*E RX buffer descriptor status is not correct: c000 instead of 4000 |
Time: 387872809000 |
*E Wrong length of the packet out from PHY (0 instead of 84) |
Time: 387872830000 |
*E Wrong data of the received packet |
Time: 387872929000 |
*E Interrupt Receive Buffer was not set, interrupt reg: 10 |
Time: 387872929000 |
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10 |
packet shoud be successfuly received |
->packet NOT received |
Time: 387952849000 |
*E RX buffer descriptor status is not correct: e000 instead of 6000 |
Time: 387952849000 |
*E Wrong length of the packet out from PHY (0 instead of 84) |
Time: 387952870000 |
*E Wrong data of the received packet |
Time: 387952969000 |
*E Interrupt Receive Buffer was not set, interrupt reg: 10 |
Time: 387952969000 |
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10 |
packet should NOT be received - RX FIFO overrun due to lack of RX BDs |
->packet NOT received |
packet shoud be successfuly received |
->packet received |
Time: 388115689000 |
*E RX buffer descriptor status is not correct: 6000 instead of 4000 |
Time: 388116049000 |
TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps ) |
packet shoud be successfuly received |
->packet received |
packet (64Bytes) should be retained in RX FIFO and written to MEM after next RX FIFO overrun |
->packet NOT received |
packet should NOT be received - RX FIFO overrun |
->packet NOT received |
->previous packet written into MEM |
packet shoud be successfuly received |
->packet received |
packet should NOT be received - RX FIFO overrun |
->packet NOT received |
packet shoud be successfuly received |
->packet received |
packet should NOT be received - RX FIFO overrun |
->packet NOT received |
packet shoud be successfuly received |
->packet received |
packet shoud be successfuly received |
->packet received |
packet should NOT be received - RX FIFO overrun due to lack of RX BDs |
->packet NOT received |
packet shoud be successfuly received |
->packet received |
|
MAC FULL DUPLEX FLOW CONTROL TEST |
Time: 388235057000 |
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps ) |
Time: 397626071000 |
TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps ) |
Time: 398657171000 |
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps ) |
Time: 399868939000 |
TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps ) |
Time: 400018579000 |
TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps ) |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
Time: 438761899000 |
TEST 5: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 100Mbps ) |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
|
MAC HALF DUPLEX FLOW TEST |
Time: 443751047000 |
TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
->TX Defer occured |
->IPGR2 timing checking |
Time: 443899119000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 444057159000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 444222399000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 444387999000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 444564339000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 444730779000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 444897579000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 445064679000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
Time: 445100407000 |
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
->IPGR2 timing checking |
Time: 445293579000 |
*E Wrong data of the transmitted packet |
->TX Defer occured |
Time: 445319207000 |
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
->IPGR2 timing checking |
Time: 445461579000 |
*E Wrong data of the transmitted packet |
->Collision occured due to registered inputs |
->IPGR2 timing checking |
Time: 445680339000 |
*E Wrong data of the transmitted packet |
->Collision occured - last checking |
->IPGR2 timing checking |
Time: 445899039000 |
*E Wrong data of the transmitted packet |
Time: 445919355000 |
TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
->TX Defer occured |
->IPGR2 timing checking |
Time: 445941549000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 445958709000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 445976589000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 445994469000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446019369000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446037369000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446055369000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446073369000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446098269000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446116269000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446134389000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446152629000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446177769000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446196129000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446214489000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446232849000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446257989000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446276349000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446294709000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446313189000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446338689000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446357289000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446376009000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446394549000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446420169000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446439009000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446457849000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446476689000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446502309000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446521149000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446539989000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446558949000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446584929000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446604009000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446623209000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446642229000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446668329000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446687649000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446706969000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446726289000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446752389000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446771709000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446791029000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446810469000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446836929000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446856489000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 446876169000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
Time: 446880487000 |
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
->IPGR2 timing checking |
Time: 446895669000 |
*E Wrong data of the transmitted packet |
->TX Defer occured |
Time: 446906887000 |
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
->IPGR2 timing checking |
Time: 446922249000 |
*E Wrong data of the transmitted packet |
->Collision occured due to registered inputs |
->IPGR2 timing checking |
Time: 446947089000 |
*E Wrong data of the transmitted packet |
->Collision occured - last checking |
->IPGR2 timing checking |
Time: 446966889000 |
*E Wrong data of the transmitted packet |
|
=========================================================================== |
PHY generates 'real delayed' Carrier sense and Collision signals for following tests |
=========================================================================== |
|
MAC FULL DUPLEX TRANSMIT TEST |
Time: 446969327000 |
TEST 0: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 10Mbps ) |
Time: 447667519000 |
TEST 1: NO TRANSMIT WHEN ALL BUFFERS ARE RX ( 100Mbps ) |
Time: 448301959000 |
TEST 2: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 10Mbps ) |
pads appending to packets is NOT selected |
->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte) |
pads appending to packets is selected |
->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes) |
pads appending to packets is NOT selected |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
Time: 482092399000 |
TEST 3: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT ONE TX BD ( 100Mbps ) |
pads appending to packets is NOT selected |
->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte) |
pads appending to packets is selected |
->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes) |
pads appending to packets is NOT selected |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
Time: 485807599000 |
TEST 4: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 10Mbps ) |
pads appending to packets is NOT selected |
using only TX BD 0 out of 128 BDs assigned to TX (wrap at first BD - TX BD 0) |
->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte) |
->all packets were send from TX BD 0 |
pads appending to packets is NOT selected |
using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127) |
->packets with lengths from 72 to 192 are checked (length increasing by 1 byte) |
->packets were send from TX BD 0 to TX BD 120 respectively |
pads appending to packets is selected |
using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127) |
->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes) |
->packets were send from TX BD 121 to TX BD 127 and from TX BD 0 to TX BD 2 respectively |
pads appending to packets is NOT selected |
using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127) |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
->packets were send from TX BD 3 to TX BD 18 respectively |
Time: 527716635000 |
TEST 5: TRANSMIT PACKETS FROM MINFL TO MAXFL SIZES AT MAX TX BDs ( 100Mbps ) |
pads appending to packets is NOT selected |
using only TX BD 0 out of 128 BDs assigned to TX (wrap at first BD - TX BD 0) |
->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte) |
->all packets were send from TX BD 0 |
pads appending to packets is NOT selected |
using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127) |
->packets with lengths from 72 to 192 are checked (length increasing by 1 byte) |
->packets were send from TX BD 0 to TX BD 120 respectively |
pads appending to packets is selected |
using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127) |
->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes) |
->packets were send from TX BD 121 to TX BD 127 and from TX BD 0 to TX BD 2 respectively |
pads appending to packets is NOT selected |
using all 128 BDs assigned to TX (wrap at 128th BD - TX BD 127) |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
->packets were send from TX BD 3 to TX BD 18 respectively |
Time: 532334235000 |
TEST 6: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps ) |
pads appending to packets is selected |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte) |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packet with length 4 is not transmitted (length increasing by 1 byte) |
->packets with lengths from 5 to 9 are checked (length increasing by 1 byte) |
using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3) |
->packets with lengths from 10 to 17 are checked (length increasing by 1 byte) |
using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4) |
->packets with lengths from 18 to 27 are checked (length increasing by 1 byte) |
using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5) |
->packets with lengths from 28 to 40 are checked (length increasing by 1 byte) |
using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6) |
->packets with lengths from 41 to 54 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7) |
->packets with lengths from 55 to 69 are checked (length increasing by 1 byte) |
Time: 536725875000 |
TEST 7: TRANSMIT PACKETS FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps ) |
pads appending to packets is selected |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte) |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packet with length 4 is not transmitted (length increasing by 1 byte) |
->packets with lengths from 5 to 9 are checked (length increasing by 1 byte) |
using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3) |
->packets with lengths from 10 to 17 are checked (length increasing by 1 byte) |
using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4) |
->packets with lengths from 18 to 27 are checked (length increasing by 1 byte) |
using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5) |
->packets with lengths from 28 to 40 are checked (length increasing by 1 byte) |
using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6) |
->packets with lengths from 41 to 54 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7) |
->packets with lengths from 55 to 69 are checked (length increasing by 1 byte) |
Time: 537331395000 |
TEST 8: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 10Mbps ) |
pads appending to packets is not selected (except for 0x23) |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte) |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packet with length 4 is not transmitted (length increasing by 1 byte) |
->packets with lengths from 5 to 9 are checked (length increasing by 1 byte) |
using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3) |
->packets with lengths from 10 to 17 are checked (length increasing by 1 byte) |
using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4) |
->packets with lengths from 18 to 27 are checked (length increasing by 1 byte) |
using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5) |
->packets with lengths from 28 to 40 are checked (length increasing by 1 byte) |
using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6) |
->packets with lengths from 41 to 54 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7) |
->packets with lengths from 55 to 69 are checked (length increasing by 1 byte) |
Time: 540418515000 |
TEST 9: TRANSMIT PACKETS (NO PADs) FROM 0 TO (MINFL - 1) SIZES AT 8 TX BD ( 100Mbps ) |
pads appending to packets is not selected (except for 0x23) |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packets with lengths from 0 to 3 are not transmitted (length increasing by 1 byte) |
using 1 BD out of 8 BDs assigned to TX (wrap at 1st BD - TX BD 0) |
->packet with length 4 is not transmitted (length increasing by 1 byte) |
->packets with lengths from 5 to 9 are checked (length increasing by 1 byte) |
using 4 BDs out of 8 BDs assigned to TX (wrap at 4th BD - TX BD 3) |
->packets with lengths from 10 to 17 are checked (length increasing by 1 byte) |
using 5 BDs out of 8 BDs assigned to TX (wrap at 5th BD - TX BD 4) |
->packets with lengths from 18 to 27 are checked (length increasing by 1 byte) |
using 6 BDs out of 8 BDs assigned to TX (wrap at 6th BD - TX BD 5) |
->packets with lengths from 28 to 40 are checked (length increasing by 1 byte) |
using 7 BDs out of 8 BDs assigned to TX (wrap at 7th BD - TX BD 6) |
->packets with lengths from 41 to 54 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs assigned to TX (wrap at 8th BD - TX BD 7) |
->packets with lengths from 55 to 69 are checked (length increasing by 1 byte) |
Time: 540893355000 |
TEST 10: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 10Mbps ) |
->packet with length 1535 sent |
->packet with length 1536 sent |
->packet with length 1537 sent |
->packet with length 104 sent |
Time: 544722915000 |
TEST 11: TRANSMIT PACKETS ACROSS MAXFL VALUE AT 13 TX BDs ( 100Mbps ) |
->packet with length 1535 sent |
->packet with length 1536 sent |
->packet with length 1537 sent |
->packet with length 104 sent |
Time: 545120475000 |
TEST 12: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 10Mbps ) |
->packet with length 116 sent |
->packet with length 117 sent |
->packet with length 118 sent |
Time: 545448195000 |
TEST 13: TRANSMIT PACKETS ACROSS CHANGED MAXFL VALUE AT 13 TX BDs ( 100Mbps ) |
->packet with length 116 sent |
->packet with length 117 sent |
->packet with length 118 sent |
Time: 545490315000 |
TEST 14: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 10Mbps ) |
->packet with length 1358 sent |
->packet with length 1359 sent |
->packet with length 1360 sent |
Time: 548798595000 |
TEST 15: TRANSMIT PACKETS ACROSS CHANGED MINFL VALUE AT 7 TX BDs ( 100Mbps ) |
->packet with length 1358 sent |
->packet with length 1359 sent |
->packet with length 1360 sent |
Time: 549139275000 |
TEST 16: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 10Mbps ) |
i_length = 1531 |
eth_phy length = 1535 |
->packet with length 1535 sent |
i_length = 1532 |
eth_phy length = 1536 |
->packet with length 1536 sent |
i_length = 1533 |
eth_phy length = 1537 |
->packet with length 1537 sent |
i_length = 65530 |
eth_phy length = 65534 |
->packet with length 65534 sent |
i_length = 65531 |
eth_phy length = 65535 |
->packet with length 65535 sent |
Time: 657784995000 |
TEST 17: TRANSMIT PACKETS ACROSS MAXFL WITH HUGEN AT 19 TX BDs ( 100Mbps ) |
i_length = 1531 |
eth_phy length = 1535 |
->packet with length 1535 sent |
i_length = 1532 |
eth_phy length = 1536 |
->packet with length 1536 sent |
i_length = 1533 |
eth_phy length = 1537 |
->packet with length 1537 sent |
i_length = 65530 |
eth_phy length = 65534 |
->packet with length 65534 sent |
i_length = 65531 |
eth_phy length = 65535 |
->packet with length 65535 sent |
Time: 668694675000 |
TEST 18: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 10Mbps ) |
->IPG with 8 mtx_clk periods (min 3) between packets with lengths 64 and 65 checked |
->IPG with 8 mtx_clk periods (min 4) between packets with lengths 66 and 67 checked |
->IPG with 8 mtx_clk periods (min 5) between packets with lengths 68 and 69 checked |
->IPG with 8 mtx_clk periods (min 6) between packets with lengths 70 and 71 checked |
->IPG with 7 mtx_clk periods (min 7) between packets with lengths 72 and 73 checked |
->IPG with 8 mtx_clk periods (min 8) between packets with lengths 74 and 75 checked |
->IPG with 9 mtx_clk periods (min 9) between packets with lengths 76 and 77 checked |
->IPG with 10 mtx_clk periods (min 10) between packets with lengths 78 and 79 checked |
->IPG with 17 mtx_clk periods (min 17) between packets with lengths 80 and 81 checked |
->IPG with 24 mtx_clk periods (min 24) between packets with lengths 82 and 83 checked |
->IPG with 38 mtx_clk periods (min 38) between packets with lengths 84 and 85 checked |
->IPG with 72 mtx_clk periods (min 72) between packets with lengths 86 and 87 checked |
->IPG with 130 mtx_clk periods (min 130) between packets with lengths 88 and 89 checked |
Time: 670752195000 |
TEST 19: IPG DURING BACK-TO-BACK TRANSMIT AT 88 TX BDs ( 100Mbps ) |
->IPG with 47 mtx_clk periods (min 3) between packets with lengths 64 and 65 checked |
->IPG with 47 mtx_clk periods (min 4) between packets with lengths 66 and 67 checked |
->IPG with 44 mtx_clk periods (min 5) between packets with lengths 68 and 69 checked |
->IPG with 45 mtx_clk periods (min 6) between packets with lengths 70 and 71 checked |
->IPG with 44 mtx_clk periods (min 7) between packets with lengths 72 and 73 checked |
->IPG with 43 mtx_clk periods (min 8) between packets with lengths 74 and 75 checked |
->IPG with 45 mtx_clk periods (min 9) between packets with lengths 76 and 77 checked |
->IPG with 44 mtx_clk periods (min 10) between packets with lengths 78 and 79 checked |
->IPG with 43 mtx_clk periods (min 17) between packets with lengths 80 and 81 checked |
->IPG with 45 mtx_clk periods (min 24) between packets with lengths 82 and 83 checked |
->IPG with 44 mtx_clk periods (min 38) between packets with lengths 84 and 85 checked |
->IPG with 72 mtx_clk periods (min 72) between packets with lengths 86 and 87 checked |
->IPG with 130 mtx_clk periods (min 130) between packets with lengths 88 and 89 checked |
Time: 671018715000 |
TEST 20: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 10Mbps ) |
->under-run on 61. byte |
->under-run on 62. byte |
->under-run on 63. byte |
->under-run on 64. byte |
->under-run on 65. byte |
->under-run on 66. byte |
->under-run on 67. byte |
->under-run on 68. byte |
->under-run on 69. byte |
->under-run on 70. byte |
->under-run on 71. byte |
->under-run on 72. byte |
->under-run on 73. byte |
->under-run on 74. byte |
->under-run on 75. byte |
->under-run on 76. byte |
->under-run on 77. byte |
->under-run on 78. byte |
->under-run on 79. byte |
->no under-run on 80. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 81. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 82. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 83. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 84. byte, since length of frame (without CRC) is only 80 bytes |
Time: 674812635000 |
TEST 21: TRANSMIT PACKETS AFTER TX UNDER-RUN ON EACH PACKET's BYTE AT 2 TX BDs ( 100Mbps ) |
->under-run on 61. byte |
->under-run on 62. byte |
->under-run on 63. byte |
->under-run on 64. byte |
->under-run on 65. byte |
->under-run on 66. byte |
->under-run on 67. byte |
->under-run on 68. byte |
->under-run on 69. byte |
->under-run on 70. byte |
->under-run on 71. byte |
->under-run on 72. byte |
->under-run on 73. byte |
->under-run on 74. byte |
->under-run on 75. byte |
->under-run on 76. byte |
->under-run on 77. byte |
->under-run on 78. byte |
->under-run on 79. byte |
->no under-run on 80. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 81. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 82. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 83. byte, since length of frame (without CRC) is only 80 bytes |
->no under-run on 84. byte, since length of frame (without CRC) is only 80 bytes |
|
MAC FULL DUPLEX RECEIVE TEST |
Time: 675288647000 |
TEST 0: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 10Mbps ) |
Time: 684922639000 |
TEST 1: NO RECEIVE WHEN ALL BUFFERS ARE TX ( 100Mbps ) |
Time: 686451079000 |
TEST 2: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 10Mbps ) |
8 packets (without this one) are checked - packets are received by two in a set |
From this moment: |
first one of two packets (including this one) is not accepted due to late RX enable |
->RX enable set 3 WB clks after RX_DV |
Time: 726629929000 |
TEST 3: RECEIVE PACKET SYNCHRONIZATION WITH RECEIVE DISABLE/ENABLE ( 100Mbps ) |
0 packets (without this one) are checked - packets are received by two in a set |
From this moment: |
first one of two packets (including this one) is not accepted due to late RX enable |
->RX enable set 2 WB clks after RX_DV |
Time: 731956609000 |
TEST 4: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 10Mbps ) |
receive small packets is NOT selected |
->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte) |
receive small packets is selected |
->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes) |
receive small packets is NOT selected |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
Time: 765608449000 |
TEST 5: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT ONE RX BD ( 100Mbps ) |
receive small packets is NOT selected |
->packets with lengths from 64 (MINFL) to 128 are checked (length increasing by 1 byte) |
receive small packets is selected |
->packets with lengths from 256 to 1408 are checked (length increasing by 128 bytes) |
receive small packets is NOT selected |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
Time: 769183969000 |
TEST 6: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 10Mbps ) |
receive small packets is NOT selected |
using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0) |
->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte) |
->all packets were received on RX BD 0 |
receive small packets is NOT selected |
using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127) |
->packets with lengths from 72 to 192 are checked (length increasing by 1 byte) |
->packets were received on RX BD 0 to RX BD 120 respectively |
receive small packets is selected |
using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127) |
->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes) |
->packets were received from RX BD 121 to RX BD 127 and from RX BD 0 to RX BD 2 respectively |
receive small packets is NOT selected |
using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127) |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
->packets were received from RX BD 3 to RX BD 18 respectively |
Time: 810685755000 |
TEST 7: RECEIVE PACKETS FROM MINFL TO MAXFL SIZES AT MAX RX BDs ( 100Mbps ) |
receive small packets is NOT selected |
using only RX BD 0 out of 128 BDs assigned to RX (wrap at first BD - RX BD 0) |
->packets with lengths from 64 (MINFL) to 71 are checked (length increasing by 1 byte) |
->all packets were received on RX BD 0 |
receive small packets is NOT selected |
using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127) |
->packets with lengths from 72 to 192 are checked (length increasing by 1 byte) |
->packets were received on RX BD 0 to RX BD 120 respectively |
receive small packets is selected |
using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127) |
->packets with lengths from 256 to 1284 are checked (length increasing by 128 bytes) |
->packets were received from RX BD 121 to RX BD 127 and from RX BD 0 to RX BD 2 respectively |
receive small packets is NOT selected |
using all 128 BDs assigned to RX (wrap at 128th BD - RX BD 127) |
->packets with lengths from 1516 to 1536 (MAXFL) are checked (length increasing by 1 byte) |
->packets were received from RX BD 3 to RX BD 18 respectively |
Time: 815124075000 |
TEST 8: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 10Mbps ) |
using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120) |
->packets with lengths from 0 to 3 are not received (length increasing by 1 byte) |
using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120) |
->packet with length 4 is not received (length increasing by 1 byte) |
->packets with lengths from 5 to 9 are checked (length increasing by 1 byte) |
using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123) |
->packets with lengths from 10 to 17 are checked (length increasing by 1 byte) |
using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124) |
->packets with lengths from 18 to 27 are checked (length increasing by 1 byte) |
using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125) |
->packets with lengths from 28 to 40 are checked (length increasing by 1 byte) |
using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126) |
->packets with lengths from 41 to 54 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127) |
->packets with lengths from 55 to 69 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127) |
->packets with lengths from 70 to 77 are checked (length increasing by 1 byte) |
Time: 818552775000 |
TEST 9: RECEIVE PACKETS FROM 0 TO (MINFL + 12) SIZES AT 8 RX BD ( 100Mbps ) |
using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120) |
->packets with lengths from 0 to 3 are not received (length increasing by 1 byte) |
using 1 BD out of 8 BDs (120..127) assigned to RX (wrap at 1st BD - RX BD 120) |
->packet with length 4 is not received (length increasing by 1 byte) |
->packets with lengths from 5 to 9 are checked (length increasing by 1 byte) |
using 4 BDs out of 8 BDs (120..127) assigned to RX (wrap at 4th BD - RX BD 123) |
->packets with lengths from 10 to 17 are checked (length increasing by 1 byte) |
using 5 BDs out of 8 BDs (120..127) assigned to RX (wrap at 5th BD - RX BD 124) |
->packets with lengths from 18 to 27 are checked (length increasing by 1 byte) |
using 6 BDs out of 8 BDs (120..127) assigned to RX (wrap at 6th BD - RX BD 125) |
->packets with lengths from 28 to 40 are checked (length increasing by 1 byte) |
using 7 BDs out of 8 BDs (120..127) assigned to RX (wrap at 7th BD - RX BD 126) |
->packets with lengths from 41 to 54 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127) |
->packets with lengths from 55 to 69 are checked (length increasing by 1 byte) |
using 8 BDs out of 8 BDs (120..127) assigned to RX (wrap at 8th BD - RX BD 127) |
->packets with lengths from 70 to 77 are checked (length increasing by 1 byte) |
Time: 819023025000 |
TEST 10: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 10Mbps ) |
Unicast packet is going to be received with PRO bit (wrap at 1st BD) |
->packet received |
Unicast packet is going to be received without PRO bit (wrap at 1st BD) |
->packet received |
non Unicast packet is going to be received with PRO bit (wrap at 1st BD) |
->packet received |
non Unicast packet is NOT going to be received without PRO bit (wrap at 1st BD) |
->packet NOT received |
Broadcast packet is going to be received with PRO & without Reject_BRO bit (wrap at 1st BD) |
->packet received |
Broadcast packet is going to be received without Reject_BRO bit (wrap at 1st BD) |
->packet received |
Broadcast packet is going to be received with PRO & with Reject_BRO bit (wrap at 1st BD) |
->packet received |
Broadcast packet is NOT going to be received with Reject_BRO bit (wrap at 1st BD) |
->packet NOT received |
Time: 819573439000 |
TEST 11: RECEIVE PACKETS AT ONE RX BD AND CHECK ADDRESSES ( 100Mbps ) |
Unicast packet is going to be received with PRO bit (wrap at 1st BD) |
->packet received |
Unicast packet is going to be received without PRO bit (wrap at 1st BD) |
->packet received |
non Unicast packet is going to be received with PRO bit (wrap at 1st BD) |
->packet received |
non Unicast packet is NOT going to be received without PRO bit (wrap at 1st BD) |
->packet NOT received |
Broadcast packet is going to be received with PRO & without Reject_BRO bit (wrap at 1st BD) |
->packet received |
Broadcast packet is going to be received without Reject_BRO bit (wrap at 1st BD) |
->packet received |
Broadcast packet is going to be received with PRO & with Reject_BRO bit (wrap at 1st BD) |
->packet received |
Broadcast packet is NOT going to be received with Reject_BRO bit (wrap at 1st BD) |
->packet NOT received |
Time: 819653959000 |
TEST 12: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 10Mbps ) |
packet shoud be successfuly received |
->packet received |
Time: 819724969000 |
*E RX buffer descriptor status is not correct: 6000 instead of 4000 |
packet (64Bytes) should be retained in RX FIFO and written to MEM after next RX FIFO overrun |
->packet NOT received |
Time: 819789048000 |
*E WB INT signal should not be set |
Time: 819789409000 |
*E Any of interrupts was set, interrupt reg: 10, len: 0 |
packet should NOT be received - RX FIFO overrun |
->packet NOT received |
Time: 819853248000 |
*E WB INT signal should not be set |
Time: 819853609000 |
*E Any of interrupts was set, interrupt reg: 10, len: 0 |
->previous packet written into MEM |
Time: 819857689000 |
*E RX buffer descriptor status is not correct: c000 instead of 4000 |
Time: 819857809000 |
*E Interrupt Receive Buffer Error was not set, interrupt reg: 10 |
Time: 819857809000 |
*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: 10 |
packet shoud be successfuly received |
->packet NOT received |
Time: 819928129000 |
*E RX buffer descriptor status is not correct: c000 instead of 4000 |
Time: 819928129000 |
*E Wrong length of the packet out from PHY (0 instead of 72) |
Time: 819928147000 |
*E Wrong data of the received packet |
Time: 819928249000 |
*E Interrupt Receive Buffer was not set, interrupt reg: 10 |
Time: 819928249000 |
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10 |
packet should NOT be received - RX FIFO overrun |
->packet NOT received |
Time: 819998688000 |
*E WB INT signal should not be set |
Time: 819999049000 |
*E Any of interrupts was set, interrupt reg: 10, len: 0 |
Time: 820003129000 |
*E RX buffer descriptor status is not correct: c000 instead of 4040 |
Time: 820003249000 |
*E Interrupt Receive Buffer Error was not set, interrupt reg: 10 |
Time: 820003249000 |
*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: 10 |
packet shoud be successfuly received |
->packet NOT received |
Time: 820073689000 |
*E RX buffer descriptor status is not correct: c000 instead of 4000 |
Time: 820073689000 |
*E Wrong length of the packet out from PHY (0 instead of 72) |
Time: 820073707000 |
*E Wrong data of the received packet |
Time: 820073809000 |
*E Interrupt Receive Buffer was not set, interrupt reg: 10 |
Time: 820073809000 |
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10 |
packet should NOT be received - RX FIFO overrun |
->packet NOT received |
Time: 820153488000 |
*E WB INT signal should not be set |
Time: 820153849000 |
*E Any of interrupts was set, interrupt reg: 10, len: 0 |
Time: 820157929000 |
*E RX buffer descriptor status is not correct: c000 instead of 4040 |
Time: 820158049000 |
*E Interrupt Receive Buffer Error was not set, interrupt reg: 10 |
Time: 820158049000 |
*E Other interrupts (except Receive Buffer Error) were set, interrupt reg: 10 |
packet shoud be successfuly received |
->packet NOT received |
Time: 820238089000 |
*E RX buffer descriptor status is not correct: c000 instead of 4000 |
Time: 820238089000 |
*E Wrong length of the packet out from PHY (0 instead of 84) |
Time: 820238110000 |
*E Wrong data of the received packet |
Time: 820238209000 |
*E Interrupt Receive Buffer was not set, interrupt reg: 10 |
Time: 820238209000 |
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10 |
packet shoud be successfuly received |
->packet NOT received |
Time: 820318129000 |
*E RX buffer descriptor status is not correct: e000 instead of 6000 |
Time: 820318129000 |
*E Wrong length of the packet out from PHY (0 instead of 84) |
Time: 820318150000 |
*E Wrong data of the received packet |
Time: 820318249000 |
*E Interrupt Receive Buffer was not set, interrupt reg: 10 |
Time: 820318249000 |
*E Other interrupts (except Receive Buffer) were set, interrupt reg: 10 |
packet should NOT be received - RX FIFO overrun due to lack of RX BDs |
->packet NOT received |
packet shoud be successfuly received |
->packet received |
Time: 820480969000 |
*E RX buffer descriptor status is not correct: 6000 instead of 4000 |
Time: 820481329000 |
TEST 13: RECEIVE PACKETS AT 8 RX BD WITH RX FIFO AND RX BD OVERRUN ( 100Mbps ) |
packet shoud be successfuly received |
->packet received |
packet (64Bytes) should be retained in RX FIFO and written to MEM after next RX FIFO overrun |
->packet NOT received |
packet should NOT be received - RX FIFO overrun |
->packet NOT received |
->previous packet written into MEM |
packet shoud be successfuly received |
->packet received |
packet should NOT be received - RX FIFO overrun |
->packet NOT received |
packet shoud be successfuly received |
->packet received |
packet should NOT be received - RX FIFO overrun |
->packet NOT received |
packet shoud be successfuly received |
->packet received |
packet shoud be successfuly received |
->packet received |
packet should NOT be received - RX FIFO overrun due to lack of RX BDs |
->packet NOT received |
packet shoud be successfuly received |
->packet received |
|
MAC FULL DUPLEX FLOW CONTROL TEST |
Time: 820600337000 |
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps ) |
Time: 829991351000 |
TEST 1: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 100Mbps ) |
Time: 831022451000 |
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 10Mbps ) |
Time: 832234219000 |
TEST 3: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED ON AND OFF AT ONE RX BD ( 100Mbps ) |
Time: 832383859000 |
TEST 4: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 10Mbps ) |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
Time: 871127179000 |
TEST 5: RANDOM RECEIVE AND TRANSMIT FRAMES AT ONE TX AND ONE RX BD ( 100Mbps ) |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames transmitted |
->8 frames received |
->8 frames transmitted |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
->8 frames received |
|
MAC HALF DUPLEX FLOW TEST |
Time: 876116327000 |
TEST 0: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 10Mbps ) |
->TX Defer occured |
->IPGR2 timing checking |
Time: 876264399000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 876422439000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 876587679000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 876753279000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 876929619000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 877096059000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 877262859000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 877429959000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 877607619000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
Time: 877635687000 |
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
->IPGR2 timing checking |
Time: 877826379000 |
*E Wrong data of the transmitted packet |
->TX Defer occured |
Time: 877854487000 |
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
->IPGR2 timing checking |
Time: 877994859000 |
*E Wrong data of the transmitted packet |
->Collision occured due to registered inputs |
->IPGR2 timing checking |
Time: 878163519000 |
*E Wrong data of the transmitted packet |
->Collision occured - last checking |
Time: 878264599000 |
*E Receive packet should be accepted |
->IPGR2 timing checking |
Time: 878342599000 |
*E Wrong length of the packet out from PHY (0 instead of 68) |
Time: 878342616000 |
*E Wrong data of the received packet |
Time: 878342616000 |
*E RX buffer descriptor status is not correct: c000 instead of 6081 |
Time: 878342859000 |
*E Wrong data of the transmitted packet |
Time: 878342959000 |
*E Interrupt Receive Error was not set, interrupt reg: 1 |
Time: 878363025000 |
TEST 1: DEFER, COLL. AND LATE COLL. WHILE TRANSMITTING AND RECEIVING FRM. AT 4 TX/RX BD ( 100Mbps ) |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878385939000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878403099000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878420979000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878438859000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878463639000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878481519000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878499399000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878517399000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878542299000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878560299000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878578419000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878596539000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878621559000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878639799000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878658039000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878676399000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878701539000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878719899000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878738259000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878756739000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878782119000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878800599000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878819199000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878837919000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878863419000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878882139000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878900859000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878919699000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878945439000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878964279000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 878983119000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879002079000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879027939000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879046899000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879065979000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879085059000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879111039000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879130239000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879149439000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879168759000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879194859000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879214179000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879233499000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879252939000 |
*E TX buffer descriptor status is not correct: 7800 instead of 7802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879279279000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879298719000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879318279000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
Time: 879322807000 |
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
->IPGR2 timing checking |
Time: 879342999000 |
*E Wrong data of the transmitted packet |
->TX Defer occured |
->IPGR2 timing checking |
Time: 879369459000 |
*E TX buffer descriptor status is not correct: 5800 instead of 5802 |
->TX Defer occured |
Time: 879374007000 |
*E Transmit should NOT start more than 1 CLK after CarrierSense and causing Collision |
->IPGR2 timing checking |
Time: 879389139000 |
*E Wrong data of the transmitted packet |
->Collision occured due to registered inputs |
->IPGR2 timing checking |
Time: 879408819000 |
*E Wrong data of the transmitted packet |
->Collision occured - last checking |
Time: 879420079000 |
*E Receive packet should be accepted |
->IPGR2 timing checking |
Time: 879428239000 |
*E Wrong length of the packet out from PHY (0 instead of 68) |
Time: 879428256000 |
*E Wrong data of the received packet |
Time: 879428256000 |
*E RX buffer descriptor status is not correct: e000 instead of 6081 |
Time: 879428499000 |
*E Wrong data of the transmitted packet |
Time: 879428599000 |
*E Interrupt Receive Error was not set, interrupt reg: 1 |
|
|
END of SIMULATION |
Simulation stopped via $stop(1) at time 879430815 NS + 0 |
/projects/ethernet/tadejm/ethernet/bench/verilog/tb_ethernet.v:530 $stop; |
ncsim> quit |
/ncsim_sim/log/dir_keeper
--- ncsim_sim/run/run_eth_sim_regr.scr (nonexistent)
+++ ncsim_sim/run/run_eth_sim_regr.scr (revision 338)
@@ -0,0 +1,242 @@
+#!/bin/csh -f
+
+set arg_num = $#argv; # number of arguments
+
+# current iterration
+set iter = 1;
+# number of tests with DEFINES + test with user defined constants!
+set all_iterations = 3;
+# ATS (Automatic Test System) parameter, which causes displaying 'OK'
+# if all testcases finish OK.
+set ok = 1;
+
+# Process argument
+set i = 1;
+set arg_waves = 0;
+set arg_regression = 0;
+
+
+if ($arg_num == 0) then
+ echo " Verification without any parameter !"
+else
+ while ($i <= $arg_num);
+ if (("$argv[$i]" == "waves") | ("$argv[$i]" == "-w")) then
+ @ arg_waves = 1;
+ echo " Verification with parameter : waves !"
+ else
+ if (("$argv[$i]" == "regression") | ("$argv[$i]" == "-r")) then
+ @ arg_regression = 1;
+ echo " Verification with parameter : regression !"
+ else
+ echo " Not correct parameter ( $i )"
+ echo " Correct parameters are:"
+ echo " 'waves' or '-w'"
+ echo " 'regression' or '-r'"
+ exit
+ endif
+ endif
+ @ i = $i + 1;
+ end
+endif
+
+
+# if ($arg_num == 1) then
+# if (("$1" == "waves") | ("$1" == "-w")) then
+# @ arg_waves = 1;
+# echo " Verification with parameter : waves !"
+# else
+# if (("$1" == "regression") | ("$1" == "-r")) then
+# @ arg_regression = 1;
+# echo " Verification with parameter : regression !"
+# else
+# echo " Not correct parameter ( $1 )"
+# echo " Correct parameters are:"
+# echo " 'waves' or '-w'"
+# echo " 'regression' or '-r'"
+# exit
+# endif
+# endif
+# else
+# if ($arg_num == 2) then
+# if (("$1" == "waves") | ("$1" == "-w")) then
+# @ arg_waves = 1;
+# if (("$2" == "regression") | ("$2" == "-r")) then
+# @ arg_regression = 1;
+# echo " Verification with parameter : waves, regression !"
+# else
+# echo " Not correct parameter ( $2 )"
+# echo " Correct 2. parameter is:"
+# echo " 'regression' or '-r'"
+# exit
+# endif
+# else
+# if (("$1" == "regression") | ("$1" == "-r")) then
+# @ arg_regression = 1;
+# if (("$2" == "waves") | ("$2" == "-w")) then
+# @ arg_waves = 1;
+# echo " Verification with parameter : waves, regression !"
+# else
+# echo " Not correct parameter ( $2 )"
+# echo " Correct 2. parameter is:"
+# echo " 'waves' or '-w'"
+# exit
+# endif
+# else
+# echo " Not correct parameter ( $1 )"
+# echo " Correct parameters are:"
+# echo " 'waves' or '-w'"
+# echo " 'regression' or '-r'"
+# exit
+# endif
+# endif
+# else
+# echo " Too many parameters ( $arg_num )"
+# echo " Maximum number of parameters is 2:"
+# echo " 'waves' or '-w'"
+# echo " 'regression' or '-r'"
+# exit
+# endif
+# endif
+# endif
+
+echo ""
+echo "<<<"
+echo "<<< Ethernet MAC VERIFICATION "
+echo "<<<"
+
+# ITERATION LOOP
+iteration:
+
+echo ""
+echo "<<<"
+echo "<<< Iteration ${iter}"
+echo "<<<"
+
+if ($arg_regression == 1) then
+ if ($iter <= $all_iterations) then
+ if ($iter == 1) then
+ echo "<<< Defines:"
+ echo "\tEthernet with GENERIC RAM"
+ echo "-DEFINE REGR" > ./defines.args
+ endif
+ if ($iter == 2) then
+ echo "<<< Defines:"
+ echo "\tEthernet with XILINX DISTRIBUTED RAM"
+ echo "-DEFINE REGR -DEFINE ETH_FIFO_XILINX" > ./defines.args
+ endif
+ if ($iter == 3) then
+ echo "<<< Defines:"
+ echo "\tEthernet with XILINX BLOCK RAM"
+ echo "-DEFINE REGR -DEFINE XILINX_RAMB4" > ./defines.args
+ endif
+ endif
+endif
+
+# Run NC-Verilog compiler
+echo ""
+echo "\t@@@"
+echo "\t@@@ Compiling sources"
+echo "\t@@@"
+
+# creating .args file for ncvlog and adding main parameters
+echo "-cdslib ../bin/cds.lib" > ./ncvlog.args
+echo "-hdlvar ../bin/hdl.var" >> ./ncvlog.args
+echo "-logfile ../log/ncvlog.log" >> ./ncvlog.args
+echo "-update" >> ./ncvlog.args
+echo "-messages" >> ./ncvlog.args
+echo "-INCDIR ../../../../bench/verilog" >> ./ncvlog.args
+echo "-INCDIR ../../../../rtl/verilog" >> ./ncvlog.args
+echo "-DEFINE SIM" >> ./ncvlog.args
+# adding defines to .args file
+if ($arg_regression == 1) then
+ cat ./defines.args >> ./ncvlog.args
+endif
+# adding RTL and Sim files to .args file
+cat ../bin/rtl_file_list.lst >> ./ncvlog.args
+cat ../bin/sim_file_list.lst >> ./ncvlog.args
+# adding device dependent files to .args file
+cat ../bin/xilinx_file_list.lst >> ./ncvlog.args
+cat ../bin/artisan_file_list.lst >> ./ncvlog.args
+
+ncvlog -file ./ncvlog.args# > /dev/null;
+echo ""
+
+
+# Run the NC-Verilog elaborator (build the design hierarchy)
+echo ""
+echo "\t@@@"
+echo "\t@@@ Building design hierarchy (elaboration)"
+echo "\t@@@"
+ncelab -file ../bin/ncelab_xilinx.args# > /dev/null;
+echo ""
+
+
+# Run the NC-Verilog simulator (simulate the design)
+echo ""
+echo "\t###"
+echo "\t### Running tests (this takes a long time!)"
+echo "\t###"
+
+# creating ncsim.args file for ncsim and adding main parameters
+echo "-cdslib ../bin/cds.lib" > ./ncsim.args
+echo "-hdlvar ../bin/hdl.var" >> ./ncsim.args
+echo "-logfile ../log/ncsim.log" >> ./ncsim.args
+echo "-messages" >> ./ncsim.args
+if ($arg_waves == 1) then
+ echo "-input ../bin/ncsim_waves.rc" >> ./ncsim.args
+else
+ echo "-input ../bin/ncsim.rc" >> ./ncsim.args
+endif
+echo "worklib.ethernet:fun" >> ./ncsim.args
+
+ncsim -file ./ncsim.args > ../log/tb_eth_display.log #| tee ../log/tb_eth_display.log
+if ($status != 0) then
+ echo ""
+ echo "TESTS couldn't start due to Errors!"
+ echo ""
+ exit
+else
+ if ($arg_regression == 1) then
+ if ($arg_waves == 1) then
+ mv ../out/waves.shm ../out/i${iter}_waves.shm
+ endif
+ # For ATS - counting all 'FAILED' words
+ set FAIL_COUNT = `grep -c "FAILED" ../log/eth_tb.log`
+ if ($FAIL_COUNT != 0) then
+ # Test didn't pass!!!
+ @ ok = 0;
+ endif
+ # Move 'log' files
+ mv ../log/eth_tb.log ../log/i${iter}_eth_tb.log
+ mv ../log/eth_tb_phy.log ../log/i${iter}_eth_tb_phy.log
+ mv ../log/eth_tb_memory.log ../log/i${iter}_eth_tb_memory.log
+ mv ../log/eth_tb_host.log ../log/i${iter}_eth_tb_host.log
+ mv ../log/eth_tb_wb_s_mon.log ../log/i${iter}_eth_tb_wb_s_mon.log
+ mv ../log/eth_tb_wb_m_mon.log ../log/i${iter}_eth_tb_wb_m_mon.log
+ endif
+endif
+echo ""
+
+@ iter += 1;
+
+if (($arg_regression == 1) && ($iter <= $all_iterations)) then
+ goto iteration
+else
+# rm ./defines.args
+ echo ""
+ echo "<<<"
+ echo "<<< End of VERIFICATION"
+ echo "<<<"
+ echo "<<<"
+ echo "<<< -------------------------------------------------"
+ echo "<<<"
+ # For ATS - displaying 'OK' when tests pass successfuly
+ echo " "
+ echo "Simulation finished:"
+ if ($ok == 1) then
+ echo "OK"
+ else
+ echo "FAILED"
+ endif
+endif
+
/ncsim_sim/run/top_groups.do
0,0 → 1,441
// Signalscan Version 6.7p1 |
|
|
define noactivityindicator |
define analog waveform lines |
define add variable default overlay off |
define waveform window analogheight 1 |
define terminal automatic |
define buttons control \ |
1 opensimmulationfile \ |
2 executedofile \ |
3 designbrowser \ |
4 waveform \ |
5 source \ |
6 breakpoints \ |
7 definesourcessearchpath \ |
8 exit \ |
9 createbreakpoint \ |
10 creategroup \ |
11 createmarker \ |
12 closesimmulationfile \ |
13 renamesimmulationfile \ |
14 replacesimulationfiledata \ |
15 listopensimmulationfiles \ |
16 savedofile |
define buttons waveform \ |
1 undo \ |
2 cut \ |
3 copy \ |
4 paste \ |
5 delete \ |
6 zoomin \ |
7 zoomout \ |
8 zoomoutfull \ |
9 expand \ |
10 createmarker \ |
11 designbrowser:1 \ |
12 variableradixbinary \ |
13 variableradixoctal \ |
14 variableradixdecimal \ |
15 variableradixhexadecimal \ |
16 variableradixascii |
define buttons designbrowser \ |
1 undo \ |
2 cut \ |
3 copy \ |
4 paste \ |
5 delete \ |
6 cdupscope \ |
7 getallvariables \ |
8 getdeepallvariables \ |
9 addvariables \ |
10 addvarsandclosewindow \ |
11 closewindow \ |
12 scopefiltermodule \ |
13 scopefiltertask \ |
14 scopefilterfunction \ |
15 scopefilterblock \ |
16 scopefilterprimitive |
define buttons event \ |
1 undo \ |
2 cut \ |
3 copy \ |
4 paste \ |
5 delete \ |
6 move \ |
7 closewindow \ |
8 duplicate \ |
9 defineasrisingedge \ |
10 defineasfallingedge \ |
11 defineasanyedge \ |
12 variableradixbinary \ |
13 variableradixoctal \ |
14 variableradixdecimal \ |
15 variableradixhexadecimal \ |
16 variableradixascii |
define buttons source \ |
1 undo \ |
2 cut \ |
3 copy \ |
4 paste \ |
5 delete \ |
6 createbreakpoint \ |
7 creategroup \ |
8 createmarker \ |
9 createevent \ |
10 createregisterpage \ |
11 closewindow \ |
12 opensimmulationfile \ |
13 closesimmulationfile \ |
14 renamesimmulationfile \ |
15 replacesimulationfiledata \ |
16 listopensimmulationfiles |
define buttons register \ |
1 undo \ |
2 cut \ |
3 copy \ |
4 paste \ |
5 delete \ |
6 createregisterpage \ |
7 closewindow \ |
8 continuefor \ |
9 continueuntil \ |
10 continueforever \ |
11 stop \ |
12 previous \ |
13 next \ |
14 variableradixbinary \ |
15 variableradixhexadecimal \ |
16 variableradixascii |
define show related transactions |
define exit prompt |
define event search direction forward |
define variable nofullhierarchy |
define variable nofilenames |
define variable nofullpathfilenames |
include bookmark with filenames |
include scope history without filenames |
define waveform window listpane 11 |
define waveform window namepane 16 |
define multivalueindication |
define pattern curpos dot |
define pattern cursor1 dot |
define pattern cursor2 dot |
define pattern marker dot |
define print designer "Miha Dolenc" |
define print border |
define print color blackonwhite |
define print command "/usr/ucb/lpr -P%P" |
define print printer lp |
define print range visible |
define print variable visible |
define rise fall time low threshold percentage 10 |
define rise fall time high threshold percentage 90 |
define rise fall time low value 0 |
define rise fall time high value 3.3 |
define sendmail command "/usr/lib/sendmail" |
define sequence time width 30.00 |
define snap |
|
define source noprompt |
define time units default |
define userdefinedbussymbol |
define user guide directory "/usr/local/designacc/signalscan-6.7p1/doc/html" |
define waveform window grid off |
define waveform window waveheight 14 |
define waveform window wavespace 6 |
define web browser command netscape |
define zoom outfull on initial add off |
add group \ |
A \ |
|
add group \ |
"WISHBONE common" \ |
tb_ethernet.eth_top.wb_clk_i \ |
tb_ethernet.eth_top.wb_rst_i \ |
tb_ethernet.eth_top.wb_dat_i[31:0]'h \ |
tb_ethernet.eth_top.wb_dat_o[31:0]'h \ |
tb_ethernet.eth_top.wb_err_o \ |
|
add group \ |
"WISHBONE slave signals" \ |
tb_ethernet.eth_sl_wb_dat_i[31:0]'h \ |
tb_ethernet.eth_sl_wb_dat_o[31:0]'h \ |
tb_ethernet.eth_top.wb_adr_i[11:2]'h \ |
tb_ethernet.eth_top.wb_sel_i[3:0]'h \ |
tb_ethernet.eth_top.wb_we_i \ |
tb_ethernet.eth_top.wb_cyc_i \ |
tb_ethernet.eth_top.wb_stb_i \ |
tb_ethernet.eth_top.wb_ack_o \ |
|
add group \ |
"WISHBONE master signals" \ |
tb_ethernet.eth_top.m_wb_adr_o[31:0]'h \ |
tb_ethernet.eth_top.m_wb_sel_o[3:0]'h \ |
tb_ethernet.eth_top.m_wb_we_o \ |
tb_ethernet.eth_top.m_wb_dat_i[31:0]'h \ |
tb_ethernet.eth_top.m_wb_dat_o[31:0]'h \ |
tb_ethernet.eth_top.m_wb_cyc_o \ |
tb_ethernet.eth_top.m_wb_stb_o \ |
tb_ethernet.eth_top.m_wb_ack_i \ |
tb_ethernet.eth_top.m_wb_err_i \ |
|
add group \ |
"WISHBONE RX memory" \ |
tb_ethernet.eth_top.wishbone.TxLength[15:0]'h \ |
tb_ethernet.eth_top.wishbone.TxLengthEq0 \ |
tb_ethernet.eth_top.wishbone.TxLengthLt4 \ |
tb_ethernet.eth_top.wishbone.TxPointerLSB[1:0]'h \ |
tb_ethernet.eth_top.wishbone.TxPointerLSB_rst[1:0]'h \ |
tb_ethernet.eth_top.wishbone.TxPointerMSB[31:2]'h \ |
tb_ethernet.eth_top.wishbone.TxPointerRead \ |
tb_ethernet.eth_top.wishbone.TxBDReady \ |
tb_ethernet.eth_top.wishbone.TxBufferAlmostEmpty \ |
tb_ethernet.eth_top.wishbone.TxBufferAlmostFull \ |
tb_ethernet.eth_top.wishbone.TxBufferEmpty \ |
tb_ethernet.eth_top.wishbone.TxBufferFull \ |
tb_ethernet.eth_top.wishbone.TxData_wb[31:0]'h \ |
tb_ethernet.eth_top.wishbone.TxData[7:0]'h \ |
tb_ethernet.eth_top.wishbone.TxDataLatched[31:0]'h \ |
tb_ethernet.eth_top.wishbone.TxByteCnt[1:0]'h \ |
tb_ethernet.eth_top.wishbone.TxStatus[14:11]'h \ |
tb_ethernet.eth_top.wishbone.TxStatusInLatched[8:0]'h \ |
tb_ethernet.test_mac_full_duplex_transmit.max_tmp[15:0]'h \ |
tb_ethernet.test_mac_full_duplex_transmit.min_tmp[15:0]'h \ |
tb_ethernet.test_mac_full_duplex_transmit.i_length'h \ |
tb_ethernet.eth_phy.tx_len[31:0]'h \ |
tb_ethernet.eth_phy.tx_len_err[31:0]'h \ |
tb_ethernet.eth_phy.tx_cnt[31:0]'h \ |
tb_ethernet.eth_phy.tx_byte_aligned_ok \ |
tb_ethernet.wb_slave.CYC_I \ |
tb_ethernet.wb_slave.STB_I \ |
tb_ethernet.wb_slave.WE_I \ |
tb_ethernet.wb_slave.ADR_I[31:0]'h \ |
tb_ethernet.wb_slave.DAT_I[31:0]'h \ |
tb_ethernet.wb_slave.SEL_I[3:0]'h \ |
tb_ethernet.wb_slave.ACK_O \ |
tb_ethernet.wb_slave.ERR_O \ |
tb_ethernet.wb_slave.RTY_O \ |
tb_ethernet.wb_slave.mem_wr_data_out[31:0]'h \ |
tb_ethernet.test_mac_full_duplex_receive.num_of_frames's \ |
tb_ethernet.test_mac_full_duplex_receive.first_fr_received \ |
tb_ethernet.test_mac_full_duplex_receive.bit_end_1's \ |
tb_ethernet.test_mac_full_duplex_receive.bit_end_2's \ |
tb_ethernet.test_mac_full_duplex_receive.bit_start_1's \ |
tb_ethernet.test_mac_full_duplex_receive.bit_start_2's \ |
tb_ethernet.test_mac_full_duplex_receive.burst_data[32767:0]'h \ |
tb_ethernet.test_mac_full_duplex_receive.burst_tmp_data[32767:0]'h \ |
tb_ethernet.test_mac_full_duplex_receive.check_frame \ |
tb_ethernet.test_mac_full_duplex_receive.data[31:0]'h \ |
tb_ethernet.test_mac_full_duplex_receive.end_task[31:0]'h \ |
tb_ethernet.test_mac_full_duplex_receive.fail's \ |
tb_ethernet.test_mac_full_duplex_receive.first_fr_received \ |
tb_ethernet.test_mac_full_duplex_receive.frame_ended \ |
tb_ethernet.test_mac_full_duplex_receive.frame_started \ |
tb_ethernet.test_mac_full_duplex_receive.i's \ |
tb_ethernet.test_mac_full_duplex_receive.i1's \ |
tb_ethernet.test_mac_full_duplex_receive.i2's \ |
tb_ethernet.test_mac_full_duplex_receive.i3's \ |
tb_ethernet.test_mac_full_duplex_receive.i_addr's \ |
tb_ethernet.test_mac_full_duplex_receive.i_data's \ |
tb_ethernet.test_mac_full_duplex_receive.i_length's \ |
tb_ethernet.test_mac_full_duplex_receive.max_tmp[15:0]'h \ |
tb_ethernet.test_mac_full_duplex_receive.min_tmp[15:0]'h \ |
tb_ethernet.test_mac_full_duplex_receive.num_of_bd's \ |
tb_ethernet.test_mac_full_duplex_receive.num_of_frames's \ |
tb_ethernet.test_mac_full_duplex_receive.num_of_reg's \ |
tb_ethernet.test_mac_full_duplex_receive.speed's \ |
tb_ethernet.test_mac_full_duplex_receive.st_data[7:0]'h \ |
tb_ethernet.test_mac_full_duplex_receive.start_task[31:0]'h \ |
tb_ethernet.test_mac_full_duplex_receive.stop_checking_frame \ |
tb_ethernet.test_mac_full_duplex_receive.test_num's \ |
tb_ethernet.test_mac_full_duplex_receive.tmp[31:0]'h \ |
tb_ethernet.test_mac_full_duplex_receive.tmp_bd'h \ |
tb_ethernet.test_mac_full_duplex_receive.tmp_bd_num's \ |
tb_ethernet.test_mac_full_duplex_receive.tmp_data's \ |
tb_ethernet.test_mac_full_duplex_receive.tmp_ipgt's \ |
tb_ethernet.test_mac_full_duplex_receive.tmp_len's \ |
tb_ethernet.test_mac_full_duplex_receive.tx_bd_num[31:0]'h \ |
tb_ethernet.test_mac_full_duplex_receive.wait_for_frame \ |
tb_ethernet.wbm_working \ |
tb_ethernet.check_rx_packet.addr_phy[31:0]'h \ |
tb_ethernet.check_rx_packet.addr_wb[31:0]'h \ |
tb_ethernet.check_rx_packet.buffer[21:0]'h \ |
tb_ethernet.check_rx_packet.data_phy'h \ |
tb_ethernet.check_rx_packet.data_wb'h \ |
tb_ethernet.check_rx_packet.delta_t \ |
tb_ethernet.check_rx_packet.failure[31:0]'h \ |
tb_ethernet.check_rx_packet.i's \ |
tb_ethernet.check_rx_packet.len[15:0]'h \ |
tb_ethernet.check_rx_packet.plus_dribble_nibble \ |
tb_ethernet.check_rx_packet.rxpnt_phy[31:0]'h \ |
tb_ethernet.check_rx_packet.rxpnt_wb[31:0]'h \ |
tb_ethernet.check_rx_packet.successful_dribble_nibble \ |
tb_ethernet.wb_slave.rd_mem.adr_i[31:0]'h \ |
tb_ethernet.wb_slave.rd_mem.dat_o[31:0]'h \ |
tb_ethernet.wb_slave.rd_mem.sel_i[3:0]'h \ |
tb_ethernet.wb_slave.ADR_I[31:0]'h \ |
tb_ethernet.wb_slave.mem_wr_data_out[31:0]'h \ |
tb_ethernet.wb_slave.SEL_I[3:0]'h \ |
|
add group \ |
"MAC FIFO" \ |
tb_ethernet.eth_top.wishbone.rx_fifo.write \ |
tb_ethernet.eth_top.wishbone.rx_fifo.data_in[31:0]'h \ |
tb_ethernet.eth_top.wishbone.rx_fifo.write_pointer[3:0]'h \ |
tb_ethernet.eth_top.wishbone.rx_fifo.almost_full \ |
tb_ethernet.eth_top.wishbone.rx_fifo.full \ |
tb_ethernet.eth_top.wishbone.rx_fifo.read \ |
tb_ethernet.eth_top.wishbone.rx_fifo.data_out[31:0]'h \ |
tb_ethernet.eth_top.wishbone.rx_fifo.read_pointer[3:0]'h \ |
tb_ethernet.eth_top.wishbone.rx_fifo.almost_empty \ |
tb_ethernet.eth_top.wishbone.rx_fifo.empty \ |
|
add group \ |
"MAC registers" \ |
tb_ethernet.eth_top.ethreg1.MODEROut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.INT_SOURCEOut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.INT_MASKOut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.IPGTOut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.IPGR1Out[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.IPGR2Out[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.PACKETLENOut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.COLLCONFOut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.TX_BD_NUMOut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.CTRLMODEROut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.MIIMODEROut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.MIICOMMANDOut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.MIIADDRESSOut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.MIITX_DATAOut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.MIIRX_DATAOut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.MIISTATUSOut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.MAC_ADDR0Out[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.MAC_ADDR1Out[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.HASH0Out[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.HASH1Out[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.TXCTRLOut[31:0]'h \ |
|
add group \ |
testbench_test_signals \ |
tb_ethernet.test_mac_full_duplex_transmit.i_length's \ |
tb_ethernet.test_mac_full_duplex_transmit.tmp_len's \ |
|
add group \ |
"MAC common" \ |
tb_ethernet.eth_top.mcoll_pad_i \ |
tb_ethernet.eth_top.mcrs_pad_i \ |
|
add group \ |
"MAC TX" \ |
tb_ethernet.eth_top.mtx_clk_pad_i \ |
tb_ethernet.eth_top.mtxd_pad_o[3:0]'h \ |
tb_ethernet.eth_top.mtxen_pad_o \ |
tb_ethernet.eth_top.mtxerr_pad_o \ |
|
add group \ |
"MAC RX" \ |
tb_ethernet.eth_top.mrx_clk_pad_i \ |
tb_ethernet.eth_top.mrxd_pad_i[3:0]'h \ |
tb_ethernet.eth_top.mrxdv_pad_i \ |
tb_ethernet.eth_top.mrxerr_pad_i \ |
|
add group \ |
"MAC MIIM interface" \ |
tb_ethernet.eth_top.mdc_pad_o \ |
tb_ethernet.eth_top.md_padoe_o \ |
tb_ethernet.eth_top.md_pad_o \ |
tb_ethernet.eth_top.md_pad_i \ |
tb_ethernet.eth_top.miim1.Busy \ |
tb_ethernet.eth_top.miim1.LinkFail \ |
tb_ethernet.eth_top.miim1.Nvalid \ |
tb_ethernet.eth_top.miim1.CtrlData[15:0]'h \ |
tb_ethernet.eth_top.miim1.UpdateMIIRX_DATAReg \ |
tb_ethernet.eth_top.miim1.Prsd[15:0]'h \ |
tb_ethernet.eth_top.miim1.Divider[7:0]'h \ |
|
add group \ |
"Test signals" \ |
tb_ethernet.test_name[799:0]'a \ |
tb_ethernet.eth_top.miim1.Nvalid \ |
tb_ethernet.eth_top.miim1.Busy \ |
tb_ethernet.eth_top.miim1.LinkFail \ |
tb_ethernet.eth_top.miim1.WriteDataOp \ |
tb_ethernet.eth_top.miim1.ReadStatusOp \ |
tb_ethernet.eth_top.miim1.ScanStatusOp \ |
tb_ethernet.eth_top.ethreg1.MIISTATUSOut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.MIITX_DATAOut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.MIIRX_DATAOut[31:0]'h \ |
tb_ethernet.eth_top.ethreg1.MIIMODEROut[31:0]'h \ |
tb_ethernet.eth_top.miim1.InProgress \ |
tb_ethernet.eth_top.miim1.InProgress_q1 \ |
tb_ethernet.eth_top.miim1.InProgress_q2 \ |
tb_ethernet.eth_top.miim1.InProgress_q3 \ |
tb_ethernet.eth_top.miim1.shftrg.ShiftReg[7:0]'h \ |
tb_ethernet.eth_phy.status_bit6_0[6:0]'h \ |
tb_ethernet.eth_phy.control_bit8_0[8:0]'h \ |
tb_ethernet.eth_phy.control_bit9 \ |
tb_ethernet.eth_phy.control_bit14_10[14:10]'h \ |
tb_ethernet.eth_phy.control_bit15 \ |
tb_ethernet.eth_phy.eth_speed \ |
tb_ethernet.eth_phy.m_rst_n_i \ |
tb_ethernet.eth_phy.mcoll_o \ |
tb_ethernet.eth_phy.mcrs_o \ |
tb_ethernet.eth_phy.md_get_phy_address \ |
tb_ethernet.eth_phy.md_get_reg_address \ |
tb_ethernet.eth_phy.md_get_reg_data_in \ |
tb_ethernet.eth_phy.md_put_reg_data_in \ |
tb_ethernet.eth_phy.md_put_reg_data_out \ |
tb_ethernet.eth_phy.reg_data_in[15:0]'h \ |
tb_ethernet.eth_phy.reg_data_out[15:0]'h \ |
tb_ethernet.eth_phy.register_bus_in[15:0]'h \ |
tb_ethernet.eth_phy.register_bus_out[15:0]'h \ |
tb_ethernet.eth_phy.reg_address[4:0]'h \ |
tb_ethernet.eth_phy.md_io_output \ |
tb_ethernet.eth_phy.md_io_enable \ |
tb_ethernet.eth_phy.md_io \ |
tb_ethernet.Mdc_O \ |
tb_ethernet.Mdi_I \ |
tb_ethernet.Mdio_IO \ |
tb_ethernet.Mdo_O \ |
tb_ethernet.Mdo_OE \ |
tb_ethernet.eth_phy.md_io_enable \ |
tb_ethernet.eth_phy.md_io_output \ |
tb_ethernet.eth_phy.md_io_rd_wr \ |
tb_ethernet.eth_phy.md_io_reg \ |
tb_ethernet.eth_phy.m_rst_n_i \ |
tb_ethernet.eth_phy.md_transfer_cnt'd \ |
tb_ethernet.eth_phy.md_transfer_cnt_reset \ |
tb_ethernet.eth_phy.mdc_i \ |
tb_ethernet.eth_phy.mrx_clk_o \ |
tb_ethernet.eth_phy.mrxd_o[3:0]'h \ |
tb_ethernet.eth_phy.mrxdv_o \ |
tb_ethernet.eth_phy.mrxerr_o \ |
tb_ethernet.eth_phy.mtx_clk_o \ |
tb_ethernet.eth_phy.mtxd_i[3:0]'h \ |
tb_ethernet.eth_phy.mtxen_i \ |
tb_ethernet.eth_phy.mtxerr_i \ |
tb_ethernet.eth_phy.phy_address[4:0]'h \ |
tb_ethernet.eth_phy.phy_id1[15:0]'h \ |
tb_ethernet.eth_phy.phy_id2[15:0]'h \ |
tb_ethernet.eth_phy.phy_log[31:0]'h \ |
tb_ethernet.eth_phy.reg_address[4:0]'h \ |
tb_ethernet.eth_phy.register_bus_in[15:0]'h \ |
tb_ethernet.eth_phy.register_bus_out[15:0]'h \ |
tb_ethernet.eth_phy.registers_addr_data_test_operation \ |
tb_ethernet.eth_phy.rx_link_down_halfperiod \ |
( \ |
minmax 0 93 \ |
) \ |
tb_ethernet.eth_phy.self_clear_d0 \ |
tb_ethernet.eth_phy.self_clear_d1 \ |
tb_ethernet.eth_phy.self_clear_d2 \ |
tb_ethernet.eth_phy.self_clear_d3 \ |
tb_ethernet.eth_phy.status_bit6_0[6:0]'h \ |
tb_ethernet.eth_phy.status_bit7 \ |
tb_ethernet.eth_phy.status_bit8 \ |
tb_ethernet.eth_phy.status_bit15_9[15:9]'h \ |
|
|
deselect all |
open window designbrowser 1 geometry 56 121 855 550 |
/ncsim_sim/run/clean
0,0 → 1,4
rm ../bin/INCA_libs/worklib/* |
rm ../bin/INCA_libs/worklib/.* |
rm ../log/*.log |
rm -rf ../out/*.shm |
/ncsim_sim/bin/sim_file_list.lst
0,0 → 1,9
../../../../bench/verilog/tb_ethernet.v |
../../../../bench/verilog/tb_eth_defines.v |
../../../../bench/verilog/eth_phy.v |
../../../../bench/verilog/eth_phy_defines.v |
../../../../bench/verilog/wb_bus_mon.v |
../../../../bench/verilog/wb_slave_behavioral.v |
../../../../bench/verilog/wb_master32.v |
../../../../bench/verilog/wb_master_behavioral.v |
|
/ncsim_sim/bin/xilinx_file_list.lst
0,0 → 1,4
../../../../../../lib/xilinx/lib/glbl/glbl.v |
../../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v |
../../../../../../lib/xilinx/lib/unisims/RAMB4_S8.v |
../../../../../../lib/xilinx/lib/unisims/RAM16X1D.v |
/ncsim_sim/bin/artisan_file_list.lst
0,0 → 1,3
../../../../../../lib/artisan/art_hssp_256x32/art_hssp_256x32_bw.v |
../../../../../../lib/artisan/art_hssp_256x32/art_hssp_256x32_bw_bist.v |
|
/ncsim_sim/bin/vs_file_list.lst
0,0 → 1,3
../../../../../../lib/vs_rams/018/vs_hdsp_256x32/vs_hdsp_256x32.v |
/ncsim_sim/bin/rtl_file_list.lst
0,0 → 1,25
../../../../rtl/verilog/eth_crc.v |
../../../../rtl/verilog/eth_defines.v |
../../../../rtl/verilog/eth_maccontrol.v |
../../../../rtl/verilog/eth_macstatus.v |
../../../../rtl/verilog/eth_miim.v |
../../../../rtl/verilog/eth_outputcontrol.v |
../../../../rtl/verilog/eth_random.v |
../../../../rtl/verilog/eth_receivecontrol.v |
../../../../rtl/verilog/eth_register.v |
../../../../rtl/verilog/eth_registers.v |
../../../../rtl/verilog/eth_rxcounters.v |
../../../../rtl/verilog/eth_rxethmac.v |
../../../../rtl/verilog/eth_rxstatem.v |
../../../../rtl/verilog/eth_shiftreg.v |
../../../../rtl/verilog/timescale.v |
../../../../rtl/verilog/eth_top.v |
../../../../rtl/verilog/eth_transmitcontrol.v |
../../../../rtl/verilog/eth_txcounters.v |
../../../../rtl/verilog/eth_txethmac.v |
../../../../rtl/verilog/eth_txstatem.v |
../../../../rtl/verilog/eth_clockgen.v |
../../../../rtl/verilog/eth_spram_256x32.v |
../../../../rtl/verilog/eth_wishbone.v |
../../../../rtl/verilog/eth_fifo.v |
../../../../rtl/verilog/eth_rxaddrcheck.v |
/ncsim_sim/bin/INCA_libs/worklib/dir_keeper
--- ncsim_sim/bin/ncelab.args (nonexistent)
+++ ncsim_sim/bin/ncelab.args (revision 338)
@@ -0,0 +1,7 @@
+-snapshot worklib.ethernet:fun
+-cdslib ../bin/cds.lib
+-logfile ../log/ncelab.log
+-access +wc
+-messages
+-no_tchk_msg
+-v93 worklib.tb_ethernet
/ncsim_sim/bin/ncsim_waves.rc
0,0 → 1,7
set dump_level all |
|
database -open waves -shm -into ../out/waves.shm |
probe -create -database waves tb_ethernet -shm -all -depth $dump_level |
|
run |
quit |
/ncsim_sim/bin/ncelab_xilinx.args
0,0 → 1,9
-snapshot worklib.ethernet:fun |
-cdslib ../bin/cds.lib |
-hdlvar ../bin/hdl.var |
-logfile ../log/ncelab_xilinx.log |
-access +wc |
-messages |
-no_tchk_msg |
-v93 |
worklib.tb_ethernet worklib.glbl |
/ncsim_sim/bin/ncsim.rc
0,0 → 1,2
run |
quit |
/ncsim_sim/bin/cds.lib
0,0 → 1,2
define worklib ../bin/INCA_libs/worklib |
include $CDS_INST_DIR/tools/inca/files/cds.lib |
/ncsim_sim/bin/hdl.var
0,0 → 1,9
# |
# hdl.var: Defines variables used by the INCA tools. |
# Created by ncprep on Sat Aug 4 10:51:23 2001 |
# |
|
softinclude $CDS_INST_DIR/tools/inca/files/hdl.var |
|
define LIB_MAP ( $LIB_MAP, + => worklib ) |
define VIEW_MAP ( $VIEW_MAP, .v => v) |
/ncsim_sim/out/dir_keeper
--- bin/sim_file_list.lst (nonexistent)
+++ bin/sim_file_list.lst (revision 338)
@@ -0,0 +1,14 @@
+../../../bench/verilog/tb_ethernet.v
+../../../bench/verilog/tb_eth_defines.v
+../../../bench/verilog/eth_phy.v
+../../../bench/verilog/eth_phy_defines.v
+../../../bench/verilog/wb_bus_mon.v
+../../../bench/verilog/wb_slave_behavioral.v
+../../../bench/verilog/wb_master32.v
+../../../bench/verilog/wb_master_behavioral.v
+../../../../../lib/artisan/art_hssp_256x32_bist.v
+../../../../../lib/artisan/art_hssp_256x32/art_hssp_256x32.v
+../../../../../bist/rtl/verilog/bist.v
+../../../../../bist/rtl/verilog/bist_sp_top.v
+
+
bin/sim_file_list.lst
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: bin/rtl_file_list.lst
===================================================================
--- bin/rtl_file_list.lst (nonexistent)
+++ bin/rtl_file_list.lst (revision 338)
@@ -0,0 +1,26 @@
+../../../rtl/verilog/eth_crc.v
+../../../rtl/verilog/eth_defines.v
+../../../rtl/verilog/eth_maccontrol.v
+../../../rtl/verilog/eth_macstatus.v
+../../../rtl/verilog/eth_miim.v
+../../../rtl/verilog/eth_outputcontrol.v
+../../../rtl/verilog/eth_random.v
+../../../rtl/verilog/eth_receivecontrol.v
+../../../rtl/verilog/eth_register.v
+../../../rtl/verilog/eth_registers.v
+../../../rtl/verilog/eth_rxcounters.v
+../../../rtl/verilog/eth_rxethmac.v
+../../../rtl/verilog/eth_rxstatem.v
+../../../rtl/verilog/eth_shiftreg.v
+../../../rtl/verilog/timescale.v
+../../../rtl/verilog/eth_top.v
+../../../rtl/verilog/eth_transmitcontrol.v
+../../../rtl/verilog/eth_txcounters.v
+../../../rtl/verilog/eth_txethmac.v
+../../../rtl/verilog/eth_txstatem.v
+../../../rtl/verilog/eth_clockgen.v
+../../../rtl/verilog/eth_spram_256x32.v
+../../../rtl/verilog/eth_wishbone.v
+../../../rtl/verilog/eth_fifo.v
+../../../rtl/verilog/eth_rxaddrcheck.v
+../../../rtl/verilog/xilinx_dist_ram_16x32.v
bin/rtl_file_list.lst
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: bin/ncelab.args
===================================================================
--- bin/ncelab.args (nonexistent)
+++ bin/ncelab.args (revision 338)
@@ -0,0 +1,7 @@
+-snapshot worklib.ethernet:fun
+-cdslib ../bin/cds.lib
+-logfile ../log/ncelab.log
+-access +wc
+-messages
+-no_tchk_msg
+-v93 worklib.tb_ethernet
bin/ncelab.args
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: bin/ncelab_xilinx.args
===================================================================
--- bin/ncelab_xilinx.args (nonexistent)
+++ bin/ncelab_xilinx.args (revision 338)
@@ -0,0 +1,9 @@
+-snapshot worklib.ethernet:fun
+-cdslib ../bin/cds.lib
+-hdlvar ../bin/hdl.var
+-logfile ../log/ncelab_xilinx.log
+-access +wc
+-messages
+-no_tchk_msg
+-v93
+worklib.tb_ethernet worklib.glbl
bin/ncelab_xilinx.args
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: bin/ncsim_waves.rc
===================================================================
--- bin/ncsim_waves.rc (nonexistent)
+++ bin/ncsim_waves.rc (revision 338)
@@ -0,0 +1,7 @@
+set dump_level all
+
+database -open waves -shm -into ../out/waves.shm
+probe -create -database waves tb_ethernet -shm -all -depth $dump_level
+
+run
+quit
bin/ncsim_waves.rc
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: bin/INCA_libs/worklib/dir_keeper
===================================================================
Index: bin/xilinx_file_list.lst
===================================================================
--- bin/xilinx_file_list.lst (nonexistent)
+++ bin/xilinx_file_list.lst (revision 338)
@@ -0,0 +1,4 @@
+../../../../../lib/xilinx/lib/glbl/glbl.v
+../../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v
+../../../../../lib/xilinx/lib/unisims/RAMB4_S16.v
+../../../../../lib/xilinx/lib/unisims/RAM16X1D.v
bin/xilinx_file_list.lst
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: bin/artisan_file_list.lst
===================================================================
--- bin/artisan_file_list.lst (nonexistent)
+++ bin/artisan_file_list.lst (revision 338)
@@ -0,0 +1,8 @@
+-cdslib ../bin/cds.lib
+-hdlvar ../bin/hdl.var
+-logfile ../log/ncvlog_artisan.log
+-update
+-messages
+../../../../../../lib/artisan/art_hsdp_256x40.v
+../../../../../../lib/artisan/art_hddp_8192x64.v
+
bin/artisan_file_list.lst
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: bin/ncsim.rc
===================================================================
--- bin/ncsim.rc (nonexistent)
+++ bin/ncsim.rc (revision 338)
@@ -0,0 +1,2 @@
+run
+quit
bin/ncsim.rc
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: bin/run_sim
===================================================================
--- bin/run_sim (nonexistent)
+++ bin/run_sim (revision 338)
@@ -0,0 +1,47 @@
+#!/bin/csh -f
+
+set arg_num = $#argv; # number of arguments
+
+if ($arg_num < 1) then
+ echo " "
+ echo "Missing required ATS argument:"
+ echo " '-r' for regression"
+ echo " "
+ exit
+endif
+
+set cur_arg = 1
+set arg_chk = 0
+
+set regression = 0
+
+while ($cur_arg <= $arg_num)
+ if ("$argv[$cur_arg]" == "-r") then
+ @ regression = 1
+ @ arg_chk = $arg_chk + 1
+ endif
+
+ if ($arg_chk != $cur_arg) then
+ echo " "
+ echo "Invalid argument $argv[$cur_arg]"
+ echo " "
+ exit
+ endif
+
+ @ cur_arg = $cur_arg + 1
+end
+
+if ($regression == 0) then
+ echo " "
+ echo "Missing required ATS argument:"
+ echo " '-r' for regression"
+ echo " "
+ exit
+else
+ echo " "
+ echo "ATS running ethernet script with following argument:"
+ echo " '-r' for regression"
+ echo " "
+ ../run/run_eth_sim_regr.scr -r
+endif
+
bin/run_sim
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: bin/cds.lib
===================================================================
--- bin/cds.lib (nonexistent)
+++ bin/cds.lib (revision 338)
@@ -0,0 +1,2 @@
+define worklib ../bin/INCA_libs/worklib
+include $CDS_INST_DIR/tools/inca/files/cds.lib
bin/cds.lib
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: bin/hdl.var
===================================================================
--- bin/hdl.var (nonexistent)
+++ bin/hdl.var (revision 338)
@@ -0,0 +1,9 @@
+#
+# hdl.var: Defines variables used by the INCA tools.
+# Created by ncprep on Sat Aug 4 10:51:23 2001
+#
+
+softinclude $CDS_INST_DIR/tools/inca/files/hdl.var
+
+define LIB_MAP ( $LIB_MAP, + => worklib )
+define VIEW_MAP ( $VIEW_MAP, .v => v)
bin/hdl.var
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: run/run_eth_sim_regr.scr
===================================================================
--- run/run_eth_sim_regr.scr (nonexistent)
+++ run/run_eth_sim_regr.scr (revision 338)
@@ -0,0 +1,218 @@
+#!/bin/csh -f
+
+set arg_num = $#argv; # number of arguments
+
+# current iterration
+set iter = 1;
+# number of tests with DEFINES + test with user defined constants!
+set all_iterations = 3;
+# ATS (Automatic Test System) parameter, which causes displaying 'OK'
+# if all testcases finish OK.
+set ok = 1;
+
+# Process argument
+set arg_waves = 0;
+set arg_regression = 0;
+
+if ($arg_num == 0) then
+ echo " Verification without any parameter !"
+else
+ if ($arg_num == 1) then
+ if (("$1" == "waves") | ("$1" == "-w")) then
+ @ arg_waves = 1;
+ echo " Verification with parameter : waves !"
+ else
+ if (("$1" == "regression") | ("$1" == "-r")) then
+ @ arg_regression = 1;
+ echo " Verification with parameter : regression !"
+ else
+ echo " Not correct parameter ( $1 )"
+ echo " Correct parameters are:"
+ echo " 'waves' or '-w'"
+ echo " 'regression' or '-r'"
+ exit
+ endif
+ endif
+ else
+ if ($arg_num == 2) then
+ if (("$1" == "waves") | ("$1" == "-w")) then
+ @ arg_waves = 1;
+ if (("$2" == "regression") | ("$2" == "-r")) then
+ @ arg_regression = 1;
+ echo " Verification with parameter : waves, regression !"
+ else
+ echo " Not correct parameter ( $2 )"
+ echo " Correct 2. parameter is:"
+ echo " 'regression' or '-r'"
+ exit
+ endif
+ else
+ if (("$1" == "regression") | ("$1" == "-r")) then
+ @ arg_regression = 1;
+ if (("$2" == "waves") | ("$2" == "-w")) then
+ @ arg_waves = 1;
+ echo " Verification with parameter : waves, regression !"
+ else
+ echo " Not correct parameter ( $2 )"
+ echo " Correct 2. parameter is:"
+ echo " 'waves' or '-w'"
+ exit
+ endif
+ else
+ echo " Not correct parameter ( $1 )"
+ echo " Correct parameters are:"
+ echo " 'waves' or '-w'"
+ echo " 'regression' or '-r'"
+ exit
+ endif
+ endif
+ else
+ echo " Too many parameters ( $arg_num )"
+ echo " Maximum number of parameters is 2:"
+ echo " 'waves' or '-w'"
+ echo " 'regression' or '-r'"
+ exit
+ endif
+ endif
+endif
+
+echo ""
+echo "<<<"
+echo "<<< Ethernet MAC VERIFICATION "
+echo "<<<"
+
+# ITERATION LOOP
+iteration:
+
+echo ""
+echo "<<<"
+echo "<<< Iteration ${iter}"
+echo "<<<"
+
+if ($arg_regression == 1) then
+ if ($iter <= $all_iterations) then
+ if ($iter == 1) then
+ echo "<<< Defines:"
+ echo "\tEthernet with GENERIC RAM"
+ echo "-DEFINE REGR" > ../run/defines.args
+ endif
+ if ($iter == 2) then
+ echo "<<< Defines:"
+ echo "\tEthernet with XILINX DISTRIBUTED RAM"
+ echo "-DEFINE REGR -DEFINE ETH_FIFO_XILINX" > ../run/defines.args
+ endif
+ if ($iter == 3) then
+ echo "<<< Defines:"
+ echo "\tEthernet with XILINX BLOCK RAM"
+ echo "-DEFINE REGR -DEFINE XILINX_RAMB4" > ../run/defines.args
+ endif
+ endif
+endif
+
+# Run NC-Verilog compiler
+echo ""
+echo "\t@@@"
+echo "\t@@@ Compiling sources"
+echo "\t@@@"
+
+# creating .args file for ncvlog and adding main parameters
+echo "-cdslib ../bin/cds.lib" > ../run/ncvlog.args
+echo "-hdlvar ../bin/hdl.var" >> ../run/ncvlog.args
+echo "-logfile ../log/ncvlog.log" >> ../run/ncvlog.args
+echo "-update" >> ../run/ncvlog.args
+echo "-messages" >> ../run/ncvlog.args
+echo "-INCDIR ../../../bench/verilog" >> ../run/ncvlog.args
+echo "-INCDIR ../../../rtl/verilog" >> ../run/ncvlog.args
+echo "-DEFINE SIM" >> ../run/ncvlog.args
+# adding defines to .args file
+if ($arg_regression == 1) then
+ cat ../run/defines.args >> ../run/ncvlog.args
+endif
+# adding RTL and Sim files to .args file
+cat ../bin/rtl_file_list.lst >> ../run/ncvlog.args
+cat ../bin/sim_file_list.lst >> ../run/ncvlog.args
+# adding device dependent files to .args file
+cat ../bin/xilinx_file_list.lst >> ../run/ncvlog.args
+
+ncvlog -file ../run/ncvlog.args# > /dev/null;
+echo ""
+
+
+# Run the NC-Verilog elaborator (build the design hierarchy)
+echo ""
+echo "\t@@@"
+echo "\t@@@ Building design hierarchy (elaboration)"
+echo "\t@@@"
+ncelab -file ../bin/ncelab_xilinx.args# > /dev/null;
+echo ""
+
+
+# Run the NC-Verilog simulator (simulate the design)
+echo ""
+echo "\t###"
+echo "\t### Running tests (this takes a long time!)"
+echo "\t###"
+
+# creating ncsim.args file for ncsim and adding main parameters
+echo "-cdslib ../bin/cds.lib" > ../run/ncsim.args
+echo "-hdlvar ../bin/hdl.var" >> ../run/ncsim.args
+echo "-logfile ../log/ncsim.log" >> ../run/ncsim.args
+echo "-messages" >> ../run/ncsim.args
+if ($arg_waves == 1) then
+ echo "-input ../bin/ncsim_waves.rc" >> ../run/ncsim.args
+else
+ echo "-input ../bin/ncsim.rc" >> ../run/ncsim.args
+endif
+echo "worklib.ethernet:fun" >> ../run/ncsim.args
+
+ncsim -file ../run/ncsim.args# > /dev/null
+if ($status != 0) then
+ echo ""
+ echo "TESTS couldn't start due to Errors!"
+ echo ""
+ exit
+else
+ if ($arg_regression == 1) then
+ if ($arg_waves == 1) then
+ mv ../out/waves.shm ../out/i${iter}_waves.shm
+ endif
+ # For ATS - counting all 'FAILED' words
+ set FAIL_COUNT = `grep -c "FAILED" ../log/eth_tb.log`
+ if ($FAIL_COUNT != 0) then
+ # Test didn't pass!!!
+ @ ok = 0;
+ endif
+ # Move 'log' files
+ mv ../log/eth_tb.log ../log/i${iter}_eth_tb.log
+ mv ../log/eth_tb_phy.log ../log/i${iter}_eth_tb_phy.log
+ mv ../log/eth_tb_memory.log ../log/i${iter}_eth_tb_memory.log
+ mv ../log/eth_tb_host.log ../log/i${iter}_eth_tb_host.log
+ mv ../log/eth_tb_wb_s_mon.log ../log/i${iter}_eth_tb_wb_s_mon.log
+ mv ../log/eth_tb_wb_m_mon.log ../log/i${iter}_eth_tb_wb_m_mon.log
+ endif
+endif
+echo ""
+
+@ iter += 1;
+
+if (($arg_regression == 1) && ($iter <= $all_iterations)) then
+ goto iteration
+else
+# rm ./defines.args
+ echo ""
+ echo "<<<"
+ echo "<<< End of VERIFICATION"
+ echo "<<<"
+ echo "<<<"
+ echo "<<< -------------------------------------------------"
+ echo "<<<"
+ # For ATS - displaying 'OK' when tests pass successfuly
+ echo " "
+ echo "Simulation finished:"
+ if ($ok == 1) then
+ echo "OK"
+ else
+ echo "FAILED"
+ endif
+endif
+
run/run_eth_sim_regr.scr
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: run/clean
===================================================================
--- run/clean (nonexistent)
+++ run/clean (revision 338)
@@ -0,0 +1,4 @@
+rm ../bin/INCA_libs/worklib/*
+rm ../bin/INCA_libs/worklib/.*
+rm ../log/*.log
+rm -rf ../out/*.shm
run/clean
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: run/top_groups.do
===================================================================
--- run/top_groups.do (nonexistent)
+++ run/top_groups.do (revision 338)
@@ -0,0 +1,292 @@
+// Signalscan Version 6.7p1
+
+
+define noactivityindicator
+define analog waveform lines
+define add variable default overlay off
+define waveform window analogheight 1
+define terminal automatic
+define buttons control \
+ 1 opensimmulationfile \
+ 2 executedofile \
+ 3 designbrowser \
+ 4 waveform \
+ 5 source \
+ 6 breakpoints \
+ 7 definesourcessearchpath \
+ 8 exit \
+ 9 createbreakpoint \
+ 10 creategroup \
+ 11 createmarker \
+ 12 closesimmulationfile \
+ 13 renamesimmulationfile \
+ 14 replacesimulationfiledata \
+ 15 listopensimmulationfiles \
+ 16 savedofile
+define buttons waveform \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 zoomin \
+ 7 zoomout \
+ 8 zoomoutfull \
+ 9 expand \
+ 10 createmarker \
+ 11 designbrowser:1 \
+ 12 variableradixbinary \
+ 13 variableradixoctal \
+ 14 variableradixdecimal \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define buttons designbrowser \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 cdupscope \
+ 7 getallvariables \
+ 8 getdeepallvariables \
+ 9 addvariables \
+ 10 addvarsandclosewindow \
+ 11 closewindow \
+ 12 scopefiltermodule \
+ 13 scopefiltertask \
+ 14 scopefilterfunction \
+ 15 scopefilterblock \
+ 16 scopefilterprimitive
+define buttons event \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 move \
+ 7 closewindow \
+ 8 duplicate \
+ 9 defineasrisingedge \
+ 10 defineasfallingedge \
+ 11 defineasanyedge \
+ 12 variableradixbinary \
+ 13 variableradixoctal \
+ 14 variableradixdecimal \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define buttons source \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 createbreakpoint \
+ 7 creategroup \
+ 8 createmarker \
+ 9 createevent \
+ 10 createregisterpage \
+ 11 closewindow \
+ 12 opensimmulationfile \
+ 13 closesimmulationfile \
+ 14 renamesimmulationfile \
+ 15 replacesimulationfiledata \
+ 16 listopensimmulationfiles
+define buttons register \
+ 1 undo \
+ 2 cut \
+ 3 copy \
+ 4 paste \
+ 5 delete \
+ 6 createregisterpage \
+ 7 closewindow \
+ 8 continuefor \
+ 9 continueuntil \
+ 10 continueforever \
+ 11 stop \
+ 12 previous \
+ 13 next \
+ 14 variableradixbinary \
+ 15 variableradixhexadecimal \
+ 16 variableradixascii
+define show related transactions
+define exit prompt
+define event search direction forward
+define variable nofullhierarchy
+define variable nofilenames
+define variable nofullpathfilenames
+include bookmark with filenames
+include scope history without filenames
+define waveform window listpane 4.96
+define waveform window namepane 15.18
+define multivalueindication
+define pattern curpos dot
+define pattern cursor1 dot
+define pattern cursor2 dot
+define pattern marker dot
+define print designer "Miha Dolenc"
+define print border
+define print color blackonwhite
+define print command "/usr/ucb/lpr -P%P"
+define print printer lp
+define print range visible
+define print variable visible
+define rise fall time low threshold percentage 10
+define rise fall time high threshold percentage 90
+define rise fall time low value 0
+define rise fall time high value 3.3
+define sendmail command "/usr/lib/sendmail"
+define sequence time width 30.00
+define snap
+
+define source noprompt
+define time units default
+define userdefinedbussymbol
+define user guide directory "/usr/local/designacc/signalscan-6.7p1/doc/html"
+define waveform window grid off
+define waveform window waveheight 14
+define waveform window wavespace 6
+define web browser command netscape
+define zoom outfull on initial add off
+add group \
+ A \
+
+add group \
+ "WISHBONE common" \
+ tb_ethernet.eth_top.wb_clk_i \
+ tb_ethernet.eth_top.wb_rst_i \
+ tb_ethernet.eth_top.wb_dat_i[31:0]'h \
+ tb_ethernet.eth_top.wb_dat_o[31:0]'h \
+ tb_ethernet.eth_top.wb_err_o \
+
+add group \
+ "WISHBONE slave signals" \
+ tb_ethernet.eth_top.wb_adr_i[11:2]'h \
+ tb_ethernet.eth_top.wb_sel_i[3:0]'h \
+ tb_ethernet.eth_top.wb_we_i \
+ tb_ethernet.eth_top.wb_cyc_i \
+ tb_ethernet.eth_top.wb_stb_i \
+ tb_ethernet.eth_top.wb_ack_o \
+
+add group \
+ "WISHBONE master signals" \
+ tb_ethernet.eth_top.m_wb_adr_o[31:0]'h \
+ tb_ethernet.eth_top.m_wb_sel_o[3:0]'h \
+ tb_ethernet.eth_top.m_wb_we_o \
+ tb_ethernet.eth_top.m_wb_dat_i[31:0]'h \
+ tb_ethernet.eth_top.m_wb_dat_o[31:0]'h \
+ tb_ethernet.eth_top.m_wb_cyc_o \
+ tb_ethernet.eth_top.m_wb_stb_o \
+ tb_ethernet.eth_top.m_wb_ack_i \
+ tb_ethernet.eth_top.m_wb_err_i \
+
+add group \
+ "MAC common" \
+ tb_ethernet.eth_top.mcoll_pad_i \
+ tb_ethernet.eth_top.mcrs_pad_i \
+
+add group \
+ "MAC TX" \
+ tb_ethernet.eth_top.mtx_clk_pad_i \
+ tb_ethernet.eth_top.mtxd_pad_o[3:0]'h \
+ tb_ethernet.eth_top.mtxen_pad_o \
+ tb_ethernet.eth_top.mtxerr_pad_o \
+
+add group \
+ "MAC RX" \
+ tb_ethernet.eth_top.mrx_clk_pad_i \
+ tb_ethernet.eth_top.mrxd_pad_i[3:0]'h \
+ tb_ethernet.eth_top.mrxdv_pad_i \
+ tb_ethernet.eth_top.mrxerr_pad_i \
+
+add group \
+ "MAC MIIM interface" \
+ tb_ethernet.eth_top.mdc_pad_o \
+ tb_ethernet.eth_top.md_padoe_o \
+ tb_ethernet.eth_top.md_pad_o \
+ tb_ethernet.eth_top.md_pad_i \
+ tb_ethernet.eth_top.miim1.Busy \
+ tb_ethernet.eth_top.miim1.LinkFail \
+ tb_ethernet.eth_top.miim1.Nvalid \
+ tb_ethernet.eth_top.miim1.CtrlData[15:0]'h \
+ tb_ethernet.eth_top.miim1.UpdateMIIRX_DATAReg \
+ tb_ethernet.eth_top.miim1.Prsd[15:0]'h \
+ tb_ethernet.eth_top.miim1.Divider[7:0]'h \
+
+add group \
+ "Test signals" \
+ tb_ethernet.test_name[799:0]'a \
+ tb_ethernet.eth_top.ethreg1.MIISTATUSOut[31:0]'h \
+ tb_ethernet.eth_top.miim1.InProgress \
+ tb_ethernet.eth_top.miim1.InProgress_q1 \
+ tb_ethernet.eth_top.miim1.InProgress_q2 \
+ tb_ethernet.eth_top.miim1.InProgress_q3 \
+ tb_ethernet.eth_top.miim1.shftrg.ShiftReg[7:0]'h \
+ tb_ethernet.eth_phy.status_bit6_0[6:0]'h \
+ tb_ethernet.eth_phy.control_bit8_0[8:0]'h \
+ tb_ethernet.eth_phy.control_bit9 \
+ tb_ethernet.eth_phy.control_bit14_10[14:10]'h \
+ tb_ethernet.eth_phy.control_bit15 \
+ tb_ethernet.eth_phy.eth_speed \
+ tb_ethernet.eth_phy.m_rst_n_i \
+ tb_ethernet.eth_phy.mcoll_o \
+ tb_ethernet.eth_phy.mcrs_o \
+ tb_ethernet.eth_phy.md_get_phy_address \
+ tb_ethernet.eth_phy.md_get_reg_address \
+ tb_ethernet.eth_phy.md_get_reg_data_in \
+ tb_ethernet.eth_phy.md_put_reg_data_in \
+ tb_ethernet.eth_phy.md_put_reg_data_out \
+ tb_ethernet.eth_phy.reg_data_in[15:0]'h \
+ tb_ethernet.eth_phy.reg_data_out[15:0]'h \
+ tb_ethernet.eth_phy.register_bus_in[15:0]'h \
+ tb_ethernet.eth_phy.register_bus_out[15:0]'h \
+ tb_ethernet.eth_phy.reg_address[4:0]'h \
+ tb_ethernet.eth_phy.md_io_output \
+ tb_ethernet.eth_phy.md_io_enable \
+ tb_ethernet.eth_phy.md_io \
+ tb_ethernet.Mdc_O \
+ tb_ethernet.Mdi_I \
+ tb_ethernet.Mdio_IO \
+ tb_ethernet.Mdo_O \
+ tb_ethernet.Mdo_OE \
+ tb_ethernet.eth_phy.md_io_enable \
+ tb_ethernet.eth_phy.md_io_output \
+ tb_ethernet.eth_phy.md_io_rd_wr \
+ tb_ethernet.eth_phy.md_io_reg \
+ tb_ethernet.eth_phy.m_rst_n_i \
+ tb_ethernet.eth_phy.md_transfer_cnt'd \
+ tb_ethernet.eth_phy.md_transfer_cnt_reset \
+ tb_ethernet.eth_phy.mdc_i \
+ tb_ethernet.eth_phy.mrx_clk_o \
+ tb_ethernet.eth_phy.mrxd_o[3:0]'h \
+ tb_ethernet.eth_phy.mrxdv_o \
+ tb_ethernet.eth_phy.mrxerr_o \
+ tb_ethernet.eth_phy.mtx_clk_o \
+ tb_ethernet.eth_phy.mtxd_i[3:0]'h \
+ tb_ethernet.eth_phy.mtxen_i \
+ tb_ethernet.eth_phy.mtxerr_i \
+ tb_ethernet.eth_phy.phy_address[4:0]'h \
+ tb_ethernet.eth_phy.phy_id1[15:0]'h \
+ tb_ethernet.eth_phy.phy_id2[15:0]'h \
+ tb_ethernet.eth_phy.phy_log[31:0]'h \
+ tb_ethernet.eth_phy.reg_address[4:0]'h \
+ tb_ethernet.eth_phy.register_bus_in[15:0]'h \
+ tb_ethernet.eth_phy.register_bus_out[15:0]'h \
+ tb_ethernet.eth_phy.registers_addr_data_test_operation \
+ tb_ethernet.eth_phy.rx_link_down_halfperiod \
+ ( \
+ minmax 0 93 \
+ ) \
+ tb_ethernet.eth_phy.self_clear_d0 \
+ tb_ethernet.eth_phy.self_clear_d1 \
+ tb_ethernet.eth_phy.self_clear_d2 \
+ tb_ethernet.eth_phy.self_clear_d3 \
+ tb_ethernet.eth_phy.status_bit6_0[6:0]'h \
+ tb_ethernet.eth_phy.status_bit7 \
+ tb_ethernet.eth_phy.status_bit8 \
+ tb_ethernet.eth_phy.status_bit15_9[15:9]'h \
+
+
+deselect all
+open window designbrowser 1 geometry 56 117 855 550
+open window waveform 1 geometry 10 59 1592 1094
+zoom at 4981823.979(0)ns 0.00025639 0.00000000
run/top_groups.do
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: log/dir_keeper
===================================================================
Index: out/dir_keeper
===================================================================
Index: modelsim_sim/run/tb_eth.do
===================================================================
--- modelsim_sim/run/tb_eth.do (nonexistent)
+++ modelsim_sim/run/tb_eth.do (revision 338)
@@ -0,0 +1,125 @@
+#/////////////////////////////////////////////////////////////////////
+#/// ////
+#/// tb_eth.do ////
+#/// ////
+#/// This file is part of the Ethernet IP core project ////
+#/// http://www.opencores.org/projects/ethmac/ ////
+#/// ////
+#/// Author(s): ////
+#/// - Igor Mohor (igorM@opencores.org) ////
+#/// ////
+#/// All additional information is avaliable in the Readme.txt ////
+#/// file. ////
+#/// ////
+#/////////////////////////////////////////////////////////////////////
+#/// ////
+#/// Copyright (C) 2001, 2002 Authors ////
+#/// ////
+#/// This source file may be used and distributed without ////
+#/// restriction provided that this copyright statement is not ////
+#/// removed from the file and that any derivative work contains ////
+#/// the original copyright notice and the associated disclaimer. ////
+#/// ////
+#/// This source file is free software; you can redistribute it ////
+#/// and/or modify it under the terms of the GNU Lesser General ////
+#/// Public License as published by the Free Software Foundation; ////
+#/// either version 2.1 of the License, or (at your option) any ////
+#/// later version. ////
+#/// ////
+#/// This source is distributed in the hope that it will be ////
+#/// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+#/// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+#/// PURPOSE. See the GNU Lesser General Public License for more ////
+#/// details. ////
+#/// ////
+#/// You should have received a copy of the GNU Lesser General ////
+#/// Public License along with this source; if not, download it ////
+#/// from http://www.opencores.org/lgpl.shtml ////
+#/// ////
+#/////////////////////////////////////////////////////////////////////
+#/
+#/ CVS Revision History
+#/
+#/ $Log: not supported by cvs2svn $
+#/ Revision 1.4 2002/10/11 13:33:56 mohor
+#/ Bist supported.
+#/
+#/ Revision 1.3 2002/10/11 12:42:12 mohor
+#/ Bist supported.
+#/
+#/ Revision 1.2 2002/09/23 18:27:36 mohor
+#/ ETH_VIRTUAL_SILICON_RAM supported.
+#/
+#/ Revision 1.1 2002/09/17 19:10:17 mohor
+#/ Macro for testbench (DO file).
+#/
+#/
+#/
+#/
+
+
+#write format wave -window .wave C:/Projects/ethernet/tadejm/ethernet/sim/rtl_sim/modelsim_sim/bin/wave.do
+#.main clear
+
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_clockgen.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_crc.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_defines.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_fifo.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_maccontrol.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_macstatus.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_miim.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_outputcontrol.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_random.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_receivecontrol.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_register.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_registers.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxaddrcheck.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxcounters.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxethmac.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_rxstatem.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_shiftreg.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_spram_256x32.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_top.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_transmitcontrol.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_txcounters.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_txethmac.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_txstatem.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/eth_wishbone.v}
+vlog -reportprogress 300 -work work {../../../../rtl/verilog/timescale.v}
+vlog -reportprogress 300 -work work {../../../../bench/verilog/eth_phy.v}
+vlog -reportprogress 300 -work work {../../../../bench/verilog/eth_phy_defines.v}
+vlog -reportprogress 300 -work work {../../../../bench/verilog/tb_eth_defines.v}
+vlog -reportprogress 300 -work work {../../../../bench/verilog/tb_ethernet.v}
+vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_bus_mon.v}
+vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_master_behavioral.v}
+vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_master32.v}
+vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_model_defines.v}
+vlog -reportprogress 300 -work work {../../../../bench/verilog/wb_slave_behavioral.v}
+
+
+# If you use define ETH_XILINX_RAMB4 switched on, then uncomment the following lines
+# vlog -reportprogress 300 -work work {C:/Xilinx/verilog/src/glbl.v}
+# vlog -reportprogress 300 -work work {C:/Xilinx/verilog/src/unisims/RAMB4_S16.v}
+
+# If you use define ETH_VIRTUAL_SILICON_RAM switched on, then uncomment the following lines
+# vlog -reportprogress 300 -work work {../../../../../vs_rams/018/vs_hdsp_256x32.v}
+
+# If you use define ETH_VIRTUAL_SILICON_RAM and ETH_BIST switched on, then uncomment
+# the following lines
+# vlog -reportprogress 300 -work work {../../../../../vs_rams/018/vs_hdsp_256x32_bist.v}
+# vlog -reportprogress 300 -work work {../../../../../vs_rams/018/vs_hdsp_256x32_bist_int.v}
+# vlog -reportprogress 300 -work work {../../../../../jtag_marvin/jt_bc1in.v}
+# vlog -reportprogress 300 -work work {../../../../../bist_marvin/bist.v}
+
+# If you use define ETH_XILINX_RAMB4 switched on, then uncomment the following lines
+# !ETH_XILINX_RAMB4
+ vsim work.tb_ethernet
+# ETH_XILINX_RAMB4
+ #vsim work.glbl work.tb_ethernet
+
+
+do ../bin/eth_wave.do
+#do ../bin/wave.do
+run -all
+
+
Index: modelsim_sim/run/dir.keeper
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: modelsim_sim/run/dir.keeper
===================================================================
--- modelsim_sim/run/dir.keeper (nonexistent)
+++ modelsim_sim/run/dir.keeper (revision 338)
modelsim_sim/run/dir.keeper
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: modelsim_sim/bin/eth_wave.do
===================================================================
--- modelsim_sim/bin/eth_wave.do (nonexistent)
+++ modelsim_sim/bin/eth_wave.do (revision 338)
@@ -0,0 +1,138 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wb_clk
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wb_rst
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wb_int
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/mtx_clk
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/mrx_clk
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MTxD
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MTxEn
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MTxErr
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MRxD
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MRxDV
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MRxErr
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MColl
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/MCrs
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/Mdi_I
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/Mdo_O
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/Mdo_OE
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/Mdio_IO
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/Mdc_O
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_adr
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_adr_i
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_dat_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_dat_i
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_sel_i
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_we_i
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_cyc_i
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_stb_i
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_ack_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_sl_wb_err_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_adr_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_dat_i
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_dat_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_sel_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_we_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_cyc_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_stb_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_ack_i
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_ma_wb_err_i
+add wave -noupdate -format Logic -radix ascii /tb_ethernet/test_name
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wbm_init_waits
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wbm_subseq_waits
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wbs_waits
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wbs_retries
+
+add wave -noupdate -format Logic -radix hex /tb_ethernet/eth_top/wishbone/*
+add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_receive/i_length
+add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_receive/num_of_bd
+add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_transmit/max_tmp
+add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_transmit/min_tmp
+add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_transmit/i_length
+add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_transmit/num_of_frames
+add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_transmit/num_of_bd
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wb_slave/calc_ack
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/wb_slave/a_e_r_resp
+add wave -noupdate -format Logic -radix decimal /tb_ethernet/test_mac_full_duplex_transmit/frame_ended
+
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/m_rst_n_i
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mtx_clk_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mtxd_i
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mtxen_i
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mtxerr_i
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mrx_clk_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mrxd_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mrxdv_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mrxerr_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mcoll_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mcrs_o
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mdc_i
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_io
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/phy_log
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/control_bit15
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/control_bit14_10
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/control_bit9
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/control_bit8_0
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/status_bit15_9
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/status_bit8
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/status_bit7
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/status_bit6_0
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/phy_id1
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/phy_id2
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/rx_link_down_halfperiod
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/eth_speed
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/respond_to_all_phy_addr
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/no_preamble
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_transfer_cnt
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_transfer_cnt_reset
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_io_reg
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_io_output
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_io_rd_wr
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_io_enable
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/phy_address
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/reg_address
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_get_phy_address
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_get_reg_address
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/reg_data_in
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_get_reg_data_in
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_put_reg_data_in
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/reg_data_out
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/md_put_reg_data_out
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/register_bus_in
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/register_bus_out
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/registers_addr_data_test_operation
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/self_clear_d0
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/self_clear_d1
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/self_clear_d2
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/self_clear_d3
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mcrs_rx
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mcrs_tx
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/mtxen_d
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/task_mcoll
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/task_mcrs
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/task_mcrs_lost
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/no_collision_in_half_duplex
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/collision_in_full_duplex
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/no_carrier_sense_in_tx_half_duplex
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/no_carrier_sense_in_rx_half_duplex
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/carrier_sense_in_tx_full_duplex
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/no_carrier_sense_in_rx_full_duplex
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/real_carrier_sense
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/tx_mem_addr_in
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/tx_mem_data_in
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/tx_cnt
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/tx_preamble_ok
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/tx_sfd_ok
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/tx_byte_aligned_ok
+add wave -noupdate -format Logic -radix hexadecimal /tb_ethernet/eth_phy/tx_len
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {476613 ns}
+WaveRestoreZoom {476105 ns} {478586 ns}
+configure wave -namecolwidth 280
+configure wave -valuecolwidth 68
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
Index: modelsim_sim/bin/work/_info
===================================================================
--- modelsim_sim/bin/work/_info (nonexistent)
+++ modelsim_sim/bin/work/_info (revision 338)
@@ -0,0 +1,4 @@
+m255
+o
+cModel Technology
+dC:\Modeltech_5.6a\examples
Index: modelsim_sim/bin/work/dir.keeper
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: modelsim_sim/bin/work/dir.keeper
===================================================================
--- modelsim_sim/bin/work/dir.keeper (nonexistent)
+++ modelsim_sim/bin/work/dir.keeper (revision 338)
modelsim_sim/bin/work/dir.keeper
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: modelsim_sim/bin/ethernet.mpf
===================================================================
--- modelsim_sim/bin/ethernet.mpf (nonexistent)
+++ modelsim_sim/bin/ethernet.mpf (revision 338)
@@ -0,0 +1,406 @@
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+
+work = work
+[vcom]
+; Turn on VHDL-1993 as the default. Default is off (VHDL-1987).
+; VHDL93 = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explict enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = false
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+VHDL93 = 0
+NoDebug = 0
+CheckSynthesis = 0
+NoVitalCheck = 0
+Optimize_1164 = 1
+NoVital = 0
+Quiet = 0
+Show_source = 0
+Show_Warning1 = 1
+Show_Warning2 = 1
+Show_Warning3 = 1
+Show_Warning4 = 1
+Show_Warning5 = 1
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+Quiet = 0
+Show_source = 0
+NoDebug = 0
+Hazard = 0
+UpCase = 0
+OptionFile = ../../../../sim/rtl_sim/modelsim_sim/bin/vlog.opt
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+resolution = 1ns
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+UserTimeUnit = ns
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Stop the simulator after an assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format. For VHDL, PathSeparator = /
+; for Verilog, PathSeparator = .
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, or deposit
+; or in other terms, fixed, wired, or charged.
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control number of VHDL files open concurrently
+; This number should always be less than the
+; current ulimit setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Controls the number of hierarchical regions displayed as
+; part of a signal name shown in the waveform window. The default
+; value or a value of zero tells VSIM to display the full name.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of a generate statement label. Do not quote it.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is to be compressed.
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1; compress WLF file.
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in WLF file
+; or only regions containing logged signals (0).
+; The default is 0; log only regions with logged signals.
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0; no limit. Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0; no limit.
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0; do not delete WLF file when simulation ends.
+; WLFDeleteOnQuit = 1
+
+[lmc]
+; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+
+; ModelSim's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = /lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = /lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = /lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = /lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = /lib/linux/libsfi.so
+[Project]
+Project_Version = 3
+Project_DefaultLib = work
+Project_SortMethod = alpha
+Project_Files_Count = 34
+Project_File_0 = ../../../../rtl/verilog/eth_registers.v
+Project_File_P_0 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031654124 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 12 dont_compile 0
+Project_File_1 = ../../../../rtl/verilog/eth_crc.v
+Project_File_P_1 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 2 dont_compile 0
+Project_File_2 = ../../../../rtl/verilog/eth_random.v
+Project_File_P_2 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 9 dont_compile 0
+Project_File_3 = ../../../../bench/verilog/wb_bus_mon.v
+Project_File_P_3 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 30 dont_compile 0
+Project_File_4 = ../../../../bench/verilog/tb_ethernet.v
+Project_File_P_4 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1032198830 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 29 dont_compile 0
+Project_File_5 = ../../../../rtl/verilog/eth_outputcontrol.v
+Project_File_P_5 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1026245520 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 8 dont_compile 0
+Project_File_6 = ../../../../rtl/verilog/eth_transmitcontrol.v
+Project_File_P_6 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 20 dont_compile 0
+Project_File_7 = ../../../../rtl/verilog/eth_top.v
+Project_File_P_7 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031842218 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 19 dont_compile 0
+Project_File_8 = ../../../../rtl/verilog/eth_rxaddrcheck.v
+Project_File_P_8 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031164866 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 13 dont_compile 0
+Project_File_9 = ../../../../bench/verilog/wb_model_defines.v
+Project_File_P_9 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 33 dont_compile 0
+Project_File_10 = ../../../../rtl/verilog/eth_receivecontrol.v
+Project_File_P_10 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 10 dont_compile 0
+Project_File_11 = ../../../../rtl/verilog/eth_rxethmac.v
+Project_File_P_11 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1013843728 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 15 dont_compile 0
+Project_File_12 = ../../../../bench/verilog/eth_phy_defines.v
+Project_File_P_12 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 27 dont_compile 0
+Project_File_13 = ../../../../rtl/verilog/eth_miim.v
+Project_File_P_13 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029349930 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 7 dont_compile 0
+Project_File_14 = ../../../../rtl/verilog/eth_rxcounters.v
+Project_File_P_14 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1013771610 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 14 dont_compile 0
+Project_File_15 = ../../../../rtl/verilog/eth_register.v
+Project_File_P_15 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029535812 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 11 dont_compile 0
+Project_File_16 = ../../../../bench/verilog/wb_slave_behavioral.v
+Project_File_P_16 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 34 dont_compile 0
+Project_File_17 = ../../../../bench/verilog/wb_master_behavioral.v
+Project_File_P_17 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 31 dont_compile 0
+Project_File_18 = ../../../../rtl/verilog/eth_txethmac.v
+Project_File_P_18 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1014740642 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 22 dont_compile 0
+Project_File_19 = ../../../../rtl/verilog/eth_wishbone.v
+Project_File_P_19 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031753926 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 24 dont_compile 0
+Project_File_20 = ../../../../rtl/verilog/eth_txcounters.v
+Project_File_P_20 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1019487254 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 21 dont_compile 0
+Project_File_21 = ../../../../bench/verilog/eth_phy.v
+Project_File_P_21 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031928616 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 26 dont_compile 0
+Project_File_22 = ../../../../bench/verilog/wb_master32.v
+Project_File_P_22 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031920154 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 32 dont_compile 0
+Project_File_23 = ../../../../rtl/verilog/eth_rxstatem.v
+Project_File_P_23 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 16 dont_compile 0
+Project_File_24 = ../../../../bench/verilog/tb_eth_defines.v
+Project_File_P_24 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031942506 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 28 dont_compile 0
+Project_File_25 = ../../../../rtl/verilog/eth_maccontrol.v
+Project_File_P_25 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 5 dont_compile 0
+Project_File_26 = ../../../../rtl/verilog/eth_txstatem.v
+Project_File_P_26 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 23 dont_compile 0
+Project_File_27 = ../../../../rtl/verilog/eth_shiftreg.v
+Project_File_P_27 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1029349020 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 17 dont_compile 0
+Project_File_28 = ../../../../rtl/verilog/eth_spram_256x32.v
+Project_File_P_28 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1027442170 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 18 dont_compile 0
+Project_File_29 = ../../../../rtl/verilog/eth_fifo.v
+Project_File_P_29 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1019483152 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 4 dont_compile 0
+Project_File_30 = ../../../../rtl/verilog/eth_macstatus.v
+Project_File_P_30 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031842216 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 6 dont_compile 0
+Project_File_31 = ../../../../rtl/verilog/eth_defines.v
+Project_File_P_31 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1031164610 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 3 dont_compile 0
+Project_File_32 = ../../../../rtl/verilog/eth_clockgen.v
+Project_File_P_32 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 0 dont_compile 0
+Project_File_33 = ../../../../rtl/verilog/timescale.v
+Project_File_P_33 = file_type Verilog group_id 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 1011781696 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_options {} vlog_upper 0 compile_to work compile_order 25 dont_compile 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
Index: modelsim_sim/bin/do.do
===================================================================
--- modelsim_sim/bin/do.do (nonexistent)
+++ modelsim_sim/bin/do.do (revision 338)
@@ -0,0 +1,48 @@
+#/////////////////////////////////////////////////////////////////////
+#/// ////
+#/// do.do ////
+#/// ////
+#/// This file is part of the Ethernet IP core project ////
+#/// http://www.opencores.org/projects/ethmac/ ////
+#/// ////
+#/// Author(s): ////
+#/// - Igor Mohor (igorM@opencores.org) ////
+#/// ////
+#/// All additional information is avaliable in the Readme.txt ////
+#/// file. ////
+#/// ////
+#/////////////////////////////////////////////////////////////////////
+#/// ////
+#/// Copyright (C) 2001, 2002 Authors ////
+#/// ////
+#/// This source file may be used and distributed without ////
+#/// restriction provided that this copyright statement is not ////
+#/// removed from the file and that any derivative work contains ////
+#/// the original copyright notice and the associated disclaimer. ////
+#/// ////
+#/// This source file is free software; you can redistribute it ////
+#/// and/or modify it under the terms of the GNU Lesser General ////
+#/// Public License as published by the Free Software Foundation; ////
+#/// either version 2.1 of the License, or (at your option) any ////
+#/// later version. ////
+#/// ////
+#/// This source is distributed in the hope that it will be ////
+#/// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+#/// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+#/// PURPOSE. See the GNU Lesser General Public License for more ////
+#/// details. ////
+#/// ////
+#/// You should have received a copy of the GNU Lesser General ////
+#/// Public License along with this source; if not, download it ////
+#/// from http://www.opencores.org/lgpl.shtml ////
+#/// ////
+#/////////////////////////////////////////////////////////////////////
+#/
+#/ CVS Revision History
+#/
+#/ $Log: not supported by cvs2svn $
+#/
+#/
+#/
+
+do ../run/tb_eth.do
Index: modelsim_sim/bin/vlog.opt
===================================================================
--- modelsim_sim/bin/vlog.opt (nonexistent)
+++ modelsim_sim/bin/vlog.opt (revision 338)
@@ -0,0 +1,2 @@
++incdir+../../../../bench/verilog
++incdir+../../../../rtl/verilog
Index: modelsim_sim/log/dir.keeper
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: modelsim_sim/log/dir.keeper
===================================================================
--- modelsim_sim/log/dir.keeper (nonexistent)
+++ modelsim_sim/log/dir.keeper (revision 338)
modelsim_sim/log/dir.keeper
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: modelsim_sim/out/dir.keeper
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: modelsim_sim/out/dir.keeper
===================================================================
--- modelsim_sim/out/dir.keeper (nonexistent)
+++ modelsim_sim/out/dir.keeper (revision 338)
modelsim_sim/out/dir.keeper
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property