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URL https://opencores.org/ocsvn/fade_ether_protocol/fade_ether_protocol/trunk

Subversion Repositories fade_ether_protocol

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    /fade_ether_protocol/trunk
    from Rev 35 to Rev 36
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Rev 35 → Rev 36

/experimental_jumbo_frames_version/fpga/src/AFCK/fade_afck.xdc
19,3 → 19,16
set_property PACKAGE_PIN A8 [get_ports {gtx10g_rxp[1]}]
set_property PACKAGE_PIN E4 [get_ports {gtx10g_rxp[2]}]
set_property PACKAGE_PIN D6 [get_ports {gtx10g_rxp[3]}]
 
set_property PACKAGE_PIN Y20 [get_ports si570_oe]
set_property IOSTANDARD LVCMOS25 [get_ports si570_oe]
 
set_property PACKAGE_PIN H26 [get_ports {gtx_rate_sel[0]}]
set_property PACKAGE_PIN A26 [get_ports {gtx_rate_sel[1]}]
set_property PACKAGE_PIN E29 [get_ports {gtx_rate_sel[2]}]
set_property PACKAGE_PIN F30 [get_ports {gtx_rate_sel[3]}]
 
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[3]}]
/experimental_jumbo_frames_version/fpga/src/AFCK/AFCK_fade_top_4ch.vhd
16,6 → 16,8
gtx_refclk_n : in std_logic;
gtx_refclk_p : in std_logic;
gtx_sfp_disable : out std_logic_vector(3 downto 0);
gtx_rate_sel : out std_logic_vector(3 downto 0);
si570_oe : out std_logic;
clk_2_n : in std_logic;
clk_2_p : in std_logic
);
252,10 → 254,12
end component fade_one_channel;
 
begin -- beh1
si570_oe <= '1';
-- Initialization vector
configuration_vector(33) <= '1'; -- training
configuration_vector(284) <= '1'; -- auto negotiation
 
gtx_rate_sel <= (others => '1');
signal_detect <= (others => '1'); -- allow transmission!
gtx_sfp_disable <= (others => '0');
 
/experimental_jumbo_frames_version/fpga/src/AFCK/fade_afck_fmc1.xdc
0,0 → 1,34
set_property PACKAGE_PIN C8 [get_ports gtx_refclk_p]
set_property IOSTANDARD LVCMOS25 [get_ports clk_2_p]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[0]}]
 
 
set_property PACKAGE_PIN J8 [get_ports clk_2_p]
 
create_clock -period 6.400 -name clk156 -waveform {0.000 3.200} [get_nets *156*]
create_clock -period 6.400 -name gtx_refclk -waveform {0.000 3.200} [get_ports {gtx_refclk_n gtx_refclk_p}]
 
set_property PACKAGE_PIN E19 [get_ports {gtx_sfp_disable[0]}]
set_property PACKAGE_PIN A23 [get_ports {gtx_sfp_disable[1]}]
set_property PACKAGE_PIN F28 [get_ports {gtx_sfp_disable[2]}]
set_property PACKAGE_PIN C29 [get_ports {gtx_sfp_disable[3]}]
set_property PACKAGE_PIN B6 [get_ports {gtx10g_rxp[0]}]
set_property PACKAGE_PIN A8 [get_ports {gtx10g_rxp[1]}]
set_property PACKAGE_PIN E4 [get_ports {gtx10g_rxp[2]}]
set_property PACKAGE_PIN D6 [get_ports {gtx10g_rxp[3]}]
 
set_property PACKAGE_PIN Y20 [get_ports si570_oe]
set_property IOSTANDARD LVCMOS25 [get_ports si570_oe]
 
set_property PACKAGE_PIN H26 [get_ports {gtx_rate_sel[0]}]
set_property PACKAGE_PIN A26 [get_ports {gtx_rate_sel[1]}]
set_property PACKAGE_PIN E29 [get_ports {gtx_rate_sel[2]}]
set_property PACKAGE_PIN F30 [get_ports {gtx_rate_sel[3]}]
 
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[3]}]
/experimental_jumbo_frames_version/fpga/src/AFCK/fade_afck_fmc2.xdc
0,0 → 1,34
set_property PACKAGE_PIN J8 [get_ports gtx_refclk_p]
set_property IOSTANDARD LVCMOS25 [get_ports clk_2_p]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[0]}]
 
 
set_property PACKAGE_PIN C8 [get_ports clk_2_p]
 
create_clock -period 6.400 -name clk156 -waveform {0.000 3.200} [get_nets *156*]
create_clock -period 6.400 -name gtx_refclk -waveform {0.000 3.200} [get_ports {gtx_refclk_n gtx_refclk_p}]
 
set_property PACKAGE_PIN T25 [get_ports {gtx_sfp_disable[0]}]
set_property PACKAGE_PIN AA28 [get_ports {gtx_sfp_disable[1]}]
set_property PACKAGE_PIN Y30 [get_ports {gtx_sfp_disable[2]}]
set_property PACKAGE_PIN AK28 [get_ports {gtx_sfp_disable[3]}]
set_property PACKAGE_PIN F6 [get_ports {gtx10g_rxp[0]}]
set_property PACKAGE_PIN G4 [get_ports {gtx10g_rxp[1]}]
set_property PACKAGE_PIN H6 [get_ports {gtx10g_rxp[2]}]
set_property PACKAGE_PIN K6 [get_ports {gtx10g_rxp[3]}]
 
set_property PACKAGE_PIN Y20 [get_ports si570_oe]
set_property IOSTANDARD LVCMOS25 [get_ports si570_oe]
 
set_property PACKAGE_PIN AE30 [get_ports {gtx_rate_sel[0]}]
set_property PACKAGE_PIN W28 [get_ports {gtx_rate_sel[1]}]
set_property PACKAGE_PIN AG27 [get_ports {gtx_rate_sel[2]}]
set_property PACKAGE_PIN AB30 [get_ports {gtx_rate_sel[3]}]
 
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[3]}]

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