Subversion Repositories fade_ether_protocol

/trunk/experimental_jumbo_frames_version/fpga/build_proj_afck_8ch

trunk/experimental_jumbo_frames_version/fpga/build_proj_afck_8ch Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/experimental_jumbo_frames_version/fpga/fade_afck_8ch.tcl =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/fade_afck_8ch.tcl (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/fade_afck_8ch.tcl (revision 37) @@ -0,0 +1,303 @@ +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Create project +create_project afck_10g3_8ch ./afck_10g3_8ch + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [get_projects afck_10g3_8ch] +set_property "board_part" "xilinx.com:kc705:part0:0.9" $obj +set_property "default_lib" "xil_defaultlib" $obj +set_property "simulator_language" "Mixed" $obj +set_property "target_language" "VHDL" $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + "[file normalize "$origin_dir/src/pkt_ack_pkg.vhd"]"\ + "[file normalize "$origin_dir/src/pkt_desc_pkg.vhd"]"\ + "[file normalize "$origin_dir/src/pkg_newcrc32_d64.vhd"]"\ + "[file normalize "$origin_dir/src/pkg_newcrc32_d32.vhd"]"\ + "[file normalize "$origin_dir/src/pkg_newcrc32_d16.vhd"]"\ + "[file normalize "$origin_dir/src/desc_mgr_pkg.vhd"]"\ + "[file normalize "$origin_dir/src/kc705/eth_sender64.vhd"]"\ + "[file normalize "$origin_dir/src/kc705/eth_receiver64.vhd"]"\ + "[file normalize "$origin_dir/src/dpram_inf.vhd"]"\ + "[file normalize "$origin_dir/src/desc_manager_simple.vhd"]"\ + "[file normalize "$origin_dir/src/cmd_proc.vhd"]"\ + "[file normalize "$origin_dir/src/fade_one_channel.vhd"]"\ + "[file normalize "$origin_dir/src/AFCK/i2c/i2c_master_bit_ctrl.vhd"]"\ + "[file normalize "$origin_dir/src/AFCK/i2c/i2c_master_byte_ctrl.vhd"]"\ + "[file normalize "$origin_dir/src/AFCK/i2c/i2c_master_top.vhd"]"\ + "[file normalize "$origin_dir/src/AFCK/i2c/i2c_bus_wrap.vhd"]"\ + "[file normalize "$origin_dir/src/AFCK/i2c/i2c_vio_ctrl_top.vhd"]"\ + "[file normalize "$origin_dir/src/AFCK/frq_counter.vhd"]"\ + "[file normalize "$origin_dir/src/AFCK/AFCK_fade_top_8ch.vhd"]"\ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/src/pkt_ack_pkg.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/pkt_desc_pkg.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/pkg_newcrc32_d64.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/pkg_newcrc32_d32.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/pkg_newcrc32_d16.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/desc_mgr_pkg.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/kc705/eth_sender64.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/kc705/eth_receiver64.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/dpram_inf.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/desc_manager_simple.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/cmd_proc.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/fade_one_channel.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/AFCK/i2c/i2c_master_bit_ctrl.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/AFCK/i2c/i2c_master_byte_ctrl.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/AFCK/i2c/i2c_master_top.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/AFCK/i2c/i2c_bus_wrap.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/AFCK/i2c/i2c_vio_ctrl_top.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/AFCK/frq_counter.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +set file "$origin_dir/src/AFCK/AFCK_fade_top_8ch.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "file_type" "VHDL" $file_obj + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property "top" "afck_10g_2" $obj + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + "[file normalize "$origin_dir/src/AFCK/ack_fifo/ack_fifo.xci"]"\ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/src/AFCK/ack_fifo/ack_fifo.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "synth_checkpoint_mode" "Singular" $file_obj + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + "[file normalize "$origin_dir/src/AFCK/ila_1/ila_1.xci"]"\ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/src/AFCK/ila_1/ila_1.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "synth_checkpoint_mode" "Singular" $file_obj + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + "[file normalize "$origin_dir/src/AFCK/ten_gig_eth_0/ten_gig_eth_pcs_pma_0.xci"]"\ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/src/AFCK/ten_gig_eth_0/ten_gig_eth_pcs_pma_0.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "synth_checkpoint_mode" "Singular" $file_obj + + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + "[file normalize "$origin_dir/src/AFCK/ten_gig_eth_1/ten_gig_eth_pcs_pma_1.xci"]"\ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/src/AFCK/ten_gig_eth_1/ten_gig_eth_pcs_pma_1.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "synth_checkpoint_mode" "Singular" $file_obj + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + "[file normalize "$origin_dir/src/AFCK/vio_0/vio_0.xci"]"\ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/src/AFCK/vio_0/vio_0.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "synth_checkpoint_mode" "Singular" $file_obj + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + "[file normalize "$origin_dir/src/AFCK/vio_frq/vio_frq.xci"]"\ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/src/AFCK/vio_frq/vio_frq.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "synth_checkpoint_mode" "Singular" $file_obj + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + "[file normalize "$origin_dir/src/AFCK/vio_stat/vio_stat.xci"]"\ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/src/AFCK/vio_stat/vio_stat.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property "synth_checkpoint_mode" "Singular" $file_obj + +# Set 'sources_1' fileset file properties for local files +# None + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/src/AFCK/fade_afck_8ch.xdc"]" +set file_added [add_files -norecurse -fileset $obj $file] +set file "$origin_dir/src/AFCK/fade_afck_8ch.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property "file_type" "XDC" $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] +set_property "target_constrs_file" "$origin_dir/src/AFCK/fade_afck_8ch.xdc" $obj + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xc7k325tffg900-2 -flow {Vivado Synthesis 2014} -strategy "Vivado Synthesis Defaults" -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2014" [get_runs synth_1] +} +set obj [get_runs synth_1] + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xc7k325tffg900-2 -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2014" [get_runs impl_1] +} +set obj [get_runs impl_1] + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:afck_10g3_8ch" +launch_runs synth_1 +wait_on_run synth_1 +launch_runs impl_1 +wait_on_run impl_1 +launch_runs impl_1 -to_step write_bitstream + Index: trunk/experimental_jumbo_frames_version/fpga/src/AFCK/AFCK_fade_top_8ch.vhd =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/src/AFCK/AFCK_fade_top_8ch.vhd (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/src/AFCK/AFCK_fade_top_8ch.vhd (revision 37) @@ -0,0 +1,579 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.pkt_ack_pkg.all; +use work.desc_mgr_pkg.all; +library unisim; +use unisim.vcomponents.all; + +entity afck_10g_2 is + + port ( + gtx10g_txn : out std_logic_vector(7 downto 0); + gtx10g_txp : out std_logic_vector(7 downto 0); + gtx10g_rxn : in std_logic_vector(7 downto 0); + gtx10g_rxp : in std_logic_vector(7 downto 0); + gtx_refclk_n : in std_logic_vector(1 downto 0); + gtx_refclk_p : in std_logic_vector(1 downto 0); + gtx_sfp_disable : out std_logic_vector(7 downto 0); + gtx_rate_sel : out std_logic_vector(7 downto 0); + -- Heartbit LED + hb_led : out std_logic_vector(2 downto 0); + -- Pin needed to enable switch matrix + clk_updaten : out std_logic; + si570_oe : out std_logic; + -- I2C interface t control FM-S14 board + scl : inout std_logic; + sda : inout std_logic; + boot_clk : in std_logic + ); + +end afck_10g_2; + +architecture beh1 of afck_10g_2 is + + constant N_OF_LINKS : integer := 4; + constant N_OF_QUADS : integer := 2; + + type T_HB is array (0 to 2) of integer; + signal heart_bit : T_HB := (0, 0, 0); + signal s_hb_led : std_logic_vector(2 downto 0) := "000"; + + signal refclk_p : std_logic_vector(N_OF_QUADS-1 downto 0) := "00"; + signal refclk_n : std_logic_vector(N_OF_QUADS-1 downto 0) := "00"; + signal reset : std_logic := '0'; + signal rst_p : std_logic := '1'; -- generated reset + signal rst_cnt : integer := 20000000; + + type T_FRQ_CNT is array (0 to 1) of std_logic_vector(31 downto 0); + signal frq_user : T_FRQ_CNT := (others => (others => '0')); + signal clk0_frq, clk1_frq : std_logic_vector(31 downto 0) := (others=>'0'); + + signal s_resetdone : std_logic_vector(N_OF_QUADS-1 downto 0) := "00"; + signal core_clk156_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00"; + + + type T_MAC_TABLE is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(47 downto 0); + constant mac_table : T_MAC_TABLE := ( + 0 => x"de_ad_fa_de_00_e2", + 1 => x"de_ad_fa_de_01_e2", + 2 => x"de_ad_fa_de_02_e2", + 3 => x"de_ad_fa_de_03_e2", + 4 => x"de_ad_fa_de_04_e2", + 5 => x"de_ad_fa_de_05_e2", + 6 => x"de_ad_fa_de_06_e2", + 7 => x"de_ad_fa_de_07_e2" + ); + + signal s_txusrclk_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00"; + signal s_txusrclk2_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00"; + signal areset_clk156_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00"; + signal gttxreset_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00"; + signal gtrxreset_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00"; + signal txuserrdy_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00"; + signal reset_counter_done_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00"; + signal qplllock_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00"; + signal qplloutclk_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00"; + signal qplloutrefclk_out : std_logic_vector(N_OF_QUADS-1 downto 0) := "00"; + type T_XGMII_XD is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(63 downto 0); + signal xgmii_txd : T_XGMII_XD := (others => (others => '0')); + type T_XGMII_XC is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(7 downto 0); + signal xgmii_txc : T_XGMII_XC := (others => (others => '0')); + signal xgmii_rxd : T_XGMII_XD := (others => (others => '0')); + signal xgmii_rxc : T_XGMII_XC := (others => (others => '0')); + signal configuration_vector : std_logic_vector(535 downto 0) := (others => '0'); + type T_STATUS_VEC is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(447 downto 0); + signal status_vector : T_STATUS_VEC := (others => (others => '0')); + type T_CORE_STATUS is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(7 downto 0); + signal core_status : T_CORE_STATUS := (others => (others => '0')); + signal signal_detect : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0'); + signal tx_fault : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0'); + signal drp_req : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0'); + signal drp_gnt : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0'); + signal drp_den_o : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0'); + signal drp_dwe_o : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0'); + type T_DRP_V16 is array (0 to N_OF_QUADS*N_OF_LINKS-1) of std_logic_vector(15 downto 0); + signal drp_daddr_o : T_DRP_V16 := (others => (others => '0')); + signal drp_di_o : T_DRP_V16 := (others => (others => '0')); + signal drp_drdy_o : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0'); + signal drp_drpdo_o : T_DRP_V16 := (others => (others => '0')); + signal drp_den_i : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0'); + signal drp_dwe_i : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0'); + + signal drp_daddr_i : T_DRP_V16 := (others => (others => '0')); + signal drp_di_i : T_DRP_V16 := (others => (others => '0')); + signal drp_drdy_i : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0'); + signal drp_drpdo_i : T_DRP_V16 := (others => (others => '0')); + signal tx_disable : std_logic_vector(N_OF_QUADS*N_OF_LINKS-1 downto 0) := (others => '0'); + + --signal counter : integer := 0; + --signal probe2 : std_logic_vector(2 downto 0); + --signal trig_in, trig_in_ack : std_logic := '0'; + signal rst_n : std_logic := '0'; + signal rst1, clk1 : std_logic := '0'; + signal clk_user : std_logic_vector(N_OF_QUADS-1 downto 0); + + component ten_gig_eth_pcs_pma_0 is + port ( + dclk : in std_logic; + refclk_p : in std_logic; + refclk_n : in std_logic; + sim_speedup_control : in std_logic; + core_clk156_out : out std_logic; + qplloutclk_out : out std_logic; + qplloutrefclk_out : out std_logic; + qplllock_out : out std_logic; + txusrclk_out : out std_logic; + txusrclk2_out : out std_logic; + areset_clk156_out : out std_logic; + gttxreset_out : out std_logic; + gtrxreset_out : out std_logic; + txuserrdy_out : out std_logic; + reset_counter_done_out : out std_logic; + reset : in std_logic; + gt0_eyescanreset : in std_logic; + gt0_eyescantrigger : in std_logic; + gt0_rxcdrhold : in std_logic; + gt0_txprbsforceerr : in std_logic; + gt0_txpolarity : in std_logic; + gt0_rxpolarity : in std_logic; + gt0_rxrate : in std_logic_vector (2 downto 0); + gt0_txpmareset : in std_logic; + gt0_rxpmareset : in std_logic; + gt0_rxdfelpmreset : in std_logic; + gt0_txprecursor : in std_logic_vector (4 downto 0); + gt0_txpostcursor : in std_logic_vector (4 downto 0); + gt0_txdiffctrl : in std_logic_vector (3 downto 0); + gt0_rxlpmen : in std_logic; + gt0_eyescandataerror : out std_logic; + gt0_txbufstatus : out std_logic_vector (1 downto 0); + gt0_txresetdone : out std_logic; + gt0_rxresetdone : out std_logic; + gt0_rxbufstatus : out std_logic_vector (2 downto 0); + gt0_rxprbserr : out std_logic; + gt0_dmonitorout : out std_logic_vector (7 downto 0); + xgmii_txd : in std_logic_vector (63 downto 0); + xgmii_txc : in std_logic_vector (7 downto 0); + xgmii_rxd : out std_logic_vector (63 downto 0); + xgmii_rxc : out std_logic_vector (7 downto 0); + txp : out std_logic; + txn : out std_logic; + rxp : in std_logic; + rxn : in std_logic; + configuration_vector : in std_logic_vector (535 downto 0); + status_vector : out std_logic_vector (447 downto 0); + core_status : out std_logic_vector (7 downto 0); + resetdone : out std_logic; + signal_detect : in std_logic; + tx_fault : in std_logic; + drp_req : out std_logic; + drp_gnt : in std_logic; + drp_den_o : out std_logic; + drp_dwe_o : out std_logic; + drp_daddr_o : out std_logic_vector (15 downto 0); + drp_di_o : out std_logic_vector (15 downto 0); + drp_drdy_i : in std_logic; + drp_drpdo_i : in std_logic_vector (15 downto 0); + drp_den_i : in std_logic; + drp_dwe_i : in std_logic; + drp_daddr_i : in std_logic_vector (15 downto 0); + drp_di_i : in std_logic_vector (15 downto 0); + drp_drdy_o : out std_logic; + drp_drpdo_o : out std_logic_vector (15 downto 0); + pma_pmd_type : in std_logic_vector (2 downto 0); + tx_disable : out std_logic); + end component ten_gig_eth_pcs_pma_0; + + component ten_gig_eth_pcs_pma_1 is + port ( + dclk : in std_logic; + clk156 : in std_logic; + txusrclk : in std_logic; + txusrclk2 : in std_logic; + txclk322 : out std_logic; + areset : in std_logic; + areset_clk156 : in std_logic; + gttxreset : in std_logic; + gtrxreset : in std_logic; + sim_speedup_control : in std_logic; + txuserrdy : in std_logic; + qplllock : in std_logic; + qplloutclk : in std_logic; + qplloutrefclk : in std_logic; + reset_counter_done : in std_logic; + gt0_eyescanreset : in std_logic; + gt0_eyescantrigger : in std_logic; + gt0_rxcdrhold : in std_logic; + gt0_txprbsforceerr : in std_logic; + gt0_txpolarity : in std_logic; + gt0_rxpolarity : in std_logic; + gt0_rxrate : in std_logic_vector (2 downto 0); + gt0_txpmareset : in std_logic; + gt0_rxpmareset : in std_logic; + gt0_rxdfelpmreset : in std_logic; + gt0_txprecursor : in std_logic_vector (4 downto 0); + gt0_txpostcursor : in std_logic_vector (4 downto 0); + gt0_txdiffctrl : in std_logic_vector (3 downto 0); + gt0_rxlpmen : in std_logic; + gt0_eyescandataerror : out std_logic; + gt0_txbufstatus : out std_logic_vector (1 downto 0); + gt0_txresetdone : out std_logic; + gt0_rxresetdone : out std_logic; + gt0_rxbufstatus : out std_logic_vector (2 downto 0); + gt0_rxprbserr : out std_logic; + gt0_dmonitorout : out std_logic_vector (7 downto 0); + xgmii_txd : in std_logic_vector (63 downto 0); + xgmii_txc : in std_logic_vector (7 downto 0); + xgmii_rxd : out std_logic_vector (63 downto 0); + xgmii_rxc : out std_logic_vector (7 downto 0); + txp : out std_logic; + txn : out std_logic; + rxp : in std_logic; + rxn : in std_logic; + configuration_vector : in std_logic_vector (535 downto 0); + status_vector : out std_logic_vector (447 downto 0); + core_status : out std_logic_vector (7 downto 0); + tx_resetdone : out std_logic; + rx_resetdone : out std_logic; + signal_detect : in std_logic; + tx_fault : in std_logic; + drp_req : out std_logic; + drp_gnt : in std_logic; + drp_den_o : out std_logic; + drp_dwe_o : out std_logic; + drp_daddr_o : out std_logic_vector (15 downto 0); + drp_di_o : out std_logic_vector (15 downto 0); + drp_drdy_i : in std_logic; + drp_drpdo_i : in std_logic_vector (15 downto 0); + drp_den_i : in std_logic; + drp_dwe_i : in std_logic; + drp_daddr_i : in std_logic_vector (15 downto 0); + drp_di_i : in std_logic_vector (15 downto 0); + drp_drdy_o : out std_logic; + drp_drpdo_o : out std_logic_vector (15 downto 0); + pma_pmd_type : in std_logic_vector (2 downto 0); + tx_disable : out std_logic); + end component ten_gig_eth_pcs_pma_1; + + component fade_one_channel is + generic ( + my_mac : std_logic_vector(47 downto 0)); + port ( + xgmii_txd : out std_logic_vector(63 downto 0); + xgmii_txc : out std_logic_vector(7 downto 0); + xgmii_rxd : in std_logic_vector(63 downto 0); + xgmii_rxc : in std_logic_vector(7 downto 0); + rst_n : in std_logic; + clk_user : in std_logic); + end component fade_one_channel; + + component frq_counter is + generic ( + CNT_TIME : integer; + CNT_LENGTH : integer); + port ( + ref_clk : in std_logic; + rst_p : in std_logic; + frq_in : in std_logic; + frq_out : out std_logic_vector(CNT_LENGTH-1 downto 0)); + end component frq_counter; + + component vio_stat is + port ( + clk : in std_logic; + probe_in0 : in std_logic_vector(7 downto 0); + probe_in1 : in std_logic_vector(7 downto 0); + probe_in2 : in std_logic_vector(7 downto 0); + probe_in3 : in std_logic_vector(7 downto 0); + probe_in4 : in std_logic_vector(7 downto 0); + probe_in5 : in std_logic_vector(7 downto 0); + probe_in6 : in std_logic_vector(7 downto 0); + probe_in7 : in std_logic_vector(7 downto 0) + ); + end component; + +begin -- beh1 + si570_oe <= '1'; + clk_updaten <= '1'; + -- Initialization vector + --configuration_vector(0) <= '1'; -- PMA loopback + --configuration_vector(110) <= '1'; -- PCS loopback + configuration_vector(33) <= '1'; -- training + configuration_vector(284) <= '1'; -- auto negotiation + + signal_detect <= (others => '1'); -- allow transmission! + gtx_sfp_disable <= (others => '0'); + gtx_rate_sel <= (others => '1'); + + -- Reset generator + process (boot_clk) is + begin -- process + if boot_clk'event and boot_clk = '1' then -- rising clock edge + if rst_cnt > 0 then + rst_cnt <= rst_cnt - 1; + else + rst_p <= '0'; + end if; + end if; + end process; + + + rst_n <= not rst_p; + refclk_n <= gtx_refclk_n; + refclk_p <= gtx_refclk_p; + reset <= not rst_n; + + --trig_in <= '1' when xgmii_rxc /= x"ff" else '0'; + + gl1 : for q in 0 to N_OF_QUADS-1 generate + gl2 : for n in 0 to N_OF_LINKS-1 generate + + il1 : if n = 0 generate + ten_gig_eth_pcs_pma_0_1 : ten_gig_eth_pcs_pma_0 + port map ( + dclk => core_clk156_out(q), + sim_speedup_control => '0', + refclk_p => refclk_p(q), + refclk_n => refclk_n(q), + reset => reset, + resetdone => s_resetdone(q), + core_clk156_out => core_clk156_out(q), + txp => gtx10g_txp(q*N_OF_LINKS+n), + txn => gtx10g_txn(q*N_OF_LINKS+n), + rxp => gtx10g_rxp(q*N_OF_LINKS+n), + rxn => gtx10g_rxn(q*N_OF_LINKS+n), + txusrclk_out => s_txusrclk_out(q), + txusrclk2_out => s_txusrclk2_out(q), + areset_clk156_out => areset_clk156_out(q), + gttxreset_out => gttxreset_out(q), + gtrxreset_out => gtrxreset_out(q), + txuserrdy_out => txuserrdy_out(q), + reset_counter_done_out => reset_counter_done_out(q), + qplllock_out => qplllock_out(q), + qplloutclk_out => qplloutclk_out(q), + qplloutrefclk_out => qplloutrefclk_out(q), + xgmii_txd => xgmii_txd(q*N_OF_LINKS+n), + xgmii_txc => xgmii_txc(q*N_OF_LINKS+n), + xgmii_rxd => xgmii_rxd(q*N_OF_LINKS+n), + xgmii_rxc => xgmii_rxc(q*N_OF_LINKS+n), + configuration_vector => configuration_vector, + status_vector => status_vector(q*N_OF_LINKS+n), + core_status => core_status(q*N_OF_LINKS+n), + signal_detect => signal_detect(q*N_OF_LINKS+n), + tx_fault => tx_fault(q*N_OF_LINKS+n), + drp_req => drp_req(q*N_OF_LINKS+n), + drp_gnt => drp_gnt(q*N_OF_LINKS+n), + drp_den_o => drp_den_o(q*N_OF_LINKS+n), + drp_dwe_o => drp_dwe_o(q*N_OF_LINKS+n), + drp_daddr_o => drp_daddr_o(q*N_OF_LINKS+n), + drp_di_o => drp_di_o(q*N_OF_LINKS+n), + drp_drdy_o => drp_drdy_o(q*N_OF_LINKS+n), + drp_drpdo_o => drp_drpdo_o(q*N_OF_LINKS+n), + drp_den_i => drp_den_i(q*N_OF_LINKS+n), + drp_dwe_i => drp_dwe_i(q*N_OF_LINKS+n), + drp_daddr_i => drp_daddr_i(q*N_OF_LINKS+n), + drp_di_i => drp_di_i(q*N_OF_LINKS+n), + drp_drdy_i => drp_drdy_i(q*N_OF_LINKS+n), + drp_drpdo_i => drp_drpdo_i(q*N_OF_LINKS+n), + tx_disable => tx_disable(q*N_OF_LINKS+n), + pma_pmd_type => "111", + gt0_eyescanreset => '0', + gt0_eyescandataerror => open, + gt0_txbufstatus => open, + gt0_rxbufstatus => open, + gt0_eyescantrigger => '0', + gt0_rxcdrhold => '0', + gt0_txprbsforceerr => '0', + gt0_txpolarity => '0', + gt0_rxpolarity => '0', + gt0_rxprbserr => open, + gt0_txpmareset => '0', + gt0_rxpmareset => '0', + gt0_txresetdone => open, + gt0_rxresetdone => open, + gt0_rxdfelpmreset => '0', + gt0_rxlpmen => '0', + gt0_dmonitorout => open, + gt0_rxrate => (others => '0'), + gt0_txprecursor => (others => '0'), + gt0_txpostcursor => (others => '0'), + gt0_txdiffctrl => "1110" + + ); + + end generate il1; + il2 : if n /= 0 generate + ten_gig_eth_pcs_pma_1_1 : entity work.ten_gig_eth_pcs_pma_1 + port map ( + dclk => core_clk156_out(q), + clk156 => core_clk156_out(q), + txusrclk => s_txusrclk_out(q), + txusrclk2 => s_txusrclk2_out(q), + txclk322 => open, + areset => reset, + areset_clk156 => areset_clk156_out(q), + gttxreset => gttxreset_out(q), + gtrxreset => gtrxreset_out(q), + sim_speedup_control => '0', + txuserrdy => txuserrdy_out(q), + qplllock => qplllock_out(q), + qplloutclk => qplloutclk_out(q), + qplloutrefclk => qplloutrefclk_out(q), + reset_counter_done => reset_counter_done_out(q), + gt0_eyescanreset => '0', + gt0_eyescantrigger => '0', + gt0_rxcdrhold => '0', + gt0_txprbsforceerr => '0', + gt0_txpolarity => '0', + gt0_rxpolarity => '0', + gt0_rxrate => (others => '0'), + gt0_txpmareset => '0', + gt0_rxpmareset => '0', + gt0_rxdfelpmreset => '0', + gt0_txprecursor => (others => '0'), + gt0_txpostcursor => (others => '0'), + gt0_txdiffctrl => "1110", + gt0_rxlpmen => '0', + gt0_eyescandataerror => open, + gt0_txbufstatus => open, + gt0_txresetdone => open, + gt0_rxresetdone => open, + gt0_rxbufstatus => open, + gt0_rxprbserr => open, + gt0_dmonitorout => open, + xgmii_txd => xgmii_txd(q*N_OF_LINKS+n), + xgmii_txc => xgmii_txc(q*N_OF_LINKS+n), + xgmii_rxd => xgmii_rxd(q*N_OF_LINKS+n), + xgmii_rxc => xgmii_rxc(q*N_OF_LINKS+n), + txp => gtx10g_txp(q*N_OF_LINKS+n), + txn => gtx10g_txn(q*N_OF_LINKS+n), + rxp => gtx10g_rxp(q*N_OF_LINKS+n), + rxn => gtx10g_rxn(q*N_OF_LINKS+n), + configuration_vector => configuration_vector, + status_vector => status_vector(q*N_OF_LINKS+n), + core_status => core_status(q*N_OF_LINKS+n), + tx_resetdone => open, + rx_resetdone => open, + signal_detect => signal_detect(q*N_OF_LINKS+n), + tx_fault => tx_fault(q*N_OF_LINKS+n), + drp_req => drp_req(q*N_OF_LINKS+n), + drp_gnt => drp_gnt(q*N_OF_LINKS+n), + drp_den_o => drp_den_o(q*N_OF_LINKS+n), + drp_dwe_o => drp_dwe_o(q*N_OF_LINKS+n), + drp_daddr_o => drp_daddr_o(q*N_OF_LINKS+n), + drp_di_o => drp_di_o(q*N_OF_LINKS+n), + drp_drdy_i => drp_drdy_i(q*N_OF_LINKS+n), + drp_drpdo_i => drp_drpdo_i(q*N_OF_LINKS+n), + drp_den_i => drp_den_i(q*N_OF_LINKS+n), + drp_dwe_i => drp_dwe_i(q*N_OF_LINKS+n), + drp_daddr_i => drp_daddr_i(q*N_OF_LINKS+n), + drp_di_i => drp_di_i(q*N_OF_LINKS+n), + drp_drdy_o => drp_drdy_o(q*N_OF_LINKS+n), + drp_drpdo_o => drp_drpdo_o(q*N_OF_LINKS+n), + pma_pmd_type => "111", + tx_disable => tx_disable(q*N_OF_LINKS+n)); + end generate il2; + + drp_gnt(q*N_OF_LINKS+n) <= drp_req(q*N_OF_LINKS+n); + drp_den_i(q*N_OF_LINKS+n) <= drp_den_o(q*N_OF_LINKS+n); + drp_dwe_i(q*N_OF_LINKS+n) <= drp_dwe_o(q*N_OF_LINKS+n); + drp_daddr_i(q*N_OF_LINKS+n) <= drp_daddr_o(q*N_OF_LINKS+n); + drp_di_i(q*N_OF_LINKS+n) <= drp_di_o(q*N_OF_LINKS+n); + drp_drpdo_i(q*N_OF_LINKS+n) <= drp_drpdo_o(q*N_OF_LINKS+n); + + fade_one_channel_1 : entity work.fade_one_channel + generic map ( + my_mac => mac_table(q*N_OF_LINKS+n)) + port map ( + xgmii_txd => xgmii_txd(q*N_OF_LINKS+n), + xgmii_txc => xgmii_txc(q*N_OF_LINKS+n), + xgmii_rxd => xgmii_rxd(q*N_OF_LINKS+n), + xgmii_rxc => xgmii_rxc(q*N_OF_LINKS+n), + rst_n => rst_n, + clk_user => clk_user(q)); + + + end generate gl2; + + frq_counter_1: entity work.frq_counter + generic map ( + CNT_TIME => 20000000, + CNT_LENGTH => 32) + port map ( + ref_clk => boot_clk, + rst_p => rst_p, + frq_in => clk_user(q), + frq_out => frq_user(q)); + + + end generate gl1; + + clk0_frq <= frq_user(0); + clk1_frq <= frq_user(1); + + rst1 <= core_status(0)(0); + --core_ready <= core_status(0); + clk1 <= boot_clk; + clk_user <= core_clk156_out; + + -- Frequency meters + vio_frq_1 : entity work.vio_frq + port map ( + clk => boot_clk, + probe_in0 => clk0_frq, + probe_in1 => clk1_frq); + + -- Vio Link statuses + vio_stat_1 : entity work.vio_stat + port map ( + clk => boot_clk, + probe_in0 => core_status(0), + probe_in1 => core_status(1), + probe_in2 => core_status(2), + probe_in3 => core_status(3), + probe_in4 => core_status(4), + probe_in5 => core_status(5), + probe_in6 => core_status(6), + probe_in7 => core_status(7)); + + -- JTAG<->I2C part for clock-crossbar + i2c_vio_ctrl_1 : entity work.i2c_vio_ctrl + port map ( + clk => boot_clk, + scl => scl, + sda => sda); + + gld1 : for i in 0 to 1 generate + p1 : process (clk_user(i), rst_n) + begin -- process p1 + if rst_n = '0' then -- asynchronous reset (active low) + heart_bit(i) <= 0; + elsif clk_user(i)'event and clk_user(i) = '1' then -- rising clock edge + if heart_bit(i) < 80000000 then + heart_bit(i) <= heart_bit(i) + 1; + else + heart_bit(i) <= 0; + s_hb_led(i) <= not s_hb_led(i); + end if; + end if; + end process p1; + + end generate gld1; + + p2 : process (boot_clk, rst_n) + begin -- process p1 + if rst_n = '0' then -- asynchronous reset (active low) + heart_bit(2) <= 0; + elsif boot_clk'event and boot_clk = '1' then -- rising clock edge + if heart_bit(2) < 10000000 then + heart_bit(2) <= heart_bit(2) + 1; + else + heart_bit(2) <= 0; + s_hb_led(2) <= not s_hb_led(2); + end if; + end if; + end process p2; + + hb_led <= s_hb_led; + +end beh1; Index: trunk/experimental_jumbo_frames_version/fpga/src/AFCK/vio_stat/vio_stat.xci =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/src/AFCK/vio_stat/vio_stat.xci (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/src/AFCK/vio_stat/vio_stat.xci (revision 37) @@ -0,0 +1,810 @@ + + + xilinx.com + xci + unknown + 1.0 + + + vio_stat + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 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1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 8 + 8 + 8 + 8 + 8 + 8 + 8 + 8 + 1 + 0 + 1 + 8 + vio_stat + kintex7 + 8 + 1 + 0 + kintex7 + xc7k325t + ffg900 + -2 + C + + VHDL + MIXED + TRUE + TRUE + xilinx.com:kc705:part0:0.9 + TRUE + 2014.4 + 5 + OUT_OF_CONTEXT + + . + . + + + + Index: trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c_tools/ADN4604.tcl =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c_tools/ADN4604.tcl (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c_tools/ADN4604.tcl (revision 37) @@ -0,0 +1,23 @@ +global ADN4604_adr +set ADN4604_adr 75 +proc ADN4604_read { reg_nr } { + global ADN4604_adr + i2c_write $ADN4604_adr [list $reg_nr] + return [i2c_single_read $ADN4604_adr ] +} + +proc ADN4604_write { reg_nr val} { + global ADN4604_adr + i2c_write $ADN4604_adr [list $reg_nr $val] +} + + +proc ADN4604_dump_regs {first last step} { + global ADN4604_adr + for {set ad [expr $first]} {$ad <= [expr $last]} {set ad [expr $ad + $step]} { + puts "[format "0x%x:0x%x" $ad [ADN4604_read $ad]]" + } +} + + + Index: trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c_tools/start_10g_links.tcl =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c_tools/start_10g_links.tcl (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c_tools/start_10g_links.tcl (revision 37) @@ -0,0 +1,11 @@ +source i2c_tools.tcl +i2c_write 112 [list 10] +source Si_156.tcl +SiSetFrq 156250000 +i2c_write 112 [list 12] +source ADN4604.tcl +ADN4604_write 0x93 [list 0xff] +ADN4604_write 0x94 [list 0xff] +ADN4604_write 0x81 [list 0x00] +ADN4604_write 0x80 [list 0x01] + Index: trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c_tools/Si_156.tcl =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c_tools/Si_156.tcl (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c_tools/Si_156.tcl (revision 37) @@ -0,0 +1,108 @@ +set Si57x_adr [expr 0x55] +set I2C_MUX_adr 112 + +proc Si57x_write_reg {adr val} { + global Si57x_adr + i2c_write $Si57x_adr [list $adr $val] +} + +proc Si57x_read_reg {adr} { + global Si57x_adr + i2c_write $Si57x_adr [list $adr] + set res [i2c_single_read $Si57x_adr] + return $res +} + +proc SiSetFrq {frq} { + global I2C_MUX_adr + #Save old mux setting and set mux to Si57x + set oldmux [i2c_single_read $I2C_MUX_adr] + i2c_write $I2C_MUX_adr [list 10] + #Reset Silabs to initial settings + Si57x_write_reg 0x87 0x01 + #Now read rfreq + set r7 [Si57x_read_reg 7] + set hsdiv [expr ($r7 & 0xe0)>>5] + set hsdiv [expr $hsdiv+4] + set n1 [expr ($r7 & 0x1f)<<2] + set r8 [Si57x_read_reg 8] + set n1 [expr $n1 | (($r8 & 192)>>6)] + set n1 [expr $n1 + 1] + set rfreq [expr $r8 & 63] + set adr 9 + while {$adr<=12} { + set rfreq [expr $rfreq * 256] + set rfreq [expr [Si57x_read_reg $adr] | $rfreq] + incr adr + } + set fxtal [expr 100e6*(1<<28)/$rfreq*$hsdiv*$n1] + #Print the xtal frequency + puts "fxtal=$fxtal frq=$frq" + #Calculate the new values + #To minimize the power consumption, we look for the minimal + #value of N1 and maximum value of HSDIV, keeping the + #DCO=frq*N1*HSDIV in range 4.85 to 5.67 GHz + #We browse possible values of N1 and hsdiv looking for the best + #combination + #Below is the list of valid N1 values + set hsdvals {{7 11.0} {5 9.0} {3 7.0} {2 6.0} {1 5.0} {0 4.0}} + #set hsdvals {{0 4.0} {1 5.0} {2 6.0} {3 7.0} {5 9.0} {7 11.0}} + set found 0 + foreach hsdl $hsdvals { + set hsdr [lindex $hsdl 0] + set hsdv [lindex $hsdl 1] + puts "hsdr=$hsdr hsdv=$hsdv" + #Now we check possible hsdiv values and take the greatest + #matching the condition + set n1v 1 + while {$n1v<=128} { + set fdco [expr $frq * $n1v] + set fdco [expr $fdco * $hsdv] + puts "frq=$frq fdco=$fdco n1v=$n1v hsdv=$hsdv" + if {($fdco >= 4.85e9) & ($fdco <= 5.67e9)} { + set found 1 + break + } + if {$n1v<2} { + set n1v [expr $n1v+1] + } else { + set n1v [expr $n1v+2] + } + } + if {$found==1} { + break + } + } + #Check if the proper value was found + if {$found==0} { + error "Proper values N1 HSDIV not found" + } else { + puts "fdco=$fdco N1=$n1v HSDIV=$hsdv" + } + #Calculate the nfreq + set nfreq [expr int($fdco*(1<<28)/$fxtal + 0.5)] + puts [format %x $nfreq] + Si57x_write_reg 0x89 0x10 + Si57x_write_reg 0x87 0x30 + #Decrement n1v, before writing to the register + set n1v [expr $n1v-1] + #Now store the values + set r7 [expr ($hsdr << 5) | ($n1v>>2)] + puts [format "r7: %x" $r7] + Si57x_write_reg 7 $r7 + set adr 12 + while {$adr>8} { + set rval [expr $nfreq & 255] + puts [format "r%d: %x" $adr $rval] + Si57x_write_reg $adr $rval + set nfreq [expr $nfreq >> 8] + set adr [expr $adr - 1] + } + set rval [expr (($n1v & 0x3)<<6) | $nfreq] + Si57x_write_reg 8 $rval + puts [format "r8: %x" $rval] + Si57x_write_reg 0x89 0x00 + Si57x_write_reg 0x87 0x40 + i2c_write $I2C_MUX_adr [list $oldmux] +} + Index: trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c_tools/i2c_tools.tcl =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c_tools/i2c_tools.tcl (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c_tools/i2c_tools.tcl (revision 37) @@ -0,0 +1,165 @@ +# AFCK - MUX PCA9547 under 112 +# should be written 12 to enable access from FPGA to other chips +# +set vio_path "i2c_vio_ctrl_1" +proc read_vio {name} { + global vio_path + refresh_hw_vio [get_hw_vios hw_vio_1] + set res [get_property INPUT_VALUE [get_hw_probes $vio_path/$name -of_objects [get_hw_vios hw_vio_1]]] + return $res +} + +proc set_vio_now {name val} { + global vio_path + #puts "val=$val name=$name" + set_property OUTPUT_VALUE $val [get_hw_probes $vio_path/$name -of_objects [get_hw_vios hw_vio_1]] + commit_hw_vio [get_hw_probes $vio_path/$name -of_objects [get_hw_vios hw_vio_1]] +} + +proc set_vio {name val} { + global vio_path + set_property OUTPUT_VALUE $val [get_hw_probes $vio_path/$name -of_objects [get_hw_vios hw_vio_1]] +} +proc com_set_vio {} { + global vio_path + commit_hw_vio [get_hw_probes [list $vio_path/vrst_n $vio_path/i2c_rst_n $vio_path/din $vio_path/addr $vio_path/rd_nwr $vio_path/cs]] +} + +proc i2c_reg_write {ad dana} { + set_vio addr $ad + set_vio din $dana + set_vio rd_nwr 0 + com_set_vio + set_vio_now cs 1 + set_vio_now cs 0 +} + +proc i2c_reg_read {ad } { + set_vio addr $ad + set_vio rd_nwr 1 + com_set_vio + set_vio_now cs 1 + set_vio_now cs 0 + refresh_hw_vio [get_hw_vios hw_vio_1] + set res [read_vio dout] + return $res +} + +proc i2c_write {ad dta} { + i2c_reg_write 3 [expr $ad << 1] + # Transmit + i2c_reg_write 4 [expr 128 | 16] + # Cmd: STA+WR + #Wait for ACK + while { 1 } { + set st [i2c_reg_read 4] + if {[expr ($st & 2) == 0]} break + if {[expr ($st & 128) != 0]} { + #Error - NACK + error "NACK in address" + } + } + set i [llength $dta] + foreach d $dta { + set i [expr $i - 1] + i2c_reg_write 3 [expr $d] + if {[expr $i == 0]} { + i2c_reg_write 4 [expr 64 | 16] + } else { + i2c_reg_write 4 16 + } + while { 1 } { + set st [i2c_reg_read 4] + if {[expr ($st & 2) == 0]} break + } + if {[expr ($st & 0x80) != 0]} { + #Error - NACK + error "NACK in data" + } + } +} + +proc i2c_single_read {ad} { + i2c_reg_write 3 [expr ($ad << 1)|1] + # Receive + i2c_reg_write 4 [expr 128 | 16] + # Cmd: STA+WR + #Wait for ACK + while { 1 } { + set st [i2c_reg_read 4] + #puts "st=$st in addr" + if {[expr ($st & 2) == 0]} break + } + if {[expr ($st & 128) != 0]} { + #Error - NACK + error "NACK in address" + } + i2c_reg_write 4 [expr 64 | 32 | 8] + while { 1 } { + set st [i2c_reg_read 4] + #puts "st=$st in data" + if {[expr ($st & 2) == 0]} break + } + #if {[expr ($st & 128) != 0]} { + # #Error - NACK + # error "NACK in data" + #} + set res [i2c_reg_read 3] + return $res +} + +proc i2c_multi_read {ad num} { + i2c_reg_write 3 [expr ($ad << 1)|1] + # Receive + i2c_reg_write 4 [expr 128 | 16] + # Cmd: STA+WR + #Wait for ACK + while { 1 } { + set st [i2c_reg_read 4] + puts "st=$st in addr" + if {[expr ($st & 2) == 0]} break + } + if {[expr ($st & 128) != 0]} { + #Error - NACK + error "NACK in address" + } + set res [list ] + while {$num > 0} { + if {[expr $num == 1]} { + i2c_reg_write 4 [expr 64 | 32 | 8 ] + } else { + i2c_reg_write 4 [expr 32 ] + } + while { 1 } { + set st [i2c_reg_read 4] + puts "st=$st in data" + if {[expr ($st & 2) == 0]} break + } + lappend res [i2c_reg_read 3] + if {[expr ($st & 128) != 0]} { + # NACK - no more data + break + } + set num [expr $num - 1] + } + return $res +} + +open_hw +current_hw_target [get_hw_targets *] +current_hw_device [lindex [get_hw_devices] 0] +foreach node [list vrst_n i2c_rst_n din addr rd_nwr cs] { + set_property OUTPUT_VALUE_RADIX UNSIGNED [get_hw_probes $vio_path/$node -of_objects [get_hw_vios hw_vio_1]] +} +foreach node [list dout] { + set_property INPUT_VALUE_RADIX UNSIGNED [get_hw_probes $vio_path/$node -of_objects [get_hw_vios hw_vio_1]] +} +set_vio_now vrst_n 0 +set_vio_now vrst_n 1 +set_vio_now i2c_rst_n 1 +i2c_reg_write 0 200 +i2c_reg_write 1 0 +i2c_reg_write 2 128 +#i2c_write 112 [list 12] +#i2c_single_read 76 + Index: trunk/experimental_jumbo_frames_version/fpga/src/AFCK/fade_afck_8ch.xdc =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/src/AFCK/fade_afck_8ch.xdc (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/src/AFCK/fade_afck_8ch.xdc (revision 37) @@ -0,0 +1,79 @@ +set_property IOSTANDARD LVCMOS15 [get_ports boot_clk] +set_property PACKAGE_PIN AF6 [get_ports boot_clk] + +set_property IOSTANDARD LVCMOS25 [get_ports {hb_led[0]}] +set_property PACKAGE_PIN G23 [get_ports {hb_led[0]}] +set_property IOSTANDARD LVCMOS25 [get_ports {hb_led[1]}] +set_property PACKAGE_PIN G25 [get_ports {hb_led[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {hb_led[2]}] +set_property PACKAGE_PIN F23 [get_ports {hb_led[2]}] + +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[7]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[6]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[5]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[4]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[3]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[2]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_sfp_disable[0]}] + +#Clocks fed directly from FMC1 and FMC2 GBTCLK0/1 +#set_property PACKAGE_PIN E8 [get_ports {gtx_refclk_p[0]}] +#set_property PACKAGE_PIN G8 [get_ports {gtx_refclk_p[1]}] + +#Clock from clock matrix via LINK01 and LINK23 +set_property PACKAGE_PIN C8 [get_ports {gtx_refclk_p[0]}] +set_property PACKAGE_PIN J8 [get_ports {gtx_refclk_p[1]}] + +set_property PACKAGE_PIN AE16 [get_ports clk_updaten] +set_property IOSTANDARD LVCMOS18 [get_ports clk_updaten] + +set_property PACKAGE_PIN Y20 [get_ports si570_oe] +set_property IOSTANDARD LVCMOS25 [get_ports si570_oe] + +create_clock -period 50.000 -name boot_clk -waveform {0.000 25.000} [get_nets boot_clk] + +create_clock -period 6.400 -name clk156 -waveform {0.000 3.200} [get_nets *156*] +create_clock -period 6.400 -name gtx_refclk -waveform {0.000 3.200} [get_ports {gtx_refclk_n gtx_refclk_p}] + +set_property PACKAGE_PIN E19 [get_ports {gtx_sfp_disable[0]}] +set_property PACKAGE_PIN A23 [get_ports {gtx_sfp_disable[1]}] +set_property PACKAGE_PIN C29 [get_ports {gtx_sfp_disable[2]}] +set_property PACKAGE_PIN F28 [get_ports {gtx_sfp_disable[3]}] +set_property PACKAGE_PIN T25 [get_ports {gtx_sfp_disable[4]}] +set_property PACKAGE_PIN AA28 [get_ports {gtx_sfp_disable[5]}] +set_property PACKAGE_PIN Y30 [get_ports {gtx_sfp_disable[6]}] +set_property PACKAGE_PIN AK28 [get_ports {gtx_sfp_disable[7]}] + +set_property PACKAGE_PIN H26 [get_ports {gtx_rate_sel[0]}] +set_property PACKAGE_PIN A26 [get_ports {gtx_rate_sel[1]}] +set_property PACKAGE_PIN E29 [get_ports {gtx_rate_sel[2]}] +set_property PACKAGE_PIN F30 [get_ports {gtx_rate_sel[3]}] +set_property PACKAGE_PIN AE30 [get_ports {gtx_rate_sel[4]}] +set_property PACKAGE_PIN W28 [get_ports {gtx_rate_sel[5]}] +set_property PACKAGE_PIN AG27 [get_ports {gtx_rate_sel[6]}] +set_property PACKAGE_PIN AB30 [get_ports {gtx_rate_sel[7]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[0]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[2]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[3]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[4]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[5]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[6]}] +set_property IOSTANDARD LVCMOS25 [get_ports {gtx_rate_sel[7]}] + +set_property PACKAGE_PIN A8 [get_ports {gtx10g_rxp[0]}] +set_property PACKAGE_PIN B6 [get_ports {gtx10g_rxp[1]}] +set_property PACKAGE_PIN D6 [get_ports {gtx10g_rxp[2]}] +set_property PACKAGE_PIN E4 [get_ports {gtx10g_rxp[3]}] +set_property PACKAGE_PIN F6 [get_ports {gtx10g_rxp[4]}] +set_property PACKAGE_PIN G4 [get_ports {gtx10g_rxp[5]}] +set_property PACKAGE_PIN H6 [get_ports {gtx10g_rxp[6]}] +set_property PACKAGE_PIN K6 [get_ports {gtx10g_rxp[7]}] + +set_property IOSTANDARD LVCMOS25 [get_ports scl] +set_property IOSTANDARD LVCMOS25 [get_ports sda] +set_property PACKAGE_PIN K19 [get_ports scl] +set_property PACKAGE_PIN G19 [get_ports sda] + + Index: trunk/experimental_jumbo_frames_version/fpga/src/AFCK/vio_frq/vio_frq.xci =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/src/AFCK/vio_frq/vio_frq.xci (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/src/AFCK/vio_frq/vio_frq.xci (revision 37) @@ -0,0 +1,810 @@ + + + xilinx.com + xci + unknown + 1.0 + + + vio_frq + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 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2014.4 + 5 + OUT_OF_CONTEXT + + . + . + + + + Index: trunk/experimental_jumbo_frames_version/fpga/src/AFCK/frq_counter.vhd =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/src/AFCK/frq_counter.vhd (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/src/AFCK/frq_counter.vhd (revision 37) @@ -0,0 +1,96 @@ +------------------------------------------------------------------------------- +-- Title : frq_counter +-- Project : +------------------------------------------------------------------------------- +-- File : frq_counter.vhd +-- Author : Wojciech M. Zabolotny +-- Company : +-- Created : 2015-05-15 +-- Last update: 2015-05-15 +-- Platform : +-- Standard : VHDL'93/02 +------------------------------------------------------------------------------- +-- Description: Simple frequency counter for monitoring of clock frequency +-- inside FPGA +------------------------------------------------------------------------------- +-- Copyright (c) 2015 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2015-05-15 1.0 wzab Created +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity frq_counter is + + generic ( + CNT_TIME : integer := 10000000; -- Counting time in cycles of ref_clk; + CNT_LENGTH : integer := 32); -- Length of the pulse counter + + port ( + ref_clk : in std_logic; + rst_p : in std_logic; + frq_in : in std_logic; + frq_out : out std_logic_vector(CNT_LENGTH-1 downto 0)); + +end entity frq_counter; + +architecture beh of frq_counter is + + signal pulse_cnt : unsigned(CNT_LENGTH-1 downto 0) := (others => '0'); + signal gate_cnt : integer range 0 to CNT_TIME+2 := 0; + signal clear, gate, gate_ack, clear_ack : std_logic := '0'; + +begin -- architecture beh + + clk1: process (ref_clk, rst_p) is + begin -- process clk1 + if rst_p = '1' then -- asynchronous reset (active low) + gate_cnt <= 0; + frq_out <= (others => '0'); + elsif ref_clk'event and ref_clk = '1' then -- rising clock edge + if gate_cnt = 0 then + gate <= '1'; + gate_cnt <= gate_cnt + 1; + elsif gate_cnt = CNT_TIME then + gate <= '0'; + if gate_ack = '0' then + frq_out <= std_logic_vector(pulse_cnt); + clear <= '1'; + gate_cnt <= gate_cnt+1; + end if; + elsif gate_cnt = CNT_TIME+1 then + if clear_ack = '1' then + clear <= '0'; + gate_cnt <= CNT_TIME+2; + end if; + elsif gate_cnt = CNT_TIME+2 then + if clear_ack = '0' then + gate_cnt <= 0; + end if; + else + gate_cnt <= gate_cnt + 1; + end if; + end if; + end process clk1; + + clk2: process (frq_in, rst_p) is + begin -- process clk2 + if rst_p = '1' then -- asynchronous reset (active low) + pulse_cnt <= (others => '0'); + gate_ack <= '0'; + clear_ack <= '0'; + elsif frq_in'event and frq_in = '1' then -- rising clock edge + gate_ack <= gate; + clear_ack <= clear; + if gate_ack = '1' then + pulse_cnt <= pulse_cnt + 1; + elsif clear_ack = '1' then + pulse_cnt <= (others => '0'); + end if; + end if; + end process clk2; + +end architecture beh; Index: trunk/experimental_jumbo_frames_version/fpga/src/AFCK/vio_0/vio_0.xci =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/src/AFCK/vio_0/vio_0.xci (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/src/AFCK/vio_0/vio_0.xci (revision 37) @@ -0,0 +1,810 @@ + + + xilinx.com + xci + unknown + 1.0 + + + vio_0 + + + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 0x0 + 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trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c/i2c_master_byte_ctrl.vhd (revision 37) @@ -0,0 +1,368 @@ +--------------------------------------------------------------------- +---- ---- +---- WISHBONE revB2 compl. I2C Master Core; byte-controller ---- +---- ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2000 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- CVS Log +-- +-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004-02-18 11:41:48 rherveille Exp $ +-- +-- $Date: 2004-02-18 11:41:48 $ +-- $Revision: 1.5 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- Revision 1.4 2003/08/09 07:01:13 rherveille +-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +-- Fixed a potential bug in the byte controller's host-acknowledge generation. +-- +-- Revision 1.3 2002/12/26 16:05:47 rherveille +-- Core is now a Multimaster I2C controller. +-- +-- Revision 1.2 2002/11/30 22:24:37 rherveille +-- Cleaned up code +-- +-- Revision 1.1 2001/11/05 12:02:33 rherveille +-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. +-- Code updated, is now up-to-date to doc. rev.0.4. +-- Added headers. +-- + + + + +-- +------------------------------------------ +-- Byte controller section +------------------------------------------ +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity i2c_master_byte_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) + nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- 4x SCL + + -- input signals + start, + stop, + read, + write, + ack_in : std_logic; + din : in std_logic_vector(7 downto 0); + + -- output signals + cmd_ack : out std_logic; -- command done + ack_out : out std_logic; + i2c_busy : out std_logic; -- arbitration lost + i2c_al : out std_logic; -- i2c bus busy + dout : out std_logic_vector(7 downto 0); + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); +end entity i2c_master_byte_ctrl; + +architecture structural of i2c_master_byte_ctrl is + component i2c_master_bit_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; + nReset : in std_logic; + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- clock prescale value + + cmd : in std_logic_vector(3 downto 0); + cmd_ack : out std_logic; -- command done + busy : out std_logic; -- i2c bus busy + al : out std_logic; -- arbitration lost + + din : in std_logic; + dout : out std_logic; + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); + end component i2c_master_bit_ctrl; + + -- commands for bit_controller block + constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; + constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; + constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; + constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; + constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; + + -- signals for bit_controller + signal core_cmd : std_logic_vector(3 downto 0); + signal core_ack, core_txd, core_rxd : std_logic; + signal al : std_logic; + + -- signals for shift register + signal sr : std_logic_vector(7 downto 0); -- 8bit shift register + signal shift, ld : std_logic; + + -- signals for state machine + signal go, host_ack : std_logic; + signal dcnt : unsigned(2 downto 0); -- data counter + signal cnt_done : std_logic; + +begin + -- hookup bit_controller + bit_ctrl: i2c_master_bit_ctrl port map( + clk => clk, + rst => rst, + nReset => nReset, + ena => ena, + clk_cnt => clk_cnt, + cmd => core_cmd, + cmd_ack => core_ack, + busy => i2c_busy, + al => al, + din => core_txd, + dout => core_rxd, + scl_i => scl_i, + scl_o => scl_o, + scl_oen => scl_oen, + sda_i => sda_i, + sda_o => sda_o, + sda_oen => sda_oen + ); + i2c_al <= al; + + -- generate host-command-acknowledge + cmd_ack <= host_ack; + + -- generate go-signal + go <= (read or write or stop) and not host_ack; + + -- assign Dout output to shift-register + dout <= sr; + + -- generate shift register + shift_register: process(clk, nReset) + begin + if (nReset = '0') then + sr <= (others => '0'); + elsif (clk'event and clk = '1') then + if (rst = '1') then + sr <= (others => '0'); + elsif (ld = '1') then + sr <= din; + elsif (shift = '1') then + sr <= (sr(6 downto 0) & core_rxd); + end if; + end if; + end process shift_register; + + -- generate data-counter + data_cnt: process(clk, nReset) + begin + if (nReset = '0') then + dcnt <= (others => '0'); + elsif (clk'event and clk = '1') then + if (rst = '1') then + dcnt <= (others => '0'); + elsif (ld = '1') then + dcnt <= (others => '1'); -- load counter with 7 + elsif (shift = '1') then + dcnt <= dcnt -1; + end if; + end if; + end process data_cnt; + + cnt_done <= '1' when (dcnt = 0) else '0'; + + -- + -- state machine + -- + statemachine : block + type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop); + signal c_state : states; + begin + -- + -- command interpreter, translate complex commands into simpler I2C commands + -- + nxt_state_decoder: process(clk, nReset) + begin + if (nReset = '0') then + core_cmd <= I2C_CMD_NOP; + core_txd <= '0'; + shift <= '0'; + ld <= '0'; + host_ack <= '0'; + c_state <= st_idle; + ack_out <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1' or al = '1') then + core_cmd <= I2C_CMD_NOP; + core_txd <= '0'; + shift <= '0'; + ld <= '0'; + host_ack <= '0'; + c_state <= st_idle; + ack_out <= '0'; + else + -- initialy reset all signal + core_txd <= sr(7); + shift <= '0'; + ld <= '0'; + host_ack <= '0'; + + case c_state is + when st_idle => + if (go = '1') then + if (start = '1') then + c_state <= st_start; + core_cmd <= I2C_CMD_START; + elsif (read = '1') then + c_state <= st_read; + core_cmd <= I2C_CMD_READ; + elsif (write = '1') then + c_state <= st_write; + core_cmd <= I2C_CMD_WRITE; + else -- stop + c_state <= st_stop; + core_cmd <= I2C_CMD_STOP; + end if; + + ld <= '1'; + end if; + + when st_start => + if (core_ack = '1') then + if (read = '1') then + c_state <= st_read; + core_cmd <= I2C_CMD_READ; + else + c_state <= st_write; + core_cmd <= I2C_CMD_WRITE; + end if; + + ld <= '1'; + end if; + + when st_write => + if (core_ack = '1') then + if (cnt_done = '1') then + c_state <= st_ack; + core_cmd <= I2C_CMD_READ; + else + c_state <= st_write; -- stay in same state + core_cmd <= I2C_CMD_WRITE; -- write next bit + shift <= '1'; + end if; + end if; + + when st_read => + if (core_ack = '1') then + if (cnt_done = '1') then + c_state <= st_ack; + core_cmd <= I2C_CMD_WRITE; + else + c_state <= st_read; -- stay in same state + core_cmd <= I2C_CMD_READ; -- read next bit + end if; + + shift <= '1'; + core_txd <= ack_in; + end if; + + when st_ack => + if (core_ack = '1') then + -- check for stop; Should a STOP command be generated ? + if (stop = '1') then + c_state <= st_stop; + core_cmd <= I2C_CMD_STOP; + else + c_state <= st_idle; + core_cmd <= I2C_CMD_NOP; + + -- generate command acknowledge signal + host_ack <= '1'; + end if; + + -- assign ack_out output to core_rxd (contains last received bit) + ack_out <= core_rxd; + + core_txd <= '1'; + else + core_txd <= ack_in; + end if; + + when st_stop => + if (core_ack = '1') then + c_state <= st_idle; + core_cmd <= I2C_CMD_NOP; + + -- generate command acknowledge signal + host_ack <= '1'; + end if; + + when others => -- illegal states + c_state <= st_idle; + core_cmd <= I2C_CMD_NOP; + report ("Byte controller entered illegal state."); + + end case; + + end if; + end if; + end process nxt_state_decoder; + + end block statemachine; + +end architecture structural; + Index: trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c/i2c_bus_wrap.vhd =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c/i2c_bus_wrap.vhd (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c/i2c_bus_wrap.vhd (revision 37) @@ -0,0 +1,200 @@ +------------------------------------------------------------------------------- +-- Title : I2C bus wrapper +-- Project : +------------------------------------------------------------------------------- +-- File : i2c_bus_wrap.vhd +-- Author : Wojciech M. Zabolotny wzab01gmail.com +-- License : PUBLIC DOMAIN +-- Company : +-- Created : 2015-05-05 +-- Last update: 2015-05-05 +-- Platform : +-- Standard : VHDL'93/02 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2015 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2015-05-05 1.0 xl Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +--use ieee.std_logic_arith.all; +--USE ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity i2c_bus_wrap is + + port ( + -- System interface + din : in std_logic_vector(7 downto 0); -- input data + dout : out std_logic_vector(7 downto 0); -- output data + addr : in std_logic_vector(2 downto 0); -- address + rd_nwr : in std_logic; + cs : in std_logic; -- address decoder output, active '1' + clk : in std_logic; + rst : in std_logic; + i2c_rst : in std_logic; + -- Interfejs I2C + scl_i : in std_logic; + scl_o : out std_logic; + sda_i : in std_logic; + sda_o : out std_logic + ); +end; -- entity i2c_bus_wrap; + +architecture i2c_beh of i2c_bus_wrap is + + component i2c_master_top + generic( + ARST_LVL : std_logic -- asynchronous reset level + ); + port ( + -- wishbone signals + wb_clk_i : in std_logic; -- master clock input + wb_rst_i : in std_logic; -- synchronous active high reset + arst_i : in std_logic; -- asynchronous reset + wb_adr_i : in unsigned(2 downto 0); -- lower address bits + wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input + wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output + wb_we_i : in std_logic; -- Write enable input + wb_stb_i : in std_logic; -- Strobe signals / core select signal + wb_cyc_i : in std_logic; -- Valid bus cycle input + wb_ack_o : out std_logic; -- Bus cycle acknowledge output + wb_inta_o : out std_logic; -- interrupt request output signal + + -- i2c lines + scl_pad_i : in std_logic; -- i2c clock line input + scl_pad_o : out std_logic; -- i2c clock line output + scl_padoen_o : out std_logic; -- i2c clock line output enable, active low + sda_pad_i : in std_logic; -- i2c data line input + sda_pad_o : out std_logic; -- i2c data line output + sda_padoen_o : out std_logic -- i2c data line output enable, active low + ); + end component; -- i2c_master_top; + + -- Additional signals used to control I2C pins + signal s_scl_pad_i, s_scl_pad_o, s_scl_padoen_o : std_logic; + signal s_sda_pad_i, s_sda_pad_o, s_sda_padoen_o : std_logic; + -- Additional signals for WISHBONE interface + signal s_wb_clk_i, s_wb_rst_i, s_arst_i, s_wb_we_i, s_wb_stb_i, s_wb_cyc_i, s_wb_ack_o, s_wb_inta_o : std_logic; + signal s_wb_dat_i, s_wb_dat_o : std_logic_vector(7 downto 0); + signal s_wb_adr_i : unsigned(2 downto 0); + signal s_rd_nwr, s_cs : std_logic; + signal s_rd_nwr2, s_cs2 : std_logic; + --signal rst : std_logic; + + type stan_ci2c is (INIT, WR_WAIT_INIT, INIT1, WR_WAIT_INIT1, + INIT2, WR_WAIT_INIT2, INIT3, WR_WAIT_INIT3, + IDLE, WR_WAIT, WR_END, RD_WAIT, RD_END); + signal stan : stan_ci2c; +begin --i2c_master_top + + + c_i2c : i2c_master_top + generic map ( + ARST_LVL => '0') + port map ( + -- WISHBONE interface + wb_clk_i => s_wb_clk_i, + wb_rst_i => s_wb_rst_i, + arst_i => s_arst_i, + wb_we_i => s_wb_we_i, + wb_stb_i => s_wb_stb_i, + wb_cyc_i => s_wb_cyc_i, + wb_ack_o => s_wb_ack_o, + wb_inta_o => s_wb_inta_o, + wb_dat_i => s_wb_dat_i, + wb_dat_o => s_wb_dat_o, + wb_adr_i => s_wb_adr_i, + -- I2C interface + scl_pad_i => s_scl_pad_i, + scl_pad_o => s_scl_pad_o, + scl_padoen_o => s_scl_padoen_o, + sda_pad_i => s_sda_pad_i, + sda_pad_o => s_sda_pad_o, + sda_padoen_o => s_sda_padoen_o); + + -- Conversion WISHBON -> our standard + -- Output-> active '0', inactive '1' ('H') + s_scl_pad_i <= scl_i; + s_sda_pad_i <= sda_i; + --s_scl_pad_i <= '0' when (s_scl_pad_o = '0' and s_scl_padoen_o = '0') else '1'; + --s_sda_pad_i <= '0' when (s_sda_pad_o = '0' and s_sda_padoen_o = '0') else '1'; + scl_o <= '0' when (s_scl_pad_o = '0' and s_scl_padoen_o = '0') else '1'; + sda_o <= '0' when (s_sda_pad_o = '0' and s_sda_padoen_o = '0') else '1'; + + -- Timing conversion: CCU -> WISHBONE + s_wb_clk_i <= clk; + s_wb_rst_i <= '0'; + s_arst_i <= i2c_rst; + s_wb_adr_i <= unsigned(addr); + -- Write cycle + -- When we detect WR (nCS=0, RD_nWR=0 & proper address), we initialize + -- the WISHBONE write cycle + -- It is a sequential process, activated with clk signal + p1 : process (clk, rst) + begin -- process p1 + if rst = '0' then -- asynchronous reset (active low) + s_wb_cyc_i <= '0'; + s_wb_stb_i <= '0'; + stan <= IDLE; + s_cs <= '0'; + s_rd_nwr <= '0'; + s_cs2 <= '0'; + s_rd_nwr2 <= '0'; + elsif clk'event and clk = '1' then -- rising clock edge + s_cs2 <= cs; + s_rd_nwr2 <= rd_nwr; + s_cs <= s_cs2; + s_rd_nwr <= s_rd_nwr2; + case stan is + when IDLE => + s_wb_dat_i <= din; + -- detection of begining of the write cycle + if s_rd_nwr = '0' and s_cs = '1' then + -- Set the write signals and wait for write + s_wb_cyc_i <= '1'; + s_wb_stb_i <= '1'; + s_wb_we_i <= '1'; + stan <= WR_WAIT; + elsif s_rd_nwr = '1' and s_cs = '1' then + -- Set the read signals and wait for read + s_wb_cyc_i <= '1'; + s_wb_stb_i <= '1'; + s_wb_we_i <= '0'; + stan <= RD_WAIT; + end if; + when WR_WAIT => + -- wait for wb_ack_o = '1' + if s_wb_ack_o = '1' then + s_wb_cyc_i <= '0'; + s_wb_stb_i <= '0'; + s_wb_we_i <= '0'; + stan <= WR_END; + end if; + when WR_END => -- end of write cycle, wait for s_cs=0 + if s_cs = '0' then + stan <= IDLE; + end if; + when RD_WAIT => + -- read cycle, wait for wb_ack_o = '1' + if s_wb_ack_o = '1' then + s_wb_cyc_i <= '0'; + s_wb_stb_i <= '0'; + s_wb_we_i <= '0'; + dout <= s_wb_dat_o; + stan <= RD_END; + end if; + when RD_END => -- end of read cycle, wait for s_cs='0' + if s_cs = '0' then + stan <= IDLE; + end if; + when others => null; + end case; + end if; + end process p1; +end i2c_beh; Index: trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c/i2c_vio_ctrl_top.vhd =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c/i2c_vio_ctrl_top.vhd (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c/i2c_vio_ctrl_top.vhd (revision 37) @@ -0,0 +1,113 @@ +------------------------------------------------------------------------------- +-- Title : I2C controller driven by VIO objects +-- Project : +------------------------------------------------------------------------------- +-- File : i2c_vio_ctrl_top.vhd +-- Author : Wojciech M. Zabolotny wzab01gmail.com +-- License : PUBLIC DOMAIN +-- Company : +-- Created : 2015-05-03 +-- Last update: 2015-05-07 +-- Platform : +-- Standard : VHDL'93/02 +------------------------------------------------------------------------------- +-- Description: +------------------------------------------------------------------------------- +-- Copyright (c) 2015 +------------------------------------------------------------------------------- +-- Revisions : +-- Date Version Author Description +-- 2015-05-03 1.0 wzab Created +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity i2c_vio_ctrl is + + port ( + clk : in std_logic; + --rst_p : in std_logic; + scl : inout std_logic; + sda : inout std_logic); + +end entity i2c_vio_ctrl; + +architecture beh of i2c_vio_ctrl is + + signal din : std_logic_vector(7 downto 0); + signal dout : std_logic_vector(7 downto 0); + signal addr : std_logic_vector(2 downto 0); + signal rd_nwr : std_logic_vector(0 to 0); + signal cs : std_logic_vector(0 to 0); + signal vclk : std_logic; + signal i2c_rst_n : std_logic_vector(0 to 0); + signal vrst_n : std_logic_vector(0 to 0); + signal scl_i : std_logic; + signal scl_o : std_logic; + signal sda_i : std_logic; + signal sda_o : std_logic; + + component i2c_bus_wrap is + port ( + din : in std_logic_vector(7 downto 0); + dout : out std_logic_vector(7 downto 0); + addr : in std_logic_vector(2 downto 0); + rd_nwr : in std_logic; + cs : in std_logic; + clk : in std_logic; + rst : in std_logic; + scl_i : in std_logic; + scl_o : out std_logic; + sda_i : in std_logic; + sda_o : out std_logic); + end component i2c_bus_wrap; + + component vio_0 is + port ( + clk : in std_logic; + probe_in0 : in std_logic_vector (7 downto 0); + probe_out0 : out std_logic_vector (0 downto 0); + probe_out1 : out std_logic_vector (7 downto 0); + probe_out2 : out std_logic_vector (2 downto 0); + probe_out3 : out std_logic_vector (0 to 0); + probe_out4 : out std_logic_vector (0 to 0); + probe_out5 : out std_logic_vector (0 to 0)); + end component vio_0; + +begin -- architecture beh + + vio_0_1 : entity work.vio_0 + port map ( + clk => clk, + probe_in0 => dout, + probe_out0 => i2c_rst_n, + probe_out1 => din, + probe_out2 => addr, + probe_out3 => rd_nwr, + probe_out4 => cs, + probe_out5 => vrst_n); + + i2c_bus_wrap1 : entity work.i2c_bus_wrap + port map ( + din => din, + dout => dout, + addr => addr, + rd_nwr => rd_nwr(0), + cs => cs(0), + clk => vclk, + rst => vrst_n(0), + i2c_rst => i2c_rst_n(0), + scl_i => scl_i, + scl_o => scl_o, + sda_i => sda_i, + sda_o => sda_o); + + vclk <= clk; + scl_i <= scl; + sda_i <= sda; + scl <= '0' when scl_o = '0' else 'Z'; + sda <= '0' when sda_o = '0' else 'Z'; + +end architecture beh; + Index: trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c/i2c_master_top.vhd =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c/i2c_master_top.vhd (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c/i2c_master_top.vhd (revision 37) @@ -0,0 +1,360 @@ +--------------------------------------------------------------------- +---- ---- +---- WISHBONE revB2 compl. I2C Master Core; top level ---- +---- ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2000 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- CVS Log +-- +-- $Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $ +-- +-- $Date: 2009-01-20 10:38:45 $ +-- $Revision: 1.8 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- Revision 1.7 2004/03/14 10:17:03 rherveille +-- Fixed simulation issue when writing to CR register +-- +-- Revision 1.6 2003/08/09 07:01:13 rherveille +-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +-- Fixed a potential bug in the byte controller's host-acknowledge generation. +-- +-- Revision 1.5 2003/02/01 02:03:06 rherveille +-- Fixed a few 'arbitration lost' bugs. VHDL version only. +-- +-- Revision 1.4 2002/12/26 16:05:47 rherveille +-- Core is now a Multimaster I2C controller. +-- +-- Revision 1.3 2002/11/30 22:24:37 rherveille +-- Cleaned up code +-- +-- Revision 1.2 2001/11/10 10:52:44 rherveille +-- Changed PRER reset value from 0x0000 to 0xffff, conform specs. +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + + +entity i2c_master_top is + generic( + ARST_LVL : std_logic := '0' -- asynchronous reset level + ); + port ( + -- wishbone signals + wb_clk_i : in std_logic; -- master clock input + wb_rst_i : in std_logic := '0'; -- synchronous active high reset + arst_i : in std_logic := not ARST_LVL; -- asynchronous reset + wb_adr_i : in unsigned(2 downto 0); -- lower address bits + wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input + wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output + wb_we_i : in std_logic; -- Write enable input + wb_stb_i : in std_logic; -- Strobe signals / core select signal + wb_cyc_i : in std_logic; -- Valid bus cycle input + wb_ack_o : out std_logic; -- Bus cycle acknowledge output + wb_inta_o : out std_logic; -- interrupt request output signal + + -- i2c lines + scl_pad_i : in std_logic; -- i2c clock line input + scl_pad_o : out std_logic; -- i2c clock line output + scl_padoen_o : out std_logic; -- i2c clock line output enable, active low + sda_pad_i : in std_logic; -- i2c data line input + sda_pad_o : out std_logic; -- i2c data line output + sda_padoen_o : out std_logic -- i2c data line output enable, active low + ); +end entity i2c_master_top; + +architecture structural of i2c_master_top is + component i2c_master_byte_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) + nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- 4x SCL + + -- input signals + start, + stop, + read, + write, + ack_in : std_logic; + din : in std_logic_vector(7 downto 0); + + -- output signals + cmd_ack : out std_logic; + ack_out : out std_logic; + i2c_busy : out std_logic; + i2c_al : out std_logic; + dout : out std_logic_vector(7 downto 0); + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); + end component i2c_master_byte_ctrl; + + -- registers + signal prer : unsigned(15 downto 0); -- clock prescale register + signal ctr : std_logic_vector(7 downto 0); -- control register + signal txr : std_logic_vector(7 downto 0); -- transmit register + signal rxr : std_logic_vector(7 downto 0); -- receive register + signal cr : std_logic_vector(7 downto 0); -- command register + signal sr : std_logic_vector(7 downto 0); -- status register + + -- internal reset signal + signal rst_i : std_logic; + + -- wishbone write access + signal wb_wacc : std_logic; + + -- internal acknowledge signal + signal iack_o : std_logic; + + -- done signal: command completed, clear command register + signal done : std_logic; + + -- command register signals + signal sta, sto, rd, wr, ack, iack : std_logic; + + signal core_en : std_logic; -- core enable signal + signal ien : std_logic; -- interrupt enable signal + + -- status register signals + signal irxack, rxack : std_logic; -- received aknowledge from slave + signal tip : std_logic; -- transfer in progress + signal irq_flag : std_logic; -- interrupt pending flag + signal i2c_busy : std_logic; -- i2c bus busy (start signal detected) + signal i2c_al, al : std_logic; -- arbitration lost + +begin + -- generate internal reset signal + rst_i <= arst_i xor ARST_LVL; + + -- generate acknowledge output signal + gen_ack_o : process(wb_clk_i) + begin + if (wb_clk_i'event and wb_clk_i = '1') then + iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored + end if; + end process gen_ack_o; + wb_ack_o <= iack_o; + + -- generate wishbone write access signal + wb_wacc <= wb_we_i and iack_o; + + -- assign wb_dat_o + assign_dato : process(wb_clk_i) + begin + if (wb_clk_i'event and wb_clk_i = '1') then + case wb_adr_i is + when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0)); + when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8)); + when "010" => wb_dat_o <= ctr; + when "011" => wb_dat_o <= rxr; -- write is transmit register TxR + when "100" => wb_dat_o <= sr; -- write is command register CR + + -- Debugging registers: + -- These registers are not documented. + -- Functionality could change in future releases + when "101" => wb_dat_o <= txr; + when "110" => wb_dat_o <= cr; + when "111" => wb_dat_o <= (others => '0'); + when others => wb_dat_o <= (others => 'X'); -- for simulation only + end case; + end if; + end process assign_dato; + + + -- generate registers (CR, SR see below) + gen_regs: process(rst_i, wb_clk_i) + begin + if (rst_i = '0') then + prer <= (others => '1'); + ctr <= (others => '0'); + txr <= (others => '0'); + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + prer <= (others => '1'); + ctr <= (others => '0'); + txr <= (others => '0'); + elsif (wb_wacc = '1') then + case wb_adr_i is + when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i); + when "001" => prer(15 downto 8) <= unsigned(wb_dat_i); + when "010" => ctr <= wb_dat_i; + when "011" => txr <= wb_dat_i; + when "100" => null; --write to CR, avoid executing the others clause + + -- illegal cases, for simulation only + when others => + report ("Illegal write address, setting all registers to unknown."); + prer <= (others => 'X'); + ctr <= (others => 'X'); + txr <= (others => 'X'); + end case; + end if; + end if; + end process gen_regs; + + + -- generate command register + gen_cr: process(rst_i, wb_clk_i) + begin + if (rst_i = '0') then + cr <= (others => '0'); + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + cr <= (others => '0'); + elsif (wb_wacc = '1') then + if ( (core_en = '1') and (wb_adr_i = "100") ) then + -- only take new commands when i2c core enabled + -- pending commands are finished + cr <= wb_dat_i; + end if; + else + if (done = '1' or i2c_al = '1') then + cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost + end if; + + cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0' + cr(0) <= '0'; -- clear IRQ_ACK bit + end if; + end if; + end process gen_cr; + + -- decode command register + sta <= cr(7); + sto <= cr(6); + rd <= cr(5); + wr <= cr(4); + ack <= cr(3); + iack <= cr(0); + + -- decode control register + core_en <= ctr(7); + ien <= ctr(6); + + -- hookup byte controller block + byte_ctrl: i2c_master_byte_ctrl + port map ( + clk => wb_clk_i, + rst => wb_rst_i, + nReset => rst_i, + ena => core_en, + clk_cnt => prer, + start => sta, + stop => sto, + read => rd, + write => wr, + ack_in => ack, + i2c_busy => i2c_busy, + i2c_al => i2c_al, + din => txr, + cmd_ack => done, + ack_out => irxack, + dout => rxr, + scl_i => scl_pad_i, + scl_o => scl_pad_o, + scl_oen => scl_padoen_o, + sda_i => sda_pad_i, + sda_o => sda_pad_o, + sda_oen => sda_padoen_o + ); + + + -- status register block + interrupt request signal + st_irq_block : block + begin + -- generate status register bits + gen_sr_bits: process (wb_clk_i, rst_i) + begin + if (rst_i = '0') then + al <= '0'; + rxack <= '0'; + tip <= '0'; + irq_flag <= '0'; + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + al <= '0'; + rxack <= '0'; + tip <= '0'; + irq_flag <= '0'; + else + al <= i2c_al or (al and not sta); + rxack <= irxack; + tip <= (rd or wr); + + -- interrupt request flag is always generated + irq_flag <= (done or i2c_al or irq_flag) and not iack; + end if; + end if; + end process gen_sr_bits; + + -- generate interrupt request signals + gen_irq: process (wb_clk_i, rst_i) + begin + if (rst_i = '0') then + wb_inta_o <= '0'; + elsif (wb_clk_i'event and wb_clk_i = '1') then + if (wb_rst_i = '1') then + wb_inta_o <= '0'; + else + -- interrupt signal is only generated when IEN (interrupt enable bit) is set + wb_inta_o <= irq_flag and ien; + end if; + end if; + end process gen_irq; + + -- assign status register bits + sr(7) <= rxack; + sr(6) <= i2c_busy; + sr(5) <= al; + sr(4 downto 2) <= (others => '0'); -- reserved + sr(1) <= tip; + sr(0) <= irq_flag; + end block; + +end architecture structural; Index: trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c/i2c_master_bit_ctrl.vhd =================================================================== --- trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c/i2c_master_bit_ctrl.vhd (nonexistent) +++ trunk/experimental_jumbo_frames_version/fpga/src/AFCK/i2c/i2c_master_bit_ctrl.vhd (revision 37) @@ -0,0 +1,576 @@ +--------------------------------------------------------------------- +---- ---- +---- WISHBONE revB2 I2C Master Core; bit-controller ---- +---- ---- +---- ---- +---- Author: Richard Herveille ---- +---- richard@asics.ws ---- +---- www.asics.ws ---- +---- ---- +---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- +---- ---- +--------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2000 Richard Herveille ---- +---- richard@asics.ws ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer.---- +---- ---- +---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- +---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- +---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- +---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- +---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- +---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- +---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- +---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- +---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- +---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- +---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- +---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- +---- POSSIBILITY OF SUCH DAMAGE. ---- +---- ---- +--------------------------------------------------------------------- + +-- CVS Log +-- +-- $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $ +-- +-- $Date: 2009-02-04 20:17:34 $ +-- $Revision: 1.17 $ +-- $Author: rherveille $ +-- $Locker: $ +-- $State: Exp $ +-- +-- Change History: +-- $Log: not supported by cvs2svn $ +-- Revision 1.16 2009/01/20 20:40:36 rherveille +-- Fixed type iscl_oen instead of scl_oen +-- +-- Revision 1.15 2009/01/20 10:34:51 rherveille +-- Added SCL clock synchronization logic +-- Fixed slave_wait signal generation +-- +-- Revision 1.14 2006/10/11 12:10:13 rherveille +-- Added missing semicolons ';' on endif +-- +-- Revision 1.13 2006/10/06 10:48:24 rherveille +-- fixed short scl high pulse after clock stretch +-- +-- Revision 1.12 2004/05/07 11:53:31 rherveille +-- Fixed previous fix :) Made a variable vs signal mistake. +-- +-- Revision 1.11 2004/05/07 11:04:00 rherveille +-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. +-- +-- Revision 1.10 2004/02/27 07:49:43 rherveille +-- Fixed a bug in the arbitration-lost signal generation. VHDL version only. +-- +-- Revision 1.9 2003/08/12 14:48:37 rherveille +-- Forgot an 'end if' :-/ +-- +-- Revision 1.8 2003/08/09 07:01:13 rherveille +-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. +-- Fixed a potential bug in the byte controller's host-acknowledge generation. +-- +-- Revision 1.7 2003/02/05 00:06:02 rherveille +-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. +-- +-- Revision 1.6 2003/02/01 02:03:06 rherveille +-- Fixed a few 'arbitration lost' bugs. VHDL version only. +-- +-- Revision 1.5 2002/12/26 16:05:47 rherveille +-- Core is now a Multimaster I2C controller. +-- +-- Revision 1.4 2002/11/30 22:24:37 rherveille +-- Cleaned up code +-- +-- Revision 1.3 2002/10/30 18:09:53 rherveille +-- Fixed some reported minor start/stop generation timing issuess. +-- +-- Revision 1.2 2002/06/15 07:37:04 rherveille +-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. +-- +-- Revision 1.1 2001/11/05 12:02:33 rherveille +-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. +-- Code updated, is now up-to-date to doc. rev.0.4. +-- Added headers. +-- + + +-- +------------------------------------- +-- Bit controller section +------------------------------------ +-- +-- Translate simple commands into SCL/SDA transitions +-- Each command has 5 states, A/B/C/D/idle +-- +-- start: SCL ~~~~~~~~~~~~~~\____ +-- SDA XX/~~~~~~~\______ +-- x | A | B | C | D | i +-- +-- repstart SCL ______/~~~~~~~\___ +-- SDA __/~~~~~~~\______ +-- x | A | B | C | D | i +-- +-- stop SCL _______/~~~~~~~~~~~ +-- SDA ==\___________/~~~~~ +-- x | A | B | C | D | i +-- +--- write SCL ______/~~~~~~~\____ +-- SDA XXX===============XX +-- x | A | B | C | D | i +-- +--- read SCL ______/~~~~~~~\____ +-- SDA XXXXXXX=XXXXXXXXXXX +-- x | A | B | C | D | i +-- + +-- Timing: Normal mode Fast mode +----------------------------------------------------------------- +-- Fscl 100KHz 400KHz +-- Th_scl 4.0us 0.6us High period of SCL +-- Tl_scl 4.7us 1.3us Low period of SCL +-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition +-- Tsu:sto 4.0us 0.6us setup time for a stop conditon +-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2c_master_bit_ctrl is + port ( + clk : in std_logic; + rst : in std_logic; + nReset : in std_logic; + ena : in std_logic; -- core enable signal + + clk_cnt : in unsigned(15 downto 0); -- clock prescale value + + cmd : in std_logic_vector(3 downto 0); + cmd_ack : out std_logic; -- command completed + busy : out std_logic; -- i2c bus busy + al : out std_logic; -- arbitration lost + + din : in std_logic; + dout : out std_logic; + + -- i2c lines + scl_i : in std_logic; -- i2c clock line input + scl_o : out std_logic; -- i2c clock line output + scl_oen : out std_logic; -- i2c clock line output enable, active low + sda_i : in std_logic; -- i2c data line input + sda_o : out std_logic; -- i2c data line output + sda_oen : out std_logic -- i2c data line output enable, active low + ); +end entity i2c_master_bit_ctrl; + +architecture structural of i2c_master_bit_ctrl is + constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; + constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; + constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; + constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; + constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; + + type states is (idle, start_a, start_b, start_c, start_d, start_e, + stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); + signal c_state : states; + + signal iscl_oen, isda_oen : std_logic; -- internal I2C lines + signal sda_chk : std_logic; -- check SDA status (multi-master arbitration) + signal dscl_oen : std_logic; -- delayed scl_oen signals + signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs + signal dSCL, dSDA : std_logic; -- delayed versions ofsSCL and sSDA + signal clk_en : std_logic; -- statemachine clock enable + signal scl_sync, slave_wait : std_logic; -- clock generation signals + signal ial : std_logic; -- internal arbitration lost signal + signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis) + +begin + -- whenever the slave is not ready it can delay the cycle by pulling SCL low + -- delay scl_oen + process (clk, nReset) + begin + if (nReset = '0') then + dscl_oen <= '0'; + elsif (clk'event and clk = '1') then + dscl_oen <= iscl_oen; + end if; + end process; + + -- slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low + -- slave_wait remains asserted until the slave releases SCL + process (clk, nReset) + begin + if (nReset = '0') then + slave_wait <= '0'; + elsif (clk'event and clk = '1') then + slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL); + end if; + end process; + + -- master drives SCL high, but another master pulls it low + -- master start counting down its low cycle now (clock synchronization) + scl_sync <= dSCL and not sSCL and iscl_oen; + + -- generate clk enable signal + gen_clken: process(clk, nReset) + begin + if (nReset = '0') then + cnt <= (others => '0'); + clk_en <= '1'; + elsif (clk'event and clk = '1') then + if ((rst = '1') or (cnt = 0) or (ena = '0') or (scl_sync = '1')) then + cnt <= clk_cnt; + clk_en <= '1'; + elsif (slave_wait = '1') then + cnt <= cnt; + clk_en <= '0'; + else + cnt <= cnt -1; + clk_en <= '0'; + end if; + end if; + end process gen_clken; + + + -- generate bus status controller + bus_status_ctrl: block + signal cSCL, cSDA : std_logic_vector( 1 downto 0); -- capture SDA and SCL + signal fSCL, fSDA : std_logic_vector( 2 downto 0); -- filter inputs for SCL and SDA + signal filter_cnt : unsigned(13 downto 0); -- clock divider for filter + signal sta_condition : std_logic; -- start detected + signal sto_condition : std_logic; -- stop detected + signal cmd_stop : std_logic; -- STOP command + signal ibusy : std_logic; -- internal busy signal + begin + -- capture SCL and SDA + capture_scl_sda: process(clk, nReset) + begin + if (nReset = '0') then + cSCL <= "00"; + cSDA <= "00"; + elsif (clk'event and clk = '1') then + if (rst = '1') then + cSCL <= "00"; + cSDA <= "00"; + else + cSCL <= (cSCL(0) & scl_i); + cSDA <= (cSDA(0) & sda_i); + end if; + end if; + end process capture_scl_sda; + + -- filter SCL and SDA; (attempt to) remove glitches + filter_divider: process(clk, nReset) + begin + if (nReset = '0') then + filter_cnt <= (others => '0'); + elsif (clk'event and clk = '1') then + if ( (rst = '1') or (ena = '0') ) then + filter_cnt <= (others => '0'); + elsif (filter_cnt = 0) then + filter_cnt <= clk_cnt(15 downto 2); + else + filter_cnt <= filter_cnt -1; + end if; + end if; + end process filter_divider; + + filter_scl_sda: process(clk, nReset) + begin + if (nReset = '0') then + fSCL <= (others => '1'); + fSDA <= (others => '1'); + elsif (clk'event and clk = '1') then + if (rst = '1') then + fSCL <= (others => '1'); + fSDA <= (others => '1'); + elsif (filter_cnt = 0) then + fSCL <= (fSCL(1 downto 0) & cSCL(1)); + fSDA <= (fSDA(1 downto 0) & cSDA(1)); + end if; + end if; + end process filter_scl_sda; + + -- generate filtered SCL and SDA signals + scl_sda: process(clk, nReset) + begin + if (nReset = '0') then + sSCL <= '1'; + sSDA <= '1'; + + dSCL <= '1'; + dSDA <= '1'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + sSCL <= '1'; + sSDA <= '1'; + + dSCL <= '1'; + dSDA <= '1'; + else + sSCL <= (fSCL(2) and fSCL(1)) or + (fSCL(2) and fSCL(0)) or + (fSCL(1) and fSCL(0)); + sSDA <= (fSDA(2) and fSDA(1)) or + (fSDA(2) and fSDA(0)) or + (fSDA(1) and fSDA(0)); + + dSCL <= sSCL; + dSDA <= sSDA; + end if; + end if; + end process scl_sda; + + + -- detect start condition => detect falling edge on SDA while SCL is high + -- detect stop condition => detect rising edge on SDA while SCL is high + detect_sta_sto: process(clk, nReset) + begin + if (nReset = '0') then + sta_condition <= '0'; + sto_condition <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + sta_condition <= '0'; + sto_condition <= '0'; + else + sta_condition <= (not sSDA and dSDA) and sSCL; + sto_condition <= (sSDA and not dSDA) and sSCL; + end if; + end if; + end process detect_sta_sto; + + + -- generate i2c-bus busy signal + gen_busy: process(clk, nReset) + begin + if (nReset = '0') then + ibusy <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + ibusy <= '0'; + else + ibusy <= (sta_condition or ibusy) and not sto_condition; + end if; + end if; + end process gen_busy; + busy <= ibusy; + + + -- generate arbitration lost signal + -- aribitration lost when: + -- 1) master drives SDA high, but the i2c bus is low + -- 2) stop detected while not requested (detect during 'idle' state) + gen_al: process(clk, nReset) + begin + if (nReset = '0') then + cmd_stop <= '0'; + ial <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1') then + cmd_stop <= '0'; + ial <= '0'; + else + if (clk_en = '1') then + if (cmd = I2C_CMD_STOP) then + cmd_stop <= '1'; + else + cmd_stop <= '0'; + end if; + end if; + + if (c_state = idle) then + ial <= (sda_chk and not sSDA and isda_oen and sSCL ) or (sto_condition and not cmd_stop); + else + ial <= (sda_chk and not sSDA and isda_oen and sSCL ); + end if; + end if; + end if; + end process gen_al; + al <= ial; + + + -- generate dout signal, store dout on rising edge of SCL + gen_dout: process(clk, nReset) + begin + if (nReset = '0') then + dout <= '0'; + elsif (clk'event and clk = '1') then + if (sSCL = '1' and dSCL = '0') then + dout <= sSDA; + end if; + end if; + end process gen_dout; + end block bus_status_ctrl; + + + -- generate statemachine + nxt_state_decoder : process (clk, nReset) + begin + if (nReset = '0') then + c_state <= idle; + cmd_ack <= '0'; + iscl_oen <= '1'; + isda_oen <= '1'; + sda_chk <= '0'; + elsif (clk'event and clk = '1') then + if (rst = '1' or ial = '1') then + c_state <= idle; + cmd_ack <= '0'; + iscl_oen <= '1'; + isda_oen <= '1'; + sda_chk <= '0'; + else + cmd_ack <= '0'; -- default no acknowledge + + if (clk_en = '1') then + case (c_state) is + -- idle + when idle => + case cmd is + when I2C_CMD_START => c_state <= start_a; + when I2C_CMD_STOP => c_state <= stop_a; + when I2C_CMD_WRITE => c_state <= wr_a; + when I2C_CMD_READ => c_state <= rd_a; + when others => c_state <= idle; -- NOP command + end case; + + iscl_oen <= iscl_oen; -- keep SCL in same state + isda_oen <= isda_oen; -- keep SDA in same state + sda_chk <= '0'; -- don't check SDA + + -- start + when start_a => + c_state <= start_b; + iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start) + isda_oen <= '1'; -- set SDA high + sda_chk <= '0'; -- don't check SDA + + when start_b => + c_state <= start_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= '1'; -- keep SDA high + sda_chk <= '0'; -- don't check SDA + + when start_c => + c_state <= start_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '0'; -- set SDA low + sda_chk <= '0'; -- don't check SDA + + when start_d => + c_state <= start_e; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + when start_e => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '0'; -- set SCL low + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + -- stop + when stop_a => + c_state <= stop_b; + iscl_oen <= '0'; -- keep SCL low + isda_oen <= '0'; -- set SDA low + sda_chk <= '0'; -- don't check SDA + + when stop_b => + c_state <= stop_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + when stop_c => + c_state <= stop_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '0'; -- keep SDA low + sda_chk <= '0'; -- don't check SDA + + when stop_d => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '1'; -- set SDA high + sda_chk <= '0'; -- don't check SDA + + -- read + when rd_a => + c_state <= rd_b; + iscl_oen <= '0'; -- keep SCL low + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + when rd_b => + c_state <= rd_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + when rd_c => + c_state <= rd_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + when rd_d => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '0'; -- set SCL low + isda_oen <= '1'; -- tri-state SDA + sda_chk <= '0'; -- don't check SDA + + -- write + when wr_a => + c_state <= wr_b; + iscl_oen <= '0'; -- keep SCL low + isda_oen <= din; -- set SDA + sda_chk <= '0'; -- don't check SDA (SCL low) + + when wr_b => + c_state <= wr_c; + iscl_oen <= '1'; -- set SCL high + isda_oen <= din; -- keep SDA + sda_chk <= '0'; -- don't check SDA yet + -- Allow some more time for SDA and SCL to settle + + when wr_c => + c_state <= wr_d; + iscl_oen <= '1'; -- keep SCL high + isda_oen <= din; -- keep SDA + sda_chk <= '1'; -- check SDA + + when wr_d => + c_state <= idle; + cmd_ack <= '1'; -- command completed + iscl_oen <= '0'; -- set SCL low + isda_oen <= din; -- keep SDA + sda_chk <= '0'; -- don't check SDA (SCL low) + + when others => + + end case; + end if; + end if; + end if; + end process nxt_state_decoder; + + + -- assign outputs + scl_o <= '0'; + scl_oen <= iscl_oen; + sda_o <= '0'; + sda_oen <= isda_oen; +end architecture structural; +