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https://opencores.org/ocsvn/forwardcom/forwardcom/trunk
Subversion Repositories forwardcom
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/forwardcom/trunk/bitstream_settings_a.xdc
0,0 → 1,57
# ForwardCom soft core |
# Constraints for Nexys Artix-7 100T board |
# Agner Fog 2021-07-31 |
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set_property CONFIG_VOLTAGE 3.3 [current_design] |
set_property CFGBVS VCCO [current_design] |
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# Board input clock 100 MHz (this affects simulation only) |
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports clock100] |
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clock100] |
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# Make data ram use block ram |
# set_property RAM_STYLE BLOCK [get_cells -hierarchical dataram*] |
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# I have problems finding out what to write here to get rid of timing warnings |
# for inputs and outputs. Feel free to change it or remove it. |
#set_input_delay -clock [get_clocks sys_clk_pin] 0.000 [get_ports resetButton] |
#set_input_delay -clock [get_clocks sys_clk_pin] -min -add_delay 0.000 [get_ports resetButton] |
#set_input_delay -clock [get_clocks sys_clk_pin] -max -add_delay 0.000 [get_ports resetButton] |
#set_input_delay -clock [get_clocks sys_clk_pin] 0.000 [get_ports resetButtonD] |
#set_input_delay -clock [get_clocks sys_clk_pin] 0.000 [get_ports stepButton] |
#set_input_delay -clock [get_clocks sys_clk_pin] 0.000 [get_ports stepButtonD] |
#set_input_delay -clock [get_clocks sys_clk_pin] 0.000 [get_ports switch0] |
#set_input_delay -clock [get_clocks sys_clk_pin] 0.000 [get_ports switch1] |
#set_input_delay -clock [get_clocks sys_clk_pin] 0.000 [get_ports switch14] |
#set_input_delay -clock [get_clocks sys_clk_pin] 0.000 [get_ports switch15] |
#set_input_delay -clock [get_clocks sys_clk_pin] 0.000 [get_ports switch2] |
#set_input_delay -clock [get_clocks sys_clk_pin] 0.000 [get_ports switch3] |
#set_input_delay -clock [get_clocks sys_clk_pin] 0.000 [get_ports switch4] |
# |
## "-min" = hold time, "-max" = setup time |
#set_output_delay -clock [get_clocks sys_clk_pin] -min -1.000 [get_ports {digit7seg[*]}] |
#set_output_delay -clock [get_clocks sys_clk_pin] -max -4.000 [get_ports {digit7seg[*]}] |
#set_output_delay -clock [get_clocks sys_clk_pin] -min -1.000 [get_ports {segment7seg[*]}] |
#set_output_delay -clock [get_clocks sys_clk_pin] -max -4.000 [get_ports {segment7seg[*]}] |
##set_output_delay -clock [get_clocks sys_clk_pin] -max -add_delay 5.000 [get_ports {digit7seg[*]}] |
#set_output_delay -clock [get_clocks sys_clk_pin] -min -1.000 [get_ports led0] |
#set_output_delay -clock [get_clocks sys_clk_pin] -max -4.000 [get_ports led0] |
#set_output_delay -clock [get_clocks sys_clk_pin] -min -1.000 [get_ports led1] |
#set_output_delay -clock [get_clocks sys_clk_pin] -max -4.000 [get_ports led1] |
#set_output_delay -clock [get_clocks sys_clk_pin] -min -1.000 [get_ports led2] |
#set_output_delay -clock [get_clocks sys_clk_pin] -max -4.000 [get_ports led2] |
#set_output_delay -clock [get_clocks sys_clk_pin] -min -2.000 [get_ports led12] |
#set_output_delay -clock [get_clocks sys_clk_pin] -max -4.000 [get_ports led12] |
#set_output_delay -clock [get_clocks sys_clk_pin] -min -2.000 [get_ports led13] |
#set_output_delay -clock [get_clocks sys_clk_pin] -max -4.000 [get_ports led13] |
#set_output_delay -clock [get_clocks sys_clk_pin] -min -2.000 [get_ports led15] |
#set_output_delay -clock [get_clocks sys_clk_pin] -max -4.000 [get_ports led15] |
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#set_switching_activity -toggle_rate 0.010 -static_probability 0.100 [get_nets {register_file_inst/genblk1[0].registers[0][63]_i_1_n_0}] |
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# generated by constraints wizard: |
set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks clock100] -group [get_clocks -include_generated_clocks sys_clk_pin] |
set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks clkfbout_clock_generator] -group [get_clocks -include_generated_clocks clkfbout_clock_generator_1] |
set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks clk_out_clock_generator] -group [get_clocks -include_generated_clocks clk_out_clock_generator_1] |