URL
https://opencores.org/ocsvn/fpga-median/fpga-median/trunk
Subversion Repositories fpga-median
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- This comparison shows the changes necessary to convert path
/fpga-median
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/trunk/rtl/median.v
1,20 → 1,36
// +---------------------------------------------------------------------------- |
// Universidade Federal da Bahia |
//------------------------------------------------------------------------------ |
// PROJECT: FPGA Median Filter |
//------------------------------------------------------------------------------ |
// FILE NAME : median.v |
// AUTHOR : João Carlos Bittencourt |
// AUTHOR'S E-MAIL : joaocarlos@ieee.org |
// ----------------------------------------------------------------------------- |
// RELEASE HISTORY |
// VERSION DATE AUTHOR DESCRIPTION |
// 1.0 2013-08-13 joao.nunes initial version |
// ----------------------------------------------------------------------------- |
// KEYWORDS: median, filter, image processing |
// ----------------------------------------------------------------------------- |
// PURPOSE: Top level entity of the Median Filter algorithm datapath. |
// ----------------------------------------------------------------------------- |
/* -------------------------------------------------------------------------------- |
This file is part of FPGA Median Filter. |
|
FPGA Median Filter is free software: you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation, either version 3 of the License, or |
(at your option) any later version. |
|
FPGA Median Filter is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>. |
-------------------------------------------------------------------------------- */ |
/* +---------------------------------------------------------------------------- |
Universidade Federal da Bahia |
------------------------------------------------------------------------------ |
PROJECT: FPGA Median Filter |
------------------------------------------------------------------------------ |
FILE NAME : median.v |
AUTHOR : João Carlos Bittencourt |
AUTHOR'S E-MAIL : joaocarlos@ieee.org |
----------------------------------------------------------------------------- |
RELEASE HISTORY |
VERSION DATE AUTHOR DESCRIPTION |
1.0 2013-08-13 joao.nunes initial version |
----------------------------------------------------------------------------- |
KEYWORDS: median, filter, image processing |
----------------------------------------------------------------------------- |
PURPOSE: Top level entity of the Median Filter algorithm datapath. |
----------------------------------------------------------------------------- */ |
`define DEBUG |
|
module median |
/trunk/rtl/dff_3_pipe.v
1,20 → 1,36
// +---------------------------------------------------------------------------- |
// Universidade Federal da Bahia |
//------------------------------------------------------------------------------ |
// PROJECT: FPGA Median Filter |
//------------------------------------------------------------------------------ |
// FILE NAME : pixel_network.v |
// AUTHOR : João Carlos Bittencourt |
// AUTHOR'S E-MAIL : joaocarlos@ieee.org |
// ----------------------------------------------------------------------------- |
// RELEASE HISTORY |
// VERSION DATE AUTHOR DESCRIPTION |
// 1.0 2013-08-13 joao.nunes initial version |
// ----------------------------------------------------------------------------- |
// KEYWORDS: dff, flip-flop, register bank |
// ----------------------------------------------------------------------------- |
// PURPOSE: Group median pipeline registers. |
// ----------------------------------------------------------------------------- |
/* -------------------------------------------------------------------------------- |
This file is part of FPGA Median Filter. |
|
FPGA Median Filter is free software: you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation, either version 3 of the License, or |
(at your option) any later version. |
|
FPGA Median Filter is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>. |
-------------------------------------------------------------------------------- */ |
/* +---------------------------------------------------------------------------- |
Universidade Federal da Bahia |
------------------------------------------------------------------------------ |
PROJECT: FPGA Median Filter |
------------------------------------------------------------------------------ |
FILE NAME : pixel_network.v |
AUTHOR : João Carlos Bittencourt |
AUTHOR'S E-MAIL : joaocarlos@ieee.org |
----------------------------------------------------------------------------- |
RELEASE HISTORY |
VERSION DATE AUTHOR DESCRIPTION |
1.0 2013-08-13 joao.nunes initial version |
----------------------------------------------------------------------------- |
KEYWORDS: dff, flip-flop, register bank |
----------------------------------------------------------------------------- |
PURPOSE: Group median pipeline registers. |
----------------------------------------------------------------------------- */ |
module dff_3_pipe |
#( |
parameter DATA_WIDTH = 8 |
/trunk/rtl/common_network.v
1,20 → 1,37
// +---------------------------------------------------------------------------- |
// Universidade Federal da Bahia |
//------------------------------------------------------------------------------ |
// PROJECT: FPGA Median Filter |
//------------------------------------------------------------------------------ |
// FILE NAME : pixel_network.v |
// AUTHOR : João Carlos Bittencourt |
// AUTHOR'S E-MAIL : joaocarlos@ieee.org |
// ----------------------------------------------------------------------------- |
// RELEASE HISTORY |
// VERSION DATE AUTHOR DESCRIPTION |
// 1.0 2013-08-13 joao.nunes initial version |
// ----------------------------------------------------------------------------- |
// KEYWORDS: comparator, low, high, median |
// ----------------------------------------------------------------------------- |
// PURPOSE: Obtain the Median of a 3x3 mask. |
// ----------------------------------------------------------------------------- |
/* -------------------------------------------------------------------------------- |
This file is part of FPGA Median Filter. |
|
FPGA Median Filter is free software: you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation, either version 3 of the License, or |
(at your option) any later version. |
|
FPGA Median Filter is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>. |
-------------------------------------------------------------------------------- */ |
|
/* +---------------------------------------------------------------------------- |
Universidade Federal da Bahia |
------------------------------------------------------------------------------ |
PROJECT: FPGA Median Filter |
------------------------------------------------------------------------------ |
FILE NAME : pixel_network.v |
AUTHOR : João Carlos Bittencourt |
AUTHOR'S E-MAIL : joaocarlos@ieee.org |
----------------------------------------------------------------------------- |
RELEASE HISTORY |
VERSION DATE AUTHOR DESCRIPTION |
1.0 2013-08-13 joao.nunes initial version |
----------------------------------------------------------------------------- |
KEYWORDS: comparator, low, high, median |
----------------------------------------------------------------------------- |
PURPOSE: Obtain the Median of a 3x3 mask. |
----------------------------------------------------------------------------- */ |
module common_network |
#( |
parameter DATA_WIDTH = 8 |
/trunk/rtl/state_machine.v
1,21 → 1,37
// +---------------------------------------------------------------------------- |
// Universidade Federal da Bahia |
//------------------------------------------------------------------------------ |
// PROJECT: FPGA Median Filter |
//------------------------------------------------------------------------------ |
// FILE NAME : median.v |
// AUTHOR : Joo Carlos Bittencourt |
// AUTHOR'S E-MAIL : joaocarlos@ieee.org |
// ----------------------------------------------------------------------------- |
// RELEASE HISTORY |
// VERSION DATE AUTHOR DESCRIPTION |
// 1.0 2013-08-13 joao.nunes initial version |
// 2.0 2013-09-06 laur.rami fix minnor issues on memory address |
// ----------------------------------------------------------------------------- |
// KEYWORDS: median, filter, image processing, state machine |
// ----------------------------------------------------------------------------- |
// PURPOSE: Windowing Memory Address Controller. |
// ----------------------------------------------------------------------------- |
/* -------------------------------------------------------------------------------- |
This file is part of FPGA Median Filter. |
|
FPGA Median Filter is free software: you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation, either version 3 of the License, or |
(at your option) any later version. |
|
FPGA Median Filter is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>. |
-------------------------------------------------------------------------------- */ |
/* +---------------------------------------------------------------------------- |
Universidade Federal da Bahia |
------------------------------------------------------------------------------ |
PROJECT: FPGA Median Filter |
------------------------------------------------------------------------------ |
FILE NAME : median.v |
AUTHOR : Joo Carlos Bittencourt |
AUTHOR'S E-MAIL : joaocarlos@ieee.org |
----------------------------------------------------------------------------- |
RELEASE HISTORY |
VERSION DATE AUTHOR DESCRIPTION |
1.0 2013-08-13 joao.nunes initial version |
2.0 2013-09-06 laur.rami fix minnor issues on memory address |
----------------------------------------------------------------------------- |
KEYWORDS: median, filter, image processing, state machine |
----------------------------------------------------------------------------- |
PURPOSE: Windowing Memory Address Controller. |
----------------------------------------------------------------------------- */ |
module state_machine |
#( |
parameter LUT_ADDR_WIDTH = 10, |
/trunk/rtl/node.v
1,20 → 1,36
// +---------------------------------------------------------------------------- |
// Universidade Federal da Bahia |
//------------------------------------------------------------------------------ |
// PROJECT: FPGA Median Filter |
//------------------------------------------------------------------------------ |
// FILE NAME : node.v |
// AUTHOR : João Carlos Bittencourt |
// AUTHOR'S E-MAIL : joaocarlos@ieee.org |
// ----------------------------------------------------------------------------- |
// RELEASE HISTORY |
// VERSION DATE AUTHOR DESCRIPTION |
// 1.0 2013-08-13 joao.nunes initial version |
// ----------------------------------------------------------------------------- |
// KEYWORDS: comparator, low, hight, median |
// ----------------------------------------------------------------------------- |
// PURPOSE: Compare two input values and return the low and high values. |
// ----------------------------------------------------------------------------- |
/* -------------------------------------------------------------------------------- |
This file is part of FPGA Median Filter. |
|
FPGA Median Filter is free software: you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation, either version 3 of the License, or |
(at your option) any later version. |
|
FPGA Median Filter is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>. |
-------------------------------------------------------------------------------- */ |
/* +---------------------------------------------------------------------------- |
Universidade Federal da Bahia |
------------------------------------------------------------------------------ |
PROJECT: FPGA Median Filter |
------------------------------------------------------------------------------ |
FILE NAME : node.v |
AUTHOR : João Carlos Bittencourt |
AUTHOR'S E-MAIL : joaocarlos@ieee.org |
----------------------------------------------------------------------------- |
RELEASE HISTORY |
VERSION DATE AUTHOR DESCRIPTION |
1.0 2013-08-13 joao.nunes initial version |
----------------------------------------------------------------------------- |
KEYWORDS: comparator, low, hight, median |
----------------------------------------------------------------------------- |
PURPOSE: Compare two input values and return the low and high values. |
----------------------------------------------------------------------------- */ |
module node |
#( |
parameter DATA_WIDTH = 8, |
/trunk/rtl/dual_port_ram.v
1,3 → 1,19
/* -------------------------------------------------------------------------------- |
This file is part of FPGA Median Filter. |
|
FPGA Median Filter is free software: you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation, either version 3 of the License, or |
(at your option) any later version. |
|
FPGA Median Filter is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>. |
-------------------------------------------------------------------------------- */ |
//*******************************************************************// |
//-------------------------------------------------------------------// |
// File name : dual_port_ram.v |
/trunk/rtl/pixel_network.v
1,20 → 1,36
// +---------------------------------------------------------------------------- |
// Universidade Federal da Bahia |
//------------------------------------------------------------------------------ |
// PROJECT: FPGA Median Filter |
//------------------------------------------------------------------------------ |
// FILE NAME : pixel_network.v |
// AUTHOR : João Carlos Bittencourt |
// AUTHOR'S E-MAIL : joaocarlos@ieee.org |
// ----------------------------------------------------------------------------- |
// RELEASE HISTORY |
// VERSION DATE AUTHOR DESCRIPTION |
// 1.0 2013-08-13 joao.nunes initial version |
// ----------------------------------------------------------------------------- |
// KEYWORDS: comparator, low, hight, median |
// ----------------------------------------------------------------------------- |
// PURPOSE: Obtain the Median of a 3x3 mask. |
// ----------------------------------------------------------------------------- |
/* -------------------------------------------------------------------------------- |
This file is part of FPGA Median Filter. |
|
FPGA Median Filter is free software: you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation, either version 3 of the License, or |
(at your option) any later version. |
|
FPGA Median Filter is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>. |
-------------------------------------------------------------------------------- */ |
/* +---------------------------------------------------------------------------- |
Universidade Federal da Bahia |
------------------------------------------------------------------------------ |
PROJECT: FPGA Median Filter |
------------------------------------------------------------------------------ |
FILE NAME : pixel_network.v |
AUTHOR : João Carlos Bittencourt |
AUTHOR'S E-MAIL : joaocarlos@ieee.org |
----------------------------------------------------------------------------- |
RELEASE HISTORY |
VERSION DATE AUTHOR DESCRIPTION |
1.0 2013-08-13 joao.nunes initial version |
----------------------------------------------------------------------------- |
KEYWORDS: comparator, low, hight, median |
----------------------------------------------------------------------------- |
PURPOSE: Obtain the Median of a 3x3 mask. |
----------------------------------------------------------------------------- */ |
module pixel_network |
#( |
parameter DATA_WIDTH = 8 |
/trunk/sim/tb/dut_if.sv
1,3 → 1,19
/* -------------------------------------------------------------------------------- |
This file is part of FPGA Median Filter. |
|
FPGA Median Filter is free software: you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation, either version 3 of the License, or |
(at your option) any later version. |
|
FPGA Median Filter is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>. |
-------------------------------------------------------------------------------- */ |
// +---------------------------------------------------------------------------- |
// Universidade Federal da Bahia |
//------------------------------------------------------------------------------ |
/trunk/sim/tb/driver.sv
1,3 → 1,19
/* -------------------------------------------------------------------------------- |
This file is part of FPGA Median Filter. |
|
FPGA Median Filter is free software: you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation, either version 3 of the License, or |
(at your option) any later version. |
|
FPGA Median Filter is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>. |
-------------------------------------------------------------------------------- */ |
// +---------------------------------------------------------------------------- |
// Universidade Federal da Bahia |
//------------------------------------------------------------------------------ |
/trunk/sim/tb/median_tb.v
1,3 → 1,19
/* -------------------------------------------------------------------------------- |
This file is part of FPGA Median Filter. |
|
FPGA Median Filter is free software: you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation, either version 3 of the License, or |
(at your option) any later version. |
|
FPGA Median Filter is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>. |
-------------------------------------------------------------------------------- */ |
// +---------------------------------------------------------------------------- |
// Universidade Federal da Bahia |
//------------------------------------------------------------------------------ |
/trunk/sim/tb/median_tb_directed.sv
1,3 → 1,19
/* -------------------------------------------------------------------------------- |
This file is part of FPGA Median Filter. |
|
FPGA Median Filter is free software: you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation, either version 3 of the License, or |
(at your option) any later version. |
|
FPGA Median Filter is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>. |
-------------------------------------------------------------------------------- */ |
// +---------------------------------------------------------------------------- |
// Universidade Federal da Bahia |
//------------------------------------------------------------------------------ |