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URL https://opencores.org/ocsvn/fpuvhdl/fpuvhdl/trunk

Subversion Repositories fpuvhdl

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  • This comparison shows the changes necessary to convert path 
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    from Rev 3 to Rev 4
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Rev 3 → Rev 4

/trunk/fpuvhdl/adder/fpadd_normalize_struct.vhd
1,4 → 1,4
-- VHDL Entity HAVOC.FPadd_normalize.symbol
-- VHDL Entity work.FPadd_normalize.symbol
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
27,7 → 27,7
END FPadd_normalize ;
 
--
-- VHDL Architecture HAVOC.FPadd_normalize.struct
-- VHDL Architecture work.FPadd_normalize.struct
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
44,8 → 44,6
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
 
LIBRARY HAVOC;
 
ARCHITECTURE struct OF FPadd_normalize IS
 
-- Architecture declarations
75,7 → 73,7
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPlzc USE ENTITY HAVOC.FPlzc;
FOR ALL : FPlzc USE ENTITY work.FPlzc;
-- pragma synthesis_on
 
 
/trunk/fpuvhdl/adder/fpadd_pipeline.vhd
1,4 → 1,4
-- VHDL Entity HAVOC.FPadd.symbol
-- VHDL Entity work.FPadd.symbol
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
27,7 → 27,7
END FPadd ;
 
--
-- VHDL Architecture HAVOC.FPadd.pipeline
-- VHDL Architecture work.FPadd.pipeline
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
43,8 → 43,6
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
LIBRARY HAVOC;
 
ARCHITECTURE pipeline OF FPadd IS
 
-- Architecture declarations
237,12 → 235,12
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPadd_stage1 USE ENTITY HAVOC.FPadd_stage1;
FOR ALL : FPadd_stage2 USE ENTITY HAVOC.FPadd_stage2;
FOR ALL : FPadd_stage3 USE ENTITY HAVOC.FPadd_stage3;
FOR ALL : FPadd_stage4 USE ENTITY HAVOC.FPadd_stage4;
FOR ALL : FPadd_stage5 USE ENTITY HAVOC.FPadd_stage5;
FOR ALL : FPadd_stage6 USE ENTITY HAVOC.FPadd_stage6;
FOR ALL : FPadd_stage1 USE ENTITY work.FPadd_stage1;
FOR ALL : FPadd_stage2 USE ENTITY work.FPadd_stage2;
FOR ALL : FPadd_stage3 USE ENTITY work.FPadd_stage3;
FOR ALL : FPadd_stage4 USE ENTITY work.FPadd_stage4;
FOR ALL : FPadd_stage5 USE ENTITY work.FPadd_stage5;
FOR ALL : FPadd_stage6 USE ENTITY work.FPadd_stage6;
-- pragma synthesis_on
 
 
/trunk/fpuvhdl/adder/fpadd_stage1_struct.vhd
1,4 → 1,4
-- VHDL Entity HAVOC.FPadd_stage1.interface
-- VHDL Entity work.FPadd_stage1.interface
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
41,7 → 41,7
END FPadd_stage1 ;
 
--
-- VHDL Architecture HAVOC.FPadd_stage1.struct
-- VHDL Architecture work.FPadd_stage1.struct
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
57,8 → 57,6
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
LIBRARY HAVOC;
 
ARCHITECTURE struct OF FPadd_stage1 IS
 
-- Architecture declarations
103,7 → 101,7
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : UnpackFP USE ENTITY HAVOC.UnpackFP;
FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
-- pragma synthesis_on
 
 
/trunk/fpuvhdl/adder/fpadd_stage2_struct.vhd
1,4 → 1,4
-- VHDL Entity HAVOC.FPadd_stage2.interface
-- VHDL Entity work.FPadd_stage2.interface
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
49,7 → 49,7
END FPadd_stage2 ;
 
--
-- VHDL Architecture HAVOC.FPadd_stage2.struct
-- VHDL Architecture work.FPadd_stage2.struct
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
65,8 → 65,6
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
LIBRARY HAVOC;
 
ARCHITECTURE struct OF FPadd_stage2 IS
 
-- Architecture declarations
123,8 → 121,8
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPalign USE ENTITY HAVOC.FPalign;
FOR ALL : FPswap USE ENTITY HAVOC.FPswap;
FOR ALL : FPalign USE ENTITY work.FPalign;
FOR ALL : FPswap USE ENTITY work.FPswap;
-- pragma synthesis_on
 
 
/trunk/fpuvhdl/adder/fpadd_stage3_struct.vhd
1,4 → 1,4
-- VHDL Entity HAVOC.FPadd_stage3.interface
-- VHDL Entity work.FPadd_stage3.interface
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
41,7 → 41,7
END FPadd_stage3 ;
 
--
-- VHDL Architecture HAVOC.FPadd_stage3.struct
-- VHDL Architecture work.FPadd_stage3.struct
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
57,8 → 57,6
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
LIBRARY HAVOC;
 
ARCHITECTURE struct OF FPadd_stage3 IS
 
-- Architecture declarations
86,7 → 84,7
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPinvert USE ENTITY HAVOC.FPinvert;
FOR ALL : FPinvert USE ENTITY work.FPinvert;
-- pragma synthesis_on
 
 
/trunk/fpuvhdl/adder/fpadd_stage4_struct.vhd
1,4 → 1,4
-- VHDL Entity HAVOC.FPadd_stage4.interface
-- VHDL Entity work.FPadd_stage4.interface
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
38,7 → 38,7
END FPadd_stage4 ;
 
--
-- VHDL Architecture HAVOC.FPadd_stage4.struct
-- VHDL Architecture work.FPadd_stage4.struct
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
54,8 → 54,6
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
LIBRARY HAVOC;
 
ARCHITECTURE struct OF FPadd_stage4 IS
 
-- Architecture declarations
98,8 → 96,8
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPadd_normalize USE ENTITY HAVOC.FPadd_normalize;
FOR ALL : FPselComplement USE ENTITY HAVOC.FPselComplement;
FOR ALL : FPadd_normalize USE ENTITY work.FPadd_normalize;
FOR ALL : FPselComplement USE ENTITY work.FPselComplement;
-- pragma synthesis_on
 
 
/trunk/fpuvhdl/adder/fpadd_stage5_struct.vhd
1,4 → 1,4
-- VHDL Entity HAVOC.FPadd_stage5.interface
-- VHDL Entity work.FPadd_stage5.interface
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
39,7 → 39,7
END FPadd_stage5 ;
 
--
-- VHDL Architecture HAVOC.FPadd_stage5.struct
-- VHDL Architecture work.FPadd_stage5.struct
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
55,8 → 55,6
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
LIBRARY HAVOC;
 
ARCHITECTURE struct OF FPadd_stage5 IS
 
-- Architecture declarations
94,8 → 92,8
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPnormalize USE ENTITY HAVOC.FPnormalize;
FOR ALL : FPround USE ENTITY HAVOC.FPround;
FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
FOR ALL : FPround USE ENTITY work.FPround;
-- pragma synthesis_on
 
 
/trunk/fpuvhdl/adder/fpadd_stage6_struct.vhd
1,4 → 1,4
-- VHDL Entity HAVOC.FPadd_stage6.interface
-- VHDL Entity work.FPadd_stage6.interface
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
32,7 → 32,7
END FPadd_stage6 ;
 
--
-- VHDL Architecture HAVOC.FPadd_stage6.struct
-- VHDL Architecture work.FPadd_stage6.struct
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
48,8 → 48,6
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
LIBRARY HAVOC;
 
ARCHITECTURE struct OF FPadd_stage6 IS
 
-- Architecture declarations
77,7 → 75,7
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : PackFP USE ENTITY HAVOC.PackFP;
FOR ALL : PackFP USE ENTITY work.PackFP;
-- pragma synthesis_on
 
 
/trunk/fpuvhdl/adder/fpadd_single_cycle.vhd
1,4 → 1,4
-- VHDL Entity HAVOC.FPadd.symbol
-- VHDL Entity work.FPadd.symbol
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
27,7 → 27,7
END FPadd ;
 
--
-- VHDL Architecture HAVOC.FPadd.single_cycle
-- VHDL Architecture work.FPadd.single_cycle
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
43,8 → 43,6
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
LIBRARY HAVOC;
 
ARCHITECTURE single_cycle OF FPadd IS
 
-- Architecture declarations
220,15 → 218,15
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPadd_normalize USE ENTITY HAVOC.FPadd_normalize;
FOR ALL : FPalign USE ENTITY HAVOC.FPalign;
FOR ALL : FPinvert USE ENTITY HAVOC.FPinvert;
FOR ALL : FPnormalize USE ENTITY HAVOC.FPnormalize;
FOR ALL : FPround USE ENTITY HAVOC.FPround;
FOR ALL : FPselComplement USE ENTITY HAVOC.FPselComplement;
FOR ALL : FPswap USE ENTITY HAVOC.FPswap;
FOR ALL : PackFP USE ENTITY HAVOC.PackFP;
FOR ALL : UnpackFP USE ENTITY HAVOC.UnpackFP;
FOR ALL : FPadd_normalize USE ENTITY work.FPadd_normalize;
FOR ALL : FPalign USE ENTITY work.FPalign;
FOR ALL : FPinvert USE ENTITY work.FPinvert;
FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
FOR ALL : FPround USE ENTITY work.FPround;
FOR ALL : FPselComplement USE ENTITY work.FPselComplement;
FOR ALL : FPswap USE ENTITY work.FPswap;
FOR ALL : PackFP USE ENTITY work.PackFP;
FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
-- pragma synthesis_on
 
 
/trunk/fpuvhdl/multiplier/fpmul_single_cycle.vhd
42,8 → 42,6
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
LIBRARY HAVOC;
 
ARCHITECTURE single_cycle OF FPmul IS
 
-- Architecture declarations
134,10 → 132,10
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPnormalize USE ENTITY HAVOC.FPnormalize;
FOR ALL : FPround USE ENTITY HAVOC.FPround;
FOR ALL : PackFP USE ENTITY HAVOC.PackFP;
FOR ALL : UnpackFP USE ENTITY HAVOC.UnpackFP;
FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
FOR ALL : FPround USE ENTITY work.FPround;
FOR ALL : PackFP USE ENTITY work.PackFP;
FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
-- pragma synthesis_on
 
 
234,8 → 232,10
-- eb6 6
PROCESS(SIG_out_norm2,A_EXP,B_EXP, EXP_out)
BEGIN
IF (EXP_out(7)='1' AND A_EXP(7)='0' AND B_EXP(7)='0') OR
(SIG_out_norm2(26 DOWNTO 3)="000000000000000000000000") THEN
IF ( EXP_out(7)='1' AND
( (A_EXP(7)='0' AND NOT (A_EXP=X"7F")) AND
(B_EXP(7)='0' AND NOT (B_EXP=X"7F")) ) ) OR
(SIG_out_norm2(26 DOWNTO 3)=X"000000") THEN
-- Underflow or zero significand
SIG_isZ <= '1';
ELSE
/trunk/fpuvhdl/multiplier/fpmul_pipeline.vhd
42,8 → 42,6
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
LIBRARY HAVOC;
 
ARCHITECTURE pipeline OF FPmul IS
 
-- Architecture declarations
150,10 → 148,10
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPmul_stage1 USE ENTITY HAVOC.FPmul_stage1;
FOR ALL : FPmul_stage2 USE ENTITY HAVOC.FPmul_stage2;
FOR ALL : FPmul_stage3 USE ENTITY HAVOC.FPmul_stage3;
FOR ALL : FPmul_stage4 USE ENTITY HAVOC.FPmul_stage4;
FOR ALL : FPmul_stage1 USE ENTITY work.FPmul_stage1;
FOR ALL : FPmul_stage2 USE ENTITY work.FPmul_stage2;
FOR ALL : FPmul_stage3 USE ENTITY work.FPmul_stage3;
FOR ALL : FPmul_stage4 USE ENTITY work.FPmul_stage4;
-- pragma synthesis_on
 
 
/trunk/fpuvhdl/multiplier/fpmul_stage1_struct.vhd
49,7 → 49,6
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
LIBRARY HAVOC;
 
ARCHITECTURE struct OF FPmul_stage1 IS
 
93,7 → 92,7
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : UnpackFP USE ENTITY HAVOC.UnpackFP;
FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
-- pragma synthesis_on
 
 
/trunk/fpuvhdl/multiplier/fpmul_stage2_struct.vhd
109,7 → 109,8
-- HDL Embedded Text Block 5 eb1
-- exp_pos 5
EXP_pos_int <= A_EXP(7) AND B_EXP(7);
EXP_neg_int <= NOT (A_EXP(7) OR B_EXP(7));
-- EXP_neg_int <= NOT(A_EXP(7) OR B_EXP(7));
EXP_neg_int <= '1' WHEN ( (A_EXP(7)='0' AND NOT (A_EXP=X"7F")) AND (B_EXP(7)='0' AND NOT (B_EXP=X"7F")) ) ELSE '0';
 
 
-- ModuleWare code(v1.1) for instance 'I4' of 'add'
/trunk/fpuvhdl/multiplier/fpmul_stage3_struct.vhd
55,8 → 55,6
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
LIBRARY HAVOC;
 
ARCHITECTURE struct OF FPmul_stage3 IS
 
-- Architecture declarations
94,8 → 92,8
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPnormalize USE ENTITY HAVOC.FPnormalize;
FOR ALL : FPround USE ENTITY HAVOC.FPround;
FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
FOR ALL : FPround USE ENTITY work.FPround;
-- pragma synthesis_on
 
 
/trunk/fpuvhdl/multiplier/fpmul_stage4_struct.vhd
48,8 → 48,6
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
LIBRARY HAVOC;
 
ARCHITECTURE struct OF FPmul_stage4 IS
 
-- Architecture declarations
90,8 → 88,8
 
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : FPnormalize USE ENTITY HAVOC.FPnormalize;
FOR ALL : PackFP USE ENTITY HAVOC.PackFP;
FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
FOR ALL : PackFP USE ENTITY work.PackFP;
-- pragma synthesis_on
 
 
/trunk/fpuvhdl.zip Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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