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https://opencores.org/ocsvn/fpuvhdl/fpuvhdl/trunk
Subversion Repositories fpuvhdl
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/trunk/fpuvhdl/adder/fpadd_stage5_struct.vhd
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/trunk/fpuvhdl/adder/fpinvert_fpinvert.vhd
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/trunk/fpuvhdl/adder/fpadd_stage6_struct.vhd
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/trunk/fpuvhdl/adder/fplzc_fplzc.vhd
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/trunk/fpuvhdl/adder/fpadd_single_cycle.vhd
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/trunk/fpuvhdl/adder/fpswap_fpswap.vhd
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/trunk/fpuvhdl/adder/fpadd_normalize_struct.vhd
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/trunk/fpuvhdl/adder/fpadd_pipeline.vhd
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/trunk/fpuvhdl/adder/fpalign_struct.vhd
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/trunk/fpuvhdl/adder/fpadd_stage1_struct.vhd
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/trunk/fpuvhdl/adder/fpadd_stage2_struct.vhd
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/trunk/fpuvhdl/adder/fpadd_stage3_struct.vhd
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/trunk/fpuvhdl/adder/fpadd_stage4_struct.vhd
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/trunk/fpuvhdl/gpl.txt
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/trunk/fpuvhdl/gpl.html
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/trunk/fpuvhdl/multiplier/fpmul_single_cycle.vhd
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/trunk/fpuvhdl/multiplier/fpmul_pipeline.vhd
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/trunk/fpuvhdl/multiplier/fpmul_stage1_struct.vhd
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/trunk/fpuvhdl/multiplier/fpmul_stage2_struct.vhd
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/trunk/fpuvhdl/multiplier/fpmul_stage3_struct.vhd
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/trunk/fpuvhdl/multiplier/fpmul_stage4_struct.vhd
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/trunk/fpuvhdl/common/fpnormalize_fpnormalize.vhd
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/trunk/fpuvhdl/common/unpackfp_unpackfp.vhd
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/trunk/fpuvhdl/common/packfp_packfp.vhd
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/trunk/fpuvhdl/common/fpround_fpround.vhd
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/trunk/fpuvhdl/README.txt
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/trunk/fpuvhdl.zip
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Index: fpuvhdl/trunk/fpuvhdl/adder/fpadd_normalize_struct.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/adder/fpadd_normalize_struct.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/adder/fpadd_normalize_struct.vhd (revision 5)
@@ -0,0 +1,210 @@
+-- VHDL Entity work.FPadd_normalize.symbol
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPadd_normalize IS
+ PORT(
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_in : IN std_logic_vector (27 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (27 DOWNTO 0);
+ zero : OUT std_logic
+ );
+
+-- Declarations
+
+END FPadd_normalize ;
+
+--
+-- VHDL Architecture work.FPadd_normalize.struct
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ARCHITECTURE struct OF FPadd_normalize IS
+
+ -- Architecture declarations
+
+ -- Internal signal declarations
+ SIGNAL EXP_lshift : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_rshift : std_logic_vector(7 DOWNTO 0);
+ SIGNAL SIG_lshift : std_logic_vector(27 DOWNTO 0);
+ SIGNAL SIG_rshift : std_logic_vector(27 DOWNTO 0);
+ SIGNAL add_in : std_logic_vector(7 DOWNTO 0);
+ SIGNAL cin : std_logic;
+ SIGNAL count : std_logic_vector(4 DOWNTO 0);
+ SIGNAL isDN : std_logic;
+ SIGNAL shift_RL : std_logic;
+ SIGNAL word : std_logic_vector(26 DOWNTO 0);
+ SIGNAL zero_int : std_logic;
+
+
+ -- Component Declarations
+ COMPONENT FPlzc
+ PORT (
+ word : IN std_logic_vector (26 DOWNTO 0);
+ zero : OUT std_logic ;
+ count : OUT std_logic_vector (4 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : FPlzc USE ENTITY work.FPlzc;
+ -- pragma synthesis_on
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 eb1
+ -- eb1 1
+ SIG_rshift <= '0' & SIG_in(27 DOWNTO 2) & (SIG_in(1) AND SIG_in(0));
+
+ -- HDL Embedded Text Block 2 eb2
+ -- eb2 2
+ add_in <= "000" & count;
+
+ -- HDL Embedded Text Block 3 eb3
+ -- eb3 3
+ PROCESS( isDN, shift_RL, EXP_lshift, EXP_rshift, EXP_in, SIG_lshift, SIG_rshift, SIG_in)
+ BEGIN
+ IF (isDN='1') THEN
+ EXP_out <= X"00";
+ SIG_out <= SIG_in;
+ ELSE
+ IF (shift_RL='1') THEN
+ -- Shift Right
+ IF (SIG_in(27)='1') THEN
+ EXP_out <= EXP_rshift;
+ SIG_out <= SIG_rshift;
+ ELSE
+ EXP_out <= EXP_in;
+ SIG_out <= SIG_in;
+ END IF;
+ ELSE
+ -- Shift Left
+ EXP_out <= EXP_lshift;
+ SIG_out <= SIG_lshift;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ -- HDL Embedded Text Block 4 eb4
+ -- eb4 4
+ zero <= zero_int AND NOT SIG_in(27);
+
+ -- HDL Embedded Text Block 5 eb5
+ -- eb5 5
+ word <= SIG_in(26 DOWNTO 0);
+
+ -- HDL Embedded Text Block 6 eb6
+ -- eb6 6
+ PROCESS(SIG_in,EXP_in)
+ BEGIN
+ IF (SIG_in(27)='0' AND SIG_in(26)='0' AND (EXP_in=X"01")) THEN
+ isDN <= '1';
+ shift_RL <= '0';
+ ELSIF (SIG_in(27)='0' AND SIG_in(26)='0' AND (EXP_in/=X"00")) THEN
+ isDN <= '0';
+ shift_RL <= '0';
+ ELSE
+ isDN <= '0';
+ shift_RL <= '1';
+ END IF;
+ END PROCESS;
+
+
+ -- ModuleWare code(v1.1) for instance 'I3' of 'gnd'
+ cin <= '0';
+
+ -- ModuleWare code(v1.1) for instance 'I4' of 'inc'
+ I4combo: PROCESS (EXP_in)
+ VARIABLE t0 : std_logic_vector(8 DOWNTO 0);
+ VARIABLE sum : signed(8 DOWNTO 0);
+ VARIABLE din_l : std_logic_vector(7 DOWNTO 0);
+ BEGIN
+ din_l := EXP_in;
+ t0 := din_l(7) & din_l;
+ sum := (signed(t0) + '1');
+ EXP_rshift <= conv_std_logic_vector(sum(7 DOWNTO 0),8);
+ END PROCESS I4combo;
+
+ -- ModuleWare code(v1.1) for instance 'I1' of 'lshift'
+ I1combo : PROCESS (SIG_in, count)
+ VARIABLE stemp : std_logic_vector (4 DOWNTO 0);
+ VARIABLE dtemp : std_logic_vector (27 DOWNTO 0);
+ VARIABLE temp : std_logic_vector (27 DOWNTO 0);
+ BEGIN
+ temp := (OTHERS=> 'X');
+ stemp := count;
+ temp := SIG_in;
+ FOR i IN 4 DOWNTO 0 LOOP
+ IF (i < 5) THEN
+ IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
+ dtemp := (OTHERS => '0');
+ dtemp(27 DOWNTO 2**i) := temp(27 - 2**i DOWNTO 0);
+ ELSIF (stemp(i) = '0' OR stemp(i) = 'L') THEN
+ dtemp := temp;
+ ELSE
+ dtemp := (OTHERS => 'X');
+ END IF;
+ ELSE
+ IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
+ dtemp := (OTHERS => '0');
+ ELSIF (stemp(i) = '0' OR stemp(i) = 'L') THEN
+ dtemp := temp;
+ ELSE
+ dtemp := (OTHERS => 'X');
+ END IF;
+ END IF;
+ temp := dtemp;
+ END LOOP;
+ SIG_lshift <= dtemp;
+ END PROCESS I1combo;
+
+ -- ModuleWare code(v1.1) for instance 'I2' of 'sub'
+ I2combo: PROCESS (EXP_in, add_in, cin)
+ VARIABLE mw_I2t0 : std_logic_vector(8 DOWNTO 0);
+ VARIABLE mw_I2t1 : std_logic_vector(8 DOWNTO 0);
+ VARIABLE diff : signed(8 DOWNTO 0);
+ VARIABLE borrow : std_logic;
+ BEGIN
+ mw_I2t0 := EXP_in(7) & EXP_in;
+ mw_I2t1 := add_in(7) & add_in;
+ borrow := cin;
+ diff := signed(mw_I2t0) - signed(mw_I2t1) - borrow;
+ EXP_lshift <= conv_std_logic_vector(diff(7 DOWNTO 0),8);
+ END PROCESS I2combo;
+
+ -- Instance port mappings.
+ I0 : FPlzc
+ PORT MAP (
+ word => word,
+ zero => zero_int,
+ count => count
+ );
+
+END struct;
Index: fpuvhdl/trunk/fpuvhdl/adder/fpadd_pipeline.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/adder/fpadd_pipeline.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/adder/fpadd_pipeline.vhd (revision 5)
@@ -0,0 +1,377 @@
+-- VHDL Entity work.FPadd.symbol
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPadd IS
+ PORT(
+ ADD_SUB : IN std_logic;
+ FP_A : IN std_logic_vector (31 DOWNTO 0);
+ FP_B : IN std_logic_vector (31 DOWNTO 0);
+ clk : IN std_logic;
+ FP_Z : OUT std_logic_vector (31 DOWNTO 0)
+ );
+
+-- Declarations
+
+END FPadd ;
+
+--
+-- VHDL Architecture work.FPadd.pipeline
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ARCHITECTURE pipeline OF FPadd IS
+
+ -- Architecture declarations
+
+ -- Internal signal declarations
+ SIGNAL ADD_SUB_out : std_logic;
+ SIGNAL A_EXP : std_logic_vector(7 DOWNTO 0);
+ SIGNAL A_SIGN : std_logic;
+ SIGNAL A_SIGN_stage2 : std_logic;
+ SIGNAL A_SIGN_stage3 : std_logic;
+ SIGNAL A_align : std_logic_vector(28 DOWNTO 0);
+ SIGNAL A_in : std_logic_vector(28 DOWNTO 0);
+ SIGNAL A_isINF : std_logic;
+ SIGNAL A_isNaN : std_logic;
+ SIGNAL A_isZ : std_logic;
+ SIGNAL B_EXP : std_logic_vector(7 DOWNTO 0);
+ SIGNAL B_XSIGN : std_logic;
+ SIGNAL B_XSIGN_stage2 : std_logic;
+ SIGNAL B_XSIGN_stage3 : std_logic;
+ SIGNAL B_align : std_logic_vector(28 DOWNTO 0);
+ SIGNAL B_in : std_logic_vector(28 DOWNTO 0);
+ SIGNAL B_isINF : std_logic;
+ SIGNAL B_isNaN : std_logic;
+ SIGNAL B_isZ : std_logic;
+ SIGNAL EXP_base : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_base_stage2 : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_diff : std_logic_vector(8 DOWNTO 0);
+ SIGNAL EXP_norm : std_logic_vector(7 DOWNTO 0);
+ SIGNAL OV : std_logic;
+ SIGNAL OV_stage4 : std_logic;
+ SIGNAL SIG_norm : std_logic_vector(27 DOWNTO 0);
+ SIGNAL SIG_norm2 : std_logic_vector(27 DOWNTO 0);
+ SIGNAL Z_EXP : std_logic_vector(7 DOWNTO 0);
+ SIGNAL Z_SIGN : std_logic;
+ SIGNAL Z_SIGN_stage4 : std_logic;
+ SIGNAL add_out : std_logic_vector(28 DOWNTO 0);
+ SIGNAL cin : std_logic;
+ SIGNAL cin_sub : std_logic;
+ SIGNAL invert_A : std_logic;
+ SIGNAL invert_B : std_logic;
+ SIGNAL isINF_tab : std_logic;
+ SIGNAL isINF_tab_stage2 : std_logic;
+ SIGNAL isINF_tab_stage3 : std_logic;
+ SIGNAL isINF_tab_stage4 : std_logic;
+ SIGNAL isNaN : std_logic;
+ SIGNAL isNaN_stage2 : std_logic;
+ SIGNAL isNaN_stage3 : std_logic;
+ SIGNAL isNaN_stage4 : std_logic;
+ SIGNAL isZ_tab : std_logic;
+ SIGNAL isZ_tab_stage2 : std_logic;
+ SIGNAL isZ_tab_stage3 : std_logic;
+ SIGNAL isZ_tab_stage4 : std_logic;
+ SIGNAL zero : std_logic;
+ SIGNAL zero_stage4 : std_logic;
+
+
+ -- Component Declarations
+ COMPONENT FPadd_stage1
+ PORT (
+ ADD_SUB : IN std_logic ;
+ FP_A : IN std_logic_vector (31 DOWNTO 0);
+ FP_B : IN std_logic_vector (31 DOWNTO 0);
+ clk : IN std_logic ;
+ ADD_SUB_out : OUT std_logic ;
+ A_EXP : OUT std_logic_vector (7 DOWNTO 0);
+ A_SIGN : OUT std_logic ;
+ A_in : OUT std_logic_vector (28 DOWNTO 0);
+ A_isINF : OUT std_logic ;
+ A_isNaN : OUT std_logic ;
+ A_isZ : OUT std_logic ;
+ B_EXP : OUT std_logic_vector (7 DOWNTO 0);
+ B_XSIGN : OUT std_logic ;
+ B_in : OUT std_logic_vector (28 DOWNTO 0);
+ B_isINF : OUT std_logic ;
+ B_isNaN : OUT std_logic ;
+ B_isZ : OUT std_logic ;
+ EXP_diff : OUT std_logic_vector (8 DOWNTO 0);
+ cin_sub : OUT std_logic
+ );
+ END COMPONENT;
+ COMPONENT FPadd_stage2
+ PORT (
+ ADD_SUB_out : IN std_logic ;
+ A_EXP : IN std_logic_vector (7 DOWNTO 0);
+ A_SIGN : IN std_logic ;
+ A_in : IN std_logic_vector (28 DOWNTO 0);
+ A_isINF : IN std_logic ;
+ A_isNaN : IN std_logic ;
+ A_isZ : IN std_logic ;
+ B_EXP : IN std_logic_vector (7 DOWNTO 0);
+ B_XSIGN : IN std_logic ;
+ B_in : IN std_logic_vector (28 DOWNTO 0);
+ B_isINF : IN std_logic ;
+ B_isNaN : IN std_logic ;
+ B_isZ : IN std_logic ;
+ EXP_diff : IN std_logic_vector (8 DOWNTO 0);
+ cin_sub : IN std_logic ;
+ clk : IN std_logic ;
+ A_SIGN_stage2 : OUT std_logic ;
+ A_align : OUT std_logic_vector (28 DOWNTO 0);
+ B_XSIGN_stage2 : OUT std_logic ;
+ B_align : OUT std_logic_vector (28 DOWNTO 0);
+ EXP_base_stage2 : OUT std_logic_vector (7 DOWNTO 0);
+ cin : OUT std_logic ;
+ invert_A : OUT std_logic ;
+ invert_B : OUT std_logic ;
+ isINF_tab_stage2 : OUT std_logic ;
+ isNaN_stage2 : OUT std_logic ;
+ isZ_tab_stage2 : OUT std_logic
+ );
+ END COMPONENT;
+ COMPONENT FPadd_stage3
+ PORT (
+ A_SIGN_stage2 : IN std_logic ;
+ A_align : IN std_logic_vector (28 DOWNTO 0);
+ B_XSIGN_stage2 : IN std_logic ;
+ B_align : IN std_logic_vector (28 DOWNTO 0);
+ EXP_base_stage2 : IN std_logic_vector (7 DOWNTO 0);
+ cin : IN std_logic ;
+ clk : IN std_logic ;
+ invert_A : IN std_logic ;
+ invert_B : IN std_logic ;
+ isINF_tab_stage2 : IN std_logic ;
+ isNaN_stage2 : IN std_logic ;
+ isZ_tab_stage2 : IN std_logic ;
+ A_SIGN_stage3 : OUT std_logic ;
+ B_XSIGN_stage3 : OUT std_logic ;
+ EXP_base : OUT std_logic_vector (7 DOWNTO 0);
+ add_out : OUT std_logic_vector (28 DOWNTO 0);
+ isINF_tab_stage3 : OUT std_logic ;
+ isNaN_stage3 : OUT std_logic ;
+ isZ_tab_stage3 : OUT std_logic
+ );
+ END COMPONENT;
+ COMPONENT FPadd_stage4
+ PORT (
+ A_SIGN_stage3 : IN std_logic ;
+ B_XSIGN_stage3 : IN std_logic ;
+ EXP_base : IN std_logic_vector (7 DOWNTO 0);
+ add_out : IN std_logic_vector (28 DOWNTO 0);
+ clk : IN std_logic ;
+ isINF_tab_stage3 : IN std_logic ;
+ isNaN_stage3 : IN std_logic ;
+ isZ_tab_stage3 : IN std_logic ;
+ EXP_norm : OUT std_logic_vector (7 DOWNTO 0);
+ OV_stage4 : OUT std_logic ;
+ SIG_norm : OUT std_logic_vector (27 DOWNTO 0);
+ Z_SIGN_stage4 : OUT std_logic ;
+ isINF_tab_stage4 : OUT std_logic ;
+ isNaN_stage4 : OUT std_logic ;
+ isZ_tab_stage4 : OUT std_logic ;
+ zero_stage4 : OUT std_logic
+ );
+ END COMPONENT;
+ COMPONENT FPadd_stage5
+ PORT (
+ EXP_norm : IN std_logic_vector (7 DOWNTO 0);
+ OV_stage4 : IN std_logic ;
+ SIG_norm : IN std_logic_vector (27 DOWNTO 0);
+ Z_SIGN_stage4 : IN std_logic ;
+ clk : IN std_logic ;
+ isINF_tab_stage4 : IN std_logic ;
+ isNaN_stage4 : IN std_logic ;
+ isZ_tab_stage4 : IN std_logic ;
+ zero_stage4 : IN std_logic ;
+ OV : OUT std_logic ;
+ SIG_norm2 : OUT std_logic_vector (27 DOWNTO 0);
+ Z_EXP : OUT std_logic_vector (7 DOWNTO 0);
+ Z_SIGN : OUT std_logic ;
+ isINF_tab : OUT std_logic ;
+ isNaN : OUT std_logic ;
+ isZ_tab : OUT std_logic ;
+ zero : OUT std_logic
+ );
+ END COMPONENT;
+ COMPONENT FPadd_stage6
+ PORT (
+ OV : IN std_logic ;
+ SIG_norm2 : IN std_logic_vector (27 DOWNTO 0);
+ Z_EXP : IN std_logic_vector (7 DOWNTO 0);
+ Z_SIGN : IN std_logic ;
+ clk : IN std_logic ;
+ isINF_tab : IN std_logic ;
+ isNaN : IN std_logic ;
+ isZ_tab : IN std_logic ;
+ zero : IN std_logic ;
+ FP_Z : OUT std_logic_vector (31 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : FPadd_stage1 USE ENTITY work.FPadd_stage1;
+ FOR ALL : FPadd_stage2 USE ENTITY work.FPadd_stage2;
+ FOR ALL : FPadd_stage3 USE ENTITY work.FPadd_stage3;
+ FOR ALL : FPadd_stage4 USE ENTITY work.FPadd_stage4;
+ FOR ALL : FPadd_stage5 USE ENTITY work.FPadd_stage5;
+ FOR ALL : FPadd_stage6 USE ENTITY work.FPadd_stage6;
+ -- pragma synthesis_on
+
+
+BEGIN
+
+ -- Instance port mappings.
+ I1 : FPadd_stage1
+ PORT MAP (
+ ADD_SUB => ADD_SUB,
+ FP_A => FP_A,
+ FP_B => FP_B,
+ clk => clk,
+ ADD_SUB_out => ADD_SUB_out,
+ A_EXP => A_EXP,
+ A_SIGN => A_SIGN,
+ A_in => A_in,
+ A_isINF => A_isINF,
+ A_isNaN => A_isNaN,
+ A_isZ => A_isZ,
+ B_EXP => B_EXP,
+ B_XSIGN => B_XSIGN,
+ B_in => B_in,
+ B_isINF => B_isINF,
+ B_isNaN => B_isNaN,
+ B_isZ => B_isZ,
+ EXP_diff => EXP_diff,
+ cin_sub => cin_sub
+ );
+ I2 : FPadd_stage2
+ PORT MAP (
+ ADD_SUB_out => ADD_SUB_out,
+ A_EXP => A_EXP,
+ A_SIGN => A_SIGN,
+ A_in => A_in,
+ A_isINF => A_isINF,
+ A_isNaN => A_isNaN,
+ A_isZ => A_isZ,
+ B_EXP => B_EXP,
+ B_XSIGN => B_XSIGN,
+ B_in => B_in,
+ B_isINF => B_isINF,
+ B_isNaN => B_isNaN,
+ B_isZ => B_isZ,
+ EXP_diff => EXP_diff,
+ cin_sub => cin_sub,
+ clk => clk,
+ A_SIGN_stage2 => A_SIGN_stage2,
+ A_align => A_align,
+ B_XSIGN_stage2 => B_XSIGN_stage2,
+ B_align => B_align,
+ EXP_base_stage2 => EXP_base_stage2,
+ cin => cin,
+ invert_A => invert_A,
+ invert_B => invert_B,
+ isINF_tab_stage2 => isINF_tab_stage2,
+ isNaN_stage2 => isNaN_stage2,
+ isZ_tab_stage2 => isZ_tab_stage2
+ );
+ I3 : FPadd_stage3
+ PORT MAP (
+ A_SIGN_stage2 => A_SIGN_stage2,
+ A_align => A_align,
+ B_XSIGN_stage2 => B_XSIGN_stage2,
+ B_align => B_align,
+ EXP_base_stage2 => EXP_base_stage2,
+ cin => cin,
+ clk => clk,
+ invert_A => invert_A,
+ invert_B => invert_B,
+ isINF_tab_stage2 => isINF_tab_stage2,
+ isNaN_stage2 => isNaN_stage2,
+ isZ_tab_stage2 => isZ_tab_stage2,
+ A_SIGN_stage3 => A_SIGN_stage3,
+ B_XSIGN_stage3 => B_XSIGN_stage3,
+ EXP_base => EXP_base,
+ add_out => add_out,
+ isINF_tab_stage3 => isINF_tab_stage3,
+ isNaN_stage3 => isNaN_stage3,
+ isZ_tab_stage3 => isZ_tab_stage3
+ );
+ I4 : FPadd_stage4
+ PORT MAP (
+ A_SIGN_stage3 => A_SIGN_stage3,
+ B_XSIGN_stage3 => B_XSIGN_stage3,
+ EXP_base => EXP_base,
+ add_out => add_out,
+ clk => clk,
+ isINF_tab_stage3 => isINF_tab_stage3,
+ isNaN_stage3 => isNaN_stage3,
+ isZ_tab_stage3 => isZ_tab_stage3,
+ EXP_norm => EXP_norm,
+ OV_stage4 => OV_stage4,
+ SIG_norm => SIG_norm,
+ Z_SIGN_stage4 => Z_SIGN_stage4,
+ isINF_tab_stage4 => isINF_tab_stage4,
+ isNaN_stage4 => isNaN_stage4,
+ isZ_tab_stage4 => isZ_tab_stage4,
+ zero_stage4 => zero_stage4
+ );
+ I5 : FPadd_stage5
+ PORT MAP (
+ EXP_norm => EXP_norm,
+ OV_stage4 => OV_stage4,
+ SIG_norm => SIG_norm,
+ Z_SIGN_stage4 => Z_SIGN_stage4,
+ clk => clk,
+ isINF_tab_stage4 => isINF_tab_stage4,
+ isNaN_stage4 => isNaN_stage4,
+ isZ_tab_stage4 => isZ_tab_stage4,
+ zero_stage4 => zero_stage4,
+ OV => OV,
+ SIG_norm2 => SIG_norm2,
+ Z_EXP => Z_EXP,
+ Z_SIGN => Z_SIGN,
+ isINF_tab => isINF_tab,
+ isNaN => isNaN,
+ isZ_tab => isZ_tab,
+ zero => zero
+ );
+ I6 : FPadd_stage6
+ PORT MAP (
+ OV => OV,
+ SIG_norm2 => SIG_norm2,
+ Z_EXP => Z_EXP,
+ Z_SIGN => Z_SIGN,
+ clk => clk,
+ isINF_tab => isINF_tab,
+ isNaN => isNaN,
+ isZ_tab => isZ_tab,
+ zero => zero,
+ FP_Z => FP_Z
+ );
+
+END pipeline;
Index: fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage1_struct.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage1_struct.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage1_struct.vhd (revision 5)
@@ -0,0 +1,195 @@
+-- VHDL Entity work.FPadd_stage1.interface
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPadd_stage1 IS
+ PORT(
+ ADD_SUB : IN std_logic;
+ FP_A : IN std_logic_vector (31 DOWNTO 0);
+ FP_B : IN std_logic_vector (31 DOWNTO 0);
+ clk : IN std_logic;
+ ADD_SUB_out : OUT std_logic;
+ A_EXP : OUT std_logic_vector (7 DOWNTO 0);
+ A_SIGN : OUT std_logic;
+ A_in : OUT std_logic_vector (28 DOWNTO 0);
+ A_isINF : OUT std_logic;
+ A_isNaN : OUT std_logic;
+ A_isZ : OUT std_logic;
+ B_EXP : OUT std_logic_vector (7 DOWNTO 0);
+ B_XSIGN : OUT std_logic;
+ B_in : OUT std_logic_vector (28 DOWNTO 0);
+ B_isINF : OUT std_logic;
+ B_isNaN : OUT std_logic;
+ B_isZ : OUT std_logic;
+ EXP_diff : OUT std_logic_vector (8 DOWNTO 0);
+ cin_sub : OUT std_logic
+ );
+
+-- Declarations
+
+END FPadd_stage1 ;
+
+--
+-- VHDL Architecture work.FPadd_stage1.struct
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ARCHITECTURE struct OF FPadd_stage1 IS
+
+ -- Architecture declarations
+
+ -- Internal signal declarations
+ SIGNAL A_EXP_int : std_logic_vector(7 DOWNTO 0);
+ SIGNAL A_SIG : std_logic_vector(31 DOWNTO 0);
+ SIGNAL A_SIGN_int : std_logic;
+ SIGNAL A_in_int : std_logic_vector(28 DOWNTO 0);
+ SIGNAL A_isDN_int : std_logic;
+ SIGNAL A_isINF_int : std_logic;
+ SIGNAL A_isNaN_int : std_logic;
+ SIGNAL A_isZ_int : std_logic;
+ SIGNAL B_EXP_int : std_logic_vector(7 DOWNTO 0);
+ SIGNAL B_SIG : std_logic_vector(31 DOWNTO 0);
+ SIGNAL B_SIGN_int : std_logic;
+ SIGNAL B_XSIGN_int : std_logic;
+ SIGNAL B_in_int : std_logic_vector(28 DOWNTO 0);
+ SIGNAL B_isDN_int : std_logic;
+ SIGNAL B_isINF_int : std_logic;
+ SIGNAL B_isNaN_int : std_logic;
+ SIGNAL B_isZ_int : std_logic;
+ SIGNAL EXP_diff_int : std_logic_vector(8 DOWNTO 0);
+ SIGNAL a_exp_in : std_logic_vector(8 DOWNTO 0);
+ SIGNAL b_exp_in : std_logic_vector(8 DOWNTO 0);
+ SIGNAL cin_sub_int : std_logic;
+
+
+ -- Component Declarations
+ COMPONENT UnpackFP
+ PORT (
+ FP : IN std_logic_vector (31 DOWNTO 0);
+ SIG : OUT std_logic_vector (31 DOWNTO 0);
+ EXP : OUT std_logic_vector (7 DOWNTO 0);
+ SIGN : OUT std_logic ;
+ isNaN : OUT std_logic ;
+ isINF : OUT std_logic ;
+ isZ : OUT std_logic ;
+ isDN : OUT std_logic
+ );
+ END COMPONENT;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
+ -- pragma synthesis_on
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 eb1
+ -- reg1 1
+ PROCESS(clk)
+ BEGIN
+ IF RISING_EDGE(clk) THEN
+ A_SIGN <= A_SIGN_int;
+ B_XSIGN <= B_XSIGN_int;
+ A_in <= A_in_int;
+ B_in <= B_in_int;
+ A_EXP <= A_EXP_int;
+ B_EXP <= B_EXP_int;
+ EXP_diff <= EXP_diff_int;
+ A_isZ <= A_isZ_int;
+ B_isZ <= B_isZ_int;
+ A_isINF <= A_isINF_int;
+ B_isINF <= B_isINF_int;
+ A_isNaN <= A_isNaN_int;
+ B_isNaN <= B_isNaN_int;
+ ADD_SUB_out <= ADD_SUB;
+ cin_sub <= cin_sub_int;
+ END IF;
+ END PROCESS;
+
+ -- HDL Embedded Text Block 2 eb2
+ -- eb2 2
+ a_exp_in <= "0" & A_EXP_int;
+
+ -- HDL Embedded Text Block 3 eb3
+ -- eb3 3
+ b_exp_in <= "0" & B_EXP_int;
+
+ -- HDL Embedded Text Block 4 eb4
+ -- eb4 4
+ cin_sub_int <= (A_isZ_int OR A_isDN_int) XOR (B_isZ_int OR B_isDN_int);
+
+ -- HDL Embedded Text Block 8 eb6
+ -- eb5 7
+ A_in_int <= "00" & A_SIG(23 DOWNTO 0) & "000";
+
+ -- HDL Embedded Text Block 10 eb8
+ -- eb6 8
+ B_in_int <= "00" & B_SIG(23 DOWNTO 0) & "000";
+
+
+ -- ModuleWare code(v1.1) for instance 'I5' of 'sub'
+ I5combo: PROCESS (a_exp_in, b_exp_in, cin_sub_int)
+ VARIABLE mw_I5t0 : std_logic_vector(9 DOWNTO 0);
+ VARIABLE mw_I5t1 : std_logic_vector(9 DOWNTO 0);
+ VARIABLE diff : signed(9 DOWNTO 0);
+ VARIABLE borrow : std_logic;
+ BEGIN
+ mw_I5t0 := a_exp_in(8) & a_exp_in;
+ mw_I5t1 := b_exp_in(8) & b_exp_in;
+ borrow := cin_sub_int;
+ diff := signed(mw_I5t0) - signed(mw_I5t1) - borrow;
+ EXP_diff_int <= conv_std_logic_vector(diff(8 DOWNTO 0),9);
+ END PROCESS I5combo;
+
+ -- ModuleWare code(v1.1) for instance 'I18' of 'xnor'
+ B_XSIGN_int <= NOT(B_SIGN_int XOR ADD_SUB);
+
+ -- Instance port mappings.
+ I1 : UnpackFP
+ PORT MAP (
+ FP => FP_A,
+ SIG => A_SIG,
+ EXP => A_EXP_int,
+ SIGN => A_SIGN_int,
+ isNaN => A_isNaN_int,
+ isINF => A_isINF_int,
+ isZ => A_isZ_int,
+ isDN => A_isDN_int
+ );
+ I3 : UnpackFP
+ PORT MAP (
+ FP => FP_B,
+ SIG => B_SIG,
+ EXP => B_EXP_int,
+ SIGN => B_SIGN_int,
+ isNaN => B_isNaN_int,
+ isINF => B_isINF_int,
+ isZ => B_isZ_int,
+ isDN => B_isDN_int
+ );
+
+END struct;
Index: fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage2_struct.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage2_struct.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage2_struct.vhd (revision 5)
@@ -0,0 +1,278 @@
+-- VHDL Entity work.FPadd_stage2.interface
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPadd_stage2 IS
+ PORT(
+ ADD_SUB_out : IN std_logic;
+ A_EXP : IN std_logic_vector (7 DOWNTO 0);
+ A_SIGN : IN std_logic;
+ A_in : IN std_logic_vector (28 DOWNTO 0);
+ A_isINF : IN std_logic;
+ A_isNaN : IN std_logic;
+ A_isZ : IN std_logic;
+ B_EXP : IN std_logic_vector (7 DOWNTO 0);
+ B_XSIGN : IN std_logic;
+ B_in : IN std_logic_vector (28 DOWNTO 0);
+ B_isINF : IN std_logic;
+ B_isNaN : IN std_logic;
+ B_isZ : IN std_logic;
+ EXP_diff : IN std_logic_vector (8 DOWNTO 0);
+ cin_sub : IN std_logic;
+ clk : IN std_logic;
+ A_SIGN_stage2 : OUT std_logic;
+ A_align : OUT std_logic_vector (28 DOWNTO 0);
+ B_XSIGN_stage2 : OUT std_logic;
+ B_align : OUT std_logic_vector (28 DOWNTO 0);
+ EXP_base_stage2 : OUT std_logic_vector (7 DOWNTO 0);
+ cin : OUT std_logic;
+ invert_A : OUT std_logic;
+ invert_B : OUT std_logic;
+ isINF_tab_stage2 : OUT std_logic;
+ isNaN_stage2 : OUT std_logic;
+ isZ_tab_stage2 : OUT std_logic
+ );
+
+-- Declarations
+
+END FPadd_stage2 ;
+
+--
+-- VHDL Architecture work.FPadd_stage2.struct
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ARCHITECTURE struct OF FPadd_stage2 IS
+
+ -- Architecture declarations
+ -- Non hierarchical truthtable declarations
+
+
+ -- Non hierarchical truthtable declarations
+
+
+
+ -- Internal signal declarations
+ SIGNAL A_CS : std_logic_vector(28 DOWNTO 0);
+ SIGNAL A_align_int : std_logic_vector(28 DOWNTO 0);
+ SIGNAL B_CS : std_logic_vector(28 DOWNTO 0);
+ SIGNAL B_align_int : std_logic_vector(28 DOWNTO 0);
+ SIGNAL EXP_base_int : std_logic_vector(7 DOWNTO 0);
+ SIGNAL cin_int : std_logic;
+ SIGNAL diff : std_logic_vector(8 DOWNTO 0);
+ SIGNAL invert_A_int : std_logic;
+ SIGNAL invert_B_int : std_logic;
+ SIGNAL isINF_tab_int : std_logic;
+ SIGNAL isNaN_int : std_logic;
+ SIGNAL isZ_tab_int : std_logic;
+ SIGNAL swap_AB : std_logic;
+
+
+ -- ModuleWare signal declarations(v1.1) for instance 'I2' of 'mux'
+ SIGNAL mw_I2din0 : std_logic_vector(7 DOWNTO 0);
+ SIGNAL mw_I2din1 : std_logic_vector(7 DOWNTO 0);
+
+ -- Component Declarations
+ COMPONENT FPalign
+ PORT (
+ A_in : IN std_logic_vector (28 DOWNTO 0);
+ B_in : IN std_logic_vector (28 DOWNTO 0);
+ cin : IN std_logic ;
+ diff : IN std_logic_vector (8 DOWNTO 0);
+ A_out : OUT std_logic_vector (28 DOWNTO 0);
+ B_out : OUT std_logic_vector (28 DOWNTO 0)
+ );
+ END COMPONENT;
+ COMPONENT FPswap
+ GENERIC (
+ width : integer := 29
+ );
+ PORT (
+ A_in : IN std_logic_vector (width-1 DOWNTO 0);
+ B_in : IN std_logic_vector (width-1 DOWNTO 0);
+ swap_AB : IN std_logic ;
+ A_out : OUT std_logic_vector (width-1 DOWNTO 0);
+ B_out : OUT std_logic_vector (width-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : FPalign USE ENTITY work.FPalign;
+ FOR ALL : FPswap USE ENTITY work.FPswap;
+ -- pragma synthesis_on
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 reg1
+ -- reg1 1
+ PROCESS(clk)
+ BEGIN
+ IF RISING_EDGE(clk) THEN
+ cin <= cin_int;
+ invert_A <= invert_A_int;
+ invert_B <= invert_B_int;
+ EXP_base_stage2 <= EXP_base_int;
+ A_align <= A_align_int;
+ B_align <= B_align_int;
+ A_SIGN_stage2 <= A_SIGN;
+ B_XSIGN_stage2 <= B_XSIGN;
+ isINF_tab_stage2 <= isINF_tab_int;
+ isNaN_stage2 <= isNaN_int;
+ isZ_tab_stage2 <= isZ_tab_int;
+ END IF;
+ END PROCESS;
+
+ -- HDL Embedded Text Block 2 diff_sign
+ -- eb5 7
+ swap_AB <= EXP_diff(8);
+ diff <= EXP_diff(8 DOWNTO 0);
+
+ -- HDL Embedded Block 3 InvertLogic
+ -- Non hierarchical truthtable
+ ---------------------------------------------------------------------------
+ InvertLogic_truth_process: PROCESS(A_SIGN, B_XSIGN, swap_AB)
+ ---------------------------------------------------------------------------
+ BEGIN
+ -- Block 1
+ IF (A_SIGN = '0') AND (B_XSIGN = '0') THEN
+ invert_A_int <= '0';
+ invert_B_int <= '0';
+ ELSIF (A_SIGN = '1') AND (B_XSIGN = '1') THEN
+ invert_A_int <= '0';
+ invert_B_int <= '0';
+ ELSIF (A_SIGN = '0') AND (B_XSIGN = '1') AND (swap_AB = '0') THEN
+ invert_A_int <= '0';
+ invert_B_int <= '1';
+ ELSIF (A_SIGN = '0') AND (B_XSIGN = '1') AND (swap_AB = '1') THEN
+ invert_A_int <= '1';
+ invert_B_int <= '0';
+ ELSIF (A_SIGN = '1') AND (B_XSIGN = '0') AND (swap_AB = '0') THEN
+ invert_A_int <= '1';
+ invert_B_int <= '0';
+ ELSIF (A_SIGN = '1') AND (B_XSIGN = '0') AND (swap_AB = '1') THEN
+ invert_A_int <= '0';
+ invert_B_int <= '1';
+ ELSE
+ invert_A_int <= '0';
+ invert_B_int <= '0';
+ END IF;
+
+ END PROCESS InvertLogic_truth_process;
+
+ -- Architecture concurrent statements
+
+
+
+ -- HDL Embedded Block 4 exceptions
+ -- Non hierarchical truthtable
+ ---------------------------------------------------------------------------
+ exceptions_truth_process: PROCESS(ADD_SUB_out, A_isINF, A_isNaN, A_isZ, B_isINF, B_isNaN, B_isZ)
+ ---------------------------------------------------------------------------
+ BEGIN
+ -- Block 1
+ IF (A_isNaN = '1') THEN
+ isINF_tab_int <= '0';
+ isNaN_int <= '1';
+ isZ_tab_int <= '0';
+ ELSIF (B_isNaN = '1') THEN
+ isINF_tab_int <= '0';
+ isNaN_int <= '1';
+ isZ_tab_int <= '0';
+ ELSIF (ADD_SUB_out = '1') AND (A_isINF = '1') AND (B_isINF = '1') THEN
+ isINF_tab_int <= '1';
+ isNaN_int <= '0';
+ isZ_tab_int <= '0';
+ ELSIF (ADD_SUB_out = '0') AND (A_isINF = '1') AND (B_isINF = '1') THEN
+ isINF_tab_int <= '0';
+ isNaN_int <= '1';
+ isZ_tab_int <= '0';
+ ELSIF (A_isINF = '1') THEN
+ isINF_tab_int <= '1';
+ isNaN_int <= '0';
+ isZ_tab_int <= '0';
+ ELSIF (B_isINF = '1') THEN
+ isINF_tab_int <= '1';
+ isNaN_int <= '0';
+ isZ_tab_int <= '0';
+ ELSIF (A_isZ = '1') AND (B_isZ = '1') THEN
+ isINF_tab_int <= '0';
+ isNaN_int <= '0';
+ isZ_tab_int <= '1';
+ ELSE
+ isINF_tab_int <= '0';
+ isNaN_int <= '0';
+ isZ_tab_int <= '0';
+ END IF;
+
+ END PROCESS exceptions_truth_process;
+
+ -- Architecture concurrent statements
+
+
+
+
+ -- ModuleWare code(v1.1) for instance 'I2' of 'mux'
+ I2combo: PROCESS(mw_I2din0, mw_I2din1, swap_AB)
+ VARIABLE dtemp : std_logic_vector(7 DOWNTO 0);
+ BEGIN
+ CASE swap_AB IS
+ WHEN '0'|'L' => dtemp := mw_I2din0;
+ WHEN '1'|'H' => dtemp := mw_I2din1;
+ WHEN OTHERS => dtemp := (OTHERS => 'X');
+ END CASE;
+ EXP_base_int <= dtemp;
+ END PROCESS I2combo;
+ mw_I2din0 <= A_EXP;
+ mw_I2din1 <= B_EXP;
+
+ -- ModuleWare code(v1.1) for instance 'I1' of 'or'
+ cin_int <= invert_B_int OR invert_A_int;
+
+ -- Instance port mappings.
+ I4 : FPalign
+ PORT MAP (
+ A_in => A_CS,
+ B_in => B_CS,
+ cin => cin_sub,
+ diff => diff,
+ A_out => A_align_int,
+ B_out => B_align_int
+ );
+ I3 : FPswap
+ GENERIC MAP (
+ width => 29
+ )
+ PORT MAP (
+ A_in => A_in,
+ B_in => B_in,
+ swap_AB => swap_AB,
+ A_out => A_CS,
+ B_out => B_CS
+ );
+
+END struct;
Index: fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage3_struct.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage3_struct.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage3_struct.vhd (revision 5)
@@ -0,0 +1,137 @@
+-- VHDL Entity work.FPadd_stage3.interface
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPadd_stage3 IS
+ PORT(
+ A_SIGN_stage2 : IN std_logic;
+ A_align : IN std_logic_vector (28 DOWNTO 0);
+ B_XSIGN_stage2 : IN std_logic;
+ B_align : IN std_logic_vector (28 DOWNTO 0);
+ EXP_base_stage2 : IN std_logic_vector (7 DOWNTO 0);
+ cin : IN std_logic;
+ clk : IN std_logic;
+ invert_A : IN std_logic;
+ invert_B : IN std_logic;
+ isINF_tab_stage2 : IN std_logic;
+ isNaN_stage2 : IN std_logic;
+ isZ_tab_stage2 : IN std_logic;
+ A_SIGN_stage3 : OUT std_logic;
+ B_XSIGN_stage3 : OUT std_logic;
+ EXP_base : OUT std_logic_vector (7 DOWNTO 0);
+ add_out : OUT std_logic_vector (28 DOWNTO 0);
+ isINF_tab_stage3 : OUT std_logic;
+ isNaN_stage3 : OUT std_logic;
+ isZ_tab_stage3 : OUT std_logic
+ );
+
+-- Declarations
+
+END FPadd_stage3 ;
+
+--
+-- VHDL Architecture work.FPadd_stage3.struct
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ARCHITECTURE struct OF FPadd_stage3 IS
+
+ -- Architecture declarations
+
+ -- Internal signal declarations
+ SIGNAL A_inv : std_logic_vector(28 DOWNTO 0);
+ SIGNAL B_inv : std_logic_vector(28 DOWNTO 0);
+ SIGNAL add_out_int : std_logic_vector(28 DOWNTO 0);
+
+
+ -- Component Declarations
+ COMPONENT FPinvert
+ GENERIC (
+ width : integer := 29
+ );
+ PORT (
+ A_in : IN std_logic_vector (width-1 DOWNTO 0);
+ B_in : IN std_logic_vector (width-1 DOWNTO 0);
+ invert_A : IN std_logic ;
+ invert_B : IN std_logic ;
+ A_out : OUT std_logic_vector (width-1 DOWNTO 0);
+ B_out : OUT std_logic_vector (width-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : FPinvert USE ENTITY work.FPinvert;
+ -- pragma synthesis_on
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 reg1
+ -- reg1 1
+ PROCESS(clk)
+ BEGIN
+ IF RISING_EDGE(clk) THEN
+ add_out <= add_out_int;
+ EXP_base <= EXP_base_stage2;
+ A_SIGN_stage3 <= A_SIGN_stage2;
+ B_XSIGN_stage3 <= B_XSIGN_stage2;
+ isINF_tab_stage3 <= isINF_tab_stage2;
+ isNaN_stage3 <= isNaN_stage2;
+ isZ_tab_stage3 <= isZ_tab_stage2;
+ END IF;
+ END PROCESS;
+
+
+ -- ModuleWare code(v1.1) for instance 'I4' of 'add'
+ I4combo: PROCESS (A_inv, B_inv, cin)
+ VARIABLE mw_I4t0 : std_logic_vector(29 DOWNTO 0);
+ VARIABLE mw_I4t1 : std_logic_vector(29 DOWNTO 0);
+ VARIABLE mw_I4sum : signed(29 DOWNTO 0);
+ VARIABLE mw_I4carry : std_logic;
+ BEGIN
+ mw_I4t0 := A_inv(28) & A_inv;
+ mw_I4t1 := B_inv(28) & B_inv;
+ mw_I4carry := cin;
+ mw_I4sum := signed(mw_I4t0) + signed(mw_I4t1) + mw_I4carry;
+ add_out_int <= conv_std_logic_vector(mw_I4sum(28 DOWNTO 0),29);
+ END PROCESS I4combo;
+
+ -- Instance port mappings.
+ I14 : FPinvert
+ GENERIC MAP (
+ width => 29
+ )
+ PORT MAP (
+ A_in => A_align,
+ B_in => B_align,
+ invert_A => invert_A,
+ invert_B => invert_B,
+ A_out => A_inv,
+ B_out => B_inv
+ );
+
+END struct;
Index: fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage4_struct.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage4_struct.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage4_struct.vhd (revision 5)
@@ -0,0 +1,193 @@
+-- VHDL Entity work.FPadd_stage4.interface
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPadd_stage4 IS
+ PORT(
+ A_SIGN_stage3 : IN std_logic;
+ B_XSIGN_stage3 : IN std_logic;
+ EXP_base : IN std_logic_vector (7 DOWNTO 0);
+ add_out : IN std_logic_vector (28 DOWNTO 0);
+ clk : IN std_logic;
+ isINF_tab_stage3 : IN std_logic;
+ isNaN_stage3 : IN std_logic;
+ isZ_tab_stage3 : IN std_logic;
+ EXP_norm : OUT std_logic_vector (7 DOWNTO 0);
+ OV_stage4 : OUT std_logic;
+ SIG_norm : OUT std_logic_vector (27 DOWNTO 0);
+ Z_SIGN_stage4 : OUT std_logic;
+ isINF_tab_stage4 : OUT std_logic;
+ isNaN_stage4 : OUT std_logic;
+ isZ_tab_stage4 : OUT std_logic;
+ zero_stage4 : OUT std_logic
+ );
+
+-- Declarations
+
+END FPadd_stage4 ;
+
+--
+-- VHDL Architecture work.FPadd_stage4.struct
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ARCHITECTURE struct OF FPadd_stage4 IS
+
+ -- Architecture declarations
+ -- Non hierarchical truthtable declarations
+
+
+
+ -- Internal signal declarations
+ SIGNAL EXP_norm_int : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_selC : std_logic_vector(7 DOWNTO 0);
+ SIGNAL OV : std_logic;
+ SIGNAL SIG_norm_int : std_logic_vector(27 DOWNTO 0);
+ SIGNAL SIG_selC : std_logic_vector(27 DOWNTO 0);
+ SIGNAL Z_SIGN : std_logic;
+ SIGNAL add_out_sign : std_logic;
+ SIGNAL zero : std_logic;
+
+
+ -- Component Declarations
+ COMPONENT FPadd_normalize
+ PORT (
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_in : IN std_logic_vector (27 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (27 DOWNTO 0);
+ zero : OUT std_logic
+ );
+ END COMPONENT;
+ COMPONENT FPselComplement
+ GENERIC (
+ SIG_width : integer := 28
+ );
+ PORT (
+ SIG_in : IN std_logic_vector (SIG_width DOWNTO 0);
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : FPadd_normalize USE ENTITY work.FPadd_normalize;
+ FOR ALL : FPselComplement USE ENTITY work.FPselComplement;
+ -- pragma synthesis_on
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 2 eb2
+ -- reg1 1
+ PROCESS(clk)
+ BEGIN
+ IF RISING_EDGE(clk) THEN
+ Z_SIGN_stage4 <= Z_SIGN;
+ OV_stage4 <= OV;
+ EXP_norm <= EXP_norm_int;
+ SIG_norm <= SIG_norm_int;
+ zero_stage4 <= zero;
+ isINF_tab_stage4 <= isINF_tab_stage3;
+ isNaN_stage4 <= isNaN_stage3;
+ isZ_tab_stage4 <= isZ_tab_stage3;
+ END IF;
+ END PROCESS;
+
+ -- HDL Embedded Text Block 4 eb4
+ -- eb4 4
+ add_out_sign <= add_out(28);
+
+ -- HDL Embedded Block 6 SignLogic
+ -- Non hierarchical truthtable
+ ---------------------------------------------------------------------------
+ SignLogic_truth_process: PROCESS(A_SIGN_stage3, B_XSIGN_stage3, add_out_sign)
+ ---------------------------------------------------------------------------
+ VARIABLE b1_A_SIGN_stage3B_XSIGN_stage3add_out_sign : std_logic_vector(2 DOWNTO 0);
+ BEGIN
+ -- Block 1
+ b1_A_SIGN_stage3B_XSIGN_stage3add_out_sign := A_SIGN_stage3 & B_XSIGN_stage3 & add_out_sign;
+
+ CASE b1_A_SIGN_stage3B_XSIGN_stage3add_out_sign IS
+ WHEN "000" =>
+ OV <= '0';
+ Z_SIGN <= '0';
+ WHEN "001" =>
+ OV <= '1';
+ Z_SIGN <= '0';
+ WHEN "010" =>
+ OV <= '0';
+ Z_SIGN <= '0';
+ WHEN "011" =>
+ OV <= '0';
+ Z_SIGN <= '1';
+ WHEN "100" =>
+ OV <= '0';
+ Z_SIGN <= '0';
+ WHEN "101" =>
+ OV <= '0';
+ Z_SIGN <= '1';
+ WHEN "110" =>
+ OV <= '0';
+ Z_SIGN <= '1';
+ WHEN "111" =>
+ OV <= '1';
+ Z_SIGN <= '1';
+ WHEN OTHERS =>
+ OV <= '0';
+ Z_SIGN <= '0';
+ END CASE;
+
+ END PROCESS SignLogic_truth_process;
+
+ -- Architecture concurrent statements
+
+
+
+
+ -- Instance port mappings.
+ I8 : FPadd_normalize
+ PORT MAP (
+ EXP_in => EXP_selC,
+ SIG_in => SIG_selC,
+ EXP_out => EXP_norm_int,
+ SIG_out => SIG_norm_int,
+ zero => zero
+ );
+ I12 : FPselComplement
+ GENERIC MAP (
+ SIG_width => 28
+ )
+ PORT MAP (
+ SIG_in => add_out,
+ EXP_in => EXP_base,
+ SIG_out => SIG_selC,
+ EXP_out => EXP_selC
+ );
+
+END struct;
Index: fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage5_struct.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage5_struct.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage5_struct.vhd (revision 5)
@@ -0,0 +1,141 @@
+-- VHDL Entity work.FPadd_stage5.interface
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPadd_stage5 IS
+ PORT(
+ EXP_norm : IN std_logic_vector (7 DOWNTO 0);
+ OV_stage4 : IN std_logic;
+ SIG_norm : IN std_logic_vector (27 DOWNTO 0);
+ Z_SIGN_stage4 : IN std_logic;
+ clk : IN std_logic;
+ isINF_tab_stage4 : IN std_logic;
+ isNaN_stage4 : IN std_logic;
+ isZ_tab_stage4 : IN std_logic;
+ zero_stage4 : IN std_logic;
+ OV : OUT std_logic;
+ SIG_norm2 : OUT std_logic_vector (27 DOWNTO 0);
+ Z_EXP : OUT std_logic_vector (7 DOWNTO 0);
+ Z_SIGN : OUT std_logic;
+ isINF_tab : OUT std_logic;
+ isNaN : OUT std_logic;
+ isZ_tab : OUT std_logic;
+ zero : OUT std_logic
+ );
+
+-- Declarations
+
+END FPadd_stage5 ;
+
+--
+-- VHDL Architecture work.FPadd_stage5.struct
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ARCHITECTURE struct OF FPadd_stage5 IS
+
+ -- Architecture declarations
+
+ -- Internal signal declarations
+ SIGNAL EXP_round_int : std_logic_vector(7 DOWNTO 0);
+ SIGNAL SIG_norm2_int : std_logic_vector(27 DOWNTO 0);
+ SIGNAL SIG_round_int : std_logic_vector(27 DOWNTO 0);
+ SIGNAL Z_EXP_int : std_logic_vector(7 DOWNTO 0);
+
+
+ -- Component Declarations
+ COMPONENT FPnormalize
+ GENERIC (
+ SIG_width : integer := 28
+ );
+ PORT (
+ SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0)
+ );
+ END COMPONENT;
+ COMPONENT FPround
+ GENERIC (
+ SIG_width : integer := 28
+ );
+ PORT (
+ SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
+ FOR ALL : FPround USE ENTITY work.FPround;
+ -- pragma synthesis_on
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 eb1
+ --reg1 1
+ PROCESS(clk)
+ BEGIN
+ IF RISING_EDGE(clk) THEN
+ Z_EXP <= Z_EXP_int;
+ SIG_norm2 <= SIG_norm2_int;
+ Z_SIGN <= Z_SIGN_stage4;
+ OV <= OV_stage4;
+ zero <= zero_stage4;
+ isINF_tab <= isINF_tab_stage4;
+ isNaN <= isNaN_stage4;
+ isZ_tab <= isZ_tab_stage4;
+ END IF;
+ END PROCESS;
+
+
+ -- Instance port mappings.
+ I11 : FPnormalize
+ GENERIC MAP (
+ SIG_width => 28
+ )
+ PORT MAP (
+ SIG_in => SIG_round_int,
+ EXP_in => EXP_round_int,
+ SIG_out => SIG_norm2_int,
+ EXP_out => Z_EXP_int
+ );
+ I10 : FPround
+ GENERIC MAP (
+ SIG_width => 28
+ )
+ PORT MAP (
+ SIG_in => SIG_norm,
+ EXP_in => EXP_norm,
+ SIG_out => SIG_round_int,
+ EXP_out => EXP_round_int
+ );
+
+END struct;
Index: fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage6_struct.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage6_struct.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/adder/fpadd_stage6_struct.vhd (revision 5)
@@ -0,0 +1,120 @@
+-- VHDL Entity work.FPadd_stage6.interface
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPadd_stage6 IS
+ PORT(
+ OV : IN std_logic;
+ SIG_norm2 : IN std_logic_vector (27 DOWNTO 0);
+ Z_EXP : IN std_logic_vector (7 DOWNTO 0);
+ Z_SIGN : IN std_logic;
+ clk : IN std_logic;
+ isINF_tab : IN std_logic;
+ isNaN : IN std_logic;
+ isZ_tab : IN std_logic;
+ zero : IN std_logic;
+ FP_Z : OUT std_logic_vector (31 DOWNTO 0)
+ );
+
+-- Declarations
+
+END FPadd_stage6 ;
+
+--
+-- VHDL Architecture work.FPadd_stage6.struct
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ARCHITECTURE struct OF FPadd_stage6 IS
+
+ -- Architecture declarations
+
+ -- Internal signal declarations
+ SIGNAL EXP_isINF : std_logic;
+ SIGNAL FP_Z_int : std_logic_vector(31 DOWNTO 0);
+ SIGNAL Z_SIG : std_logic_vector(22 DOWNTO 0);
+ SIGNAL isINF : std_logic;
+ SIGNAL isZ : std_logic;
+
+
+ -- Component Declarations
+ COMPONENT PackFP
+ PORT (
+ SIGN : IN std_logic ;
+ EXP : IN std_logic_vector (7 DOWNTO 0);
+ SIG : IN std_logic_vector (22 DOWNTO 0);
+ isNaN : IN std_logic ;
+ isINF : IN std_logic ;
+ isZ : IN std_logic ;
+ FP : OUT std_logic_vector (31 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : PackFP USE ENTITY work.PackFP;
+ -- pragma synthesis_on
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 eb1
+ --reg1 1
+ PROCESS(clk)
+ BEGIN
+ IF RISING_EDGE(clk) THEN
+ FP_Z <= FP_Z_int;
+ END IF;
+ END PROCESS;
+
+ -- HDL Embedded Text Block 2 eb2
+ -- eb2 2
+ Z_SIG <= SIG_norm2(25 DOWNTO 3);
+
+ -- HDL Embedded Text Block 9 eb7
+ -- eb7 9
+ EXP_isINF <= '1' WHEN (OV='1' OR Z_EXP=X"FF") ELSE '0';
+
+
+ -- ModuleWare code(v1.1) for instance 'I7' of 'or'
+ isINF <= EXP_isINF OR isINF_tab;
+
+ -- ModuleWare code(v1.1) for instance 'I17' of 'or'
+ isZ <= zero OR isZ_tab;
+
+ -- Instance port mappings.
+ I2 : PackFP
+ PORT MAP (
+ SIGN => Z_SIGN,
+ EXP => Z_EXP,
+ SIG => Z_SIG,
+ isNaN => isNaN,
+ isINF => isINF,
+ isZ => isZ,
+ FP => FP_Z_int
+ );
+
+END struct;
Index: fpuvhdl/trunk/fpuvhdl/adder/fpadd_single_cycle.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/adder/fpadd_single_cycle.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/adder/fpadd_single_cycle.vhd (revision 5)
@@ -0,0 +1,556 @@
+-- VHDL Entity work.FPadd.symbol
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPadd IS
+ PORT(
+ ADD_SUB : IN std_logic;
+ FP_A : IN std_logic_vector (31 DOWNTO 0);
+ FP_B : IN std_logic_vector (31 DOWNTO 0);
+ clk : IN std_logic;
+ FP_Z : OUT std_logic_vector (31 DOWNTO 0)
+ );
+
+-- Declarations
+
+END FPadd ;
+
+--
+-- VHDL Architecture work.FPadd.single_cycle
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ARCHITECTURE single_cycle OF FPadd IS
+
+ -- Architecture declarations
+ -- Non hierarchical truthtable declarations
+
+
+ -- Non hierarchical truthtable declarations
+
+
+ -- Non hierarchical truthtable declarations
+
+
+
+ -- Internal signal declarations
+ SIGNAL A_CS : std_logic_vector(28 DOWNTO 0);
+ SIGNAL A_EXP : std_logic_vector(7 DOWNTO 0);
+ SIGNAL A_SIG : std_logic_vector(31 DOWNTO 0);
+ SIGNAL A_SIGN : std_logic;
+ SIGNAL A_in : std_logic_vector(28 DOWNTO 0);
+ SIGNAL A_isDN : std_logic;
+ SIGNAL A_isINF : std_logic;
+ SIGNAL A_isNaN : std_logic;
+ SIGNAL A_isZ : std_logic;
+ SIGNAL B_CS : std_logic_vector(28 DOWNTO 0);
+ SIGNAL B_EXP : std_logic_vector(7 DOWNTO 0);
+ SIGNAL B_SIG : std_logic_vector(31 DOWNTO 0);
+ SIGNAL B_SIGN : std_logic;
+ SIGNAL B_XSIGN : std_logic;
+ SIGNAL B_in : std_logic_vector(28 DOWNTO 0);
+ SIGNAL B_isDN : std_logic;
+ SIGNAL B_isINF : std_logic;
+ SIGNAL B_isNaN : std_logic;
+ SIGNAL B_isZ : std_logic;
+ SIGNAL EXP_base : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_diff : std_logic_vector(8 DOWNTO 0);
+ SIGNAL EXP_isINF : std_logic;
+ SIGNAL EXP_norm : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_round : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_selC : std_logic_vector(7 DOWNTO 0);
+ SIGNAL OV : std_logic;
+ SIGNAL SIG_norm : std_logic_vector(27 DOWNTO 0);
+ SIGNAL SIG_norm2 : std_logic_vector(27 DOWNTO 0);
+ SIGNAL SIG_round : std_logic_vector(27 DOWNTO 0);
+ SIGNAL SIG_selC : std_logic_vector(27 DOWNTO 0);
+ SIGNAL Z_EXP : std_logic_vector(7 DOWNTO 0);
+ SIGNAL Z_SIG : std_logic_vector(22 DOWNTO 0);
+ SIGNAL Z_SIGN : std_logic;
+ SIGNAL a_align : std_logic_vector(28 DOWNTO 0);
+ SIGNAL a_exp_in : std_logic_vector(8 DOWNTO 0);
+ SIGNAL a_inv : std_logic_vector(28 DOWNTO 0);
+ SIGNAL add_out : std_logic_vector(28 DOWNTO 0);
+ SIGNAL b_align : std_logic_vector(28 DOWNTO 0);
+ SIGNAL b_exp_in : std_logic_vector(8 DOWNTO 0);
+ SIGNAL b_inv : std_logic_vector(28 DOWNTO 0);
+ SIGNAL cin : std_logic;
+ SIGNAL cin_sub : std_logic;
+ SIGNAL invert_A : std_logic;
+ SIGNAL invert_B : std_logic;
+ SIGNAL isINF : std_logic;
+ SIGNAL isINF_tab : std_logic;
+ SIGNAL isNaN : std_logic;
+ SIGNAL isZ : std_logic;
+ SIGNAL isZ_tab : std_logic;
+ SIGNAL mux_sel : std_logic;
+ SIGNAL zero : std_logic;
+
+
+ -- ModuleWare signal declarations(v1.1) for instance 'I13' of 'mux'
+ SIGNAL mw_I13din0 : std_logic_vector(7 DOWNTO 0);
+ SIGNAL mw_I13din1 : std_logic_vector(7 DOWNTO 0);
+
+ -- Component Declarations
+ COMPONENT FPadd_normalize
+ PORT (
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_in : IN std_logic_vector (27 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (27 DOWNTO 0);
+ zero : OUT std_logic
+ );
+ END COMPONENT;
+ COMPONENT FPalign
+ PORT (
+ A_in : IN std_logic_vector (28 DOWNTO 0);
+ B_in : IN std_logic_vector (28 DOWNTO 0);
+ cin : IN std_logic ;
+ diff : IN std_logic_vector (8 DOWNTO 0);
+ A_out : OUT std_logic_vector (28 DOWNTO 0);
+ B_out : OUT std_logic_vector (28 DOWNTO 0)
+ );
+ END COMPONENT;
+ COMPONENT FPinvert
+ GENERIC (
+ width : integer := 29
+ );
+ PORT (
+ A_in : IN std_logic_vector (width-1 DOWNTO 0);
+ B_in : IN std_logic_vector (width-1 DOWNTO 0);
+ invert_A : IN std_logic ;
+ invert_B : IN std_logic ;
+ A_out : OUT std_logic_vector (width-1 DOWNTO 0);
+ B_out : OUT std_logic_vector (width-1 DOWNTO 0)
+ );
+ END COMPONENT;
+ COMPONENT FPnormalize
+ GENERIC (
+ SIG_width : integer := 28
+ );
+ PORT (
+ SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0)
+ );
+ END COMPONENT;
+ COMPONENT FPround
+ GENERIC (
+ SIG_width : integer := 28
+ );
+ PORT (
+ SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0)
+ );
+ END COMPONENT;
+ COMPONENT FPselComplement
+ GENERIC (
+ SIG_width : integer := 28
+ );
+ PORT (
+ SIG_in : IN std_logic_vector (SIG_width DOWNTO 0);
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0)
+ );
+ END COMPONENT;
+ COMPONENT FPswap
+ GENERIC (
+ width : integer := 29
+ );
+ PORT (
+ A_in : IN std_logic_vector (width-1 DOWNTO 0);
+ B_in : IN std_logic_vector (width-1 DOWNTO 0);
+ swap_AB : IN std_logic ;
+ A_out : OUT std_logic_vector (width-1 DOWNTO 0);
+ B_out : OUT std_logic_vector (width-1 DOWNTO 0)
+ );
+ END COMPONENT;
+ COMPONENT PackFP
+ PORT (
+ SIGN : IN std_logic ;
+ EXP : IN std_logic_vector (7 DOWNTO 0);
+ SIG : IN std_logic_vector (22 DOWNTO 0);
+ isNaN : IN std_logic ;
+ isINF : IN std_logic ;
+ isZ : IN std_logic ;
+ FP : OUT std_logic_vector (31 DOWNTO 0)
+ );
+ END COMPONENT;
+ COMPONENT UnpackFP
+ PORT (
+ FP : IN std_logic_vector (31 DOWNTO 0);
+ SIG : OUT std_logic_vector (31 DOWNTO 0);
+ EXP : OUT std_logic_vector (7 DOWNTO 0);
+ SIGN : OUT std_logic ;
+ isNaN : OUT std_logic ;
+ isINF : OUT std_logic ;
+ isZ : OUT std_logic ;
+ isDN : OUT std_logic
+ );
+ END COMPONENT;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : FPadd_normalize USE ENTITY work.FPadd_normalize;
+ FOR ALL : FPalign USE ENTITY work.FPalign;
+ FOR ALL : FPinvert USE ENTITY work.FPinvert;
+ FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
+ FOR ALL : FPround USE ENTITY work.FPround;
+ FOR ALL : FPselComplement USE ENTITY work.FPselComplement;
+ FOR ALL : FPswap USE ENTITY work.FPswap;
+ FOR ALL : PackFP USE ENTITY work.PackFP;
+ FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
+ -- pragma synthesis_on
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 eb1
+ -- eb1 1
+ cin_sub <= (A_isDN OR A_isZ) XOR
+ (B_isDN OR B_isZ);
+
+ -- HDL Embedded Text Block 2 eb2
+ -- eb2 2
+ Z_SIG <= SIG_norm2(25 DOWNTO 3);
+
+ -- HDL Embedded Block 3 eb3
+ -- Non hierarchical truthtable
+ ---------------------------------------------------------------------------
+ eb3_truth_process: PROCESS(ADD_SUB, A_isINF, A_isNaN, A_isZ, B_isINF, B_isNaN, B_isZ)
+ ---------------------------------------------------------------------------
+ BEGIN
+ -- Block 1
+ IF (A_isNaN = '1') THEN
+ isINF_tab <= '0';
+ isNaN <= '1';
+ isZ_tab <= '0';
+ ELSIF (B_isNaN = '1') THEN
+ isINF_tab <= '0';
+ isNaN <= '1';
+ isZ_tab <= '0';
+ ELSIF (ADD_SUB = '1') AND (A_isINF = '1') AND (B_isINF = '1') THEN
+ isINF_tab <= '1';
+ isNaN <= '0';
+ isZ_tab <= '0';
+ ELSIF (ADD_SUB = '0') AND (A_isINF = '1') AND (B_isINF = '1') THEN
+ isINF_tab <= '0';
+ isNaN <= '1';
+ isZ_tab <= '0';
+ ELSIF (A_isINF = '1') THEN
+ isINF_tab <= '1';
+ isNaN <= '0';
+ isZ_tab <= '0';
+ ELSIF (B_isINF = '1') THEN
+ isINF_tab <= '1';
+ isNaN <= '0';
+ isZ_tab <= '0';
+ ELSIF (A_isZ = '1') AND (B_isZ = '1') THEN
+ isINF_tab <= '0';
+ isNaN <= '0';
+ isZ_tab <= '1';
+ ELSE
+ isINF_tab <= '0';
+ isNaN <= '0';
+ isZ_tab <= '0';
+ END IF;
+
+ END PROCESS eb3_truth_process;
+
+ -- Architecture concurrent statements
+
+
+
+ -- HDL Embedded Text Block 4 eb4
+ -- eb4 4
+ mux_sel <= EXP_diff(8);
+
+ -- HDL Embedded Block 5 InvertLogic
+ -- Non hierarchical truthtable
+ ---------------------------------------------------------------------------
+ InvertLogic_truth_process: PROCESS(A_SIGN, B_XSIGN, EXP_diff)
+ ---------------------------------------------------------------------------
+ BEGIN
+ -- Block 1
+ IF (A_SIGN = '0') AND (B_XSIGN = '0') THEN
+ invert_A <= '0';
+ invert_B <= '0';
+ ELSIF (A_SIGN = '1') AND (B_XSIGN = '1') THEN
+ invert_A <= '0';
+ invert_B <= '0';
+ ELSIF (A_SIGN = '0') AND (B_XSIGN = '1') AND (EXP_diff(8) = '0') THEN
+ invert_A <= '0';
+ invert_B <= '1';
+ ELSIF (A_SIGN = '0') AND (B_XSIGN = '1') AND (EXP_diff(8) = '1') THEN
+ invert_A <= '1';
+ invert_B <= '0';
+ ELSIF (A_SIGN = '1') AND (B_XSIGN = '0') AND (EXP_diff(8) = '0') THEN
+ invert_A <= '1';
+ invert_B <= '0';
+ ELSIF (A_SIGN = '1') AND (B_XSIGN = '0') AND (EXP_diff(8) = '1') THEN
+ invert_A <= '0';
+ invert_B <= '1';
+ ELSE
+ invert_A <= '0';
+ invert_B <= '0';
+ END IF;
+
+ END PROCESS InvertLogic_truth_process;
+
+ -- Architecture concurrent statements
+
+
+
+ -- HDL Embedded Block 6 SignLogic
+ -- Non hierarchical truthtable
+ ---------------------------------------------------------------------------
+ SignLogic_truth_process: PROCESS(A_SIGN, B_XSIGN, add_out)
+ ---------------------------------------------------------------------------
+ VARIABLE b1_A_SIGNB_XSIGNadd_out_28 : std_logic_vector(2 DOWNTO 0);
+ BEGIN
+ -- Block 1
+ b1_A_SIGNB_XSIGNadd_out_28 := A_SIGN & B_XSIGN & add_out(28);
+
+ CASE b1_A_SIGNB_XSIGNadd_out_28 IS
+ WHEN "000" =>
+ OV <= '0';
+ Z_SIGN <= '0';
+ WHEN "001" =>
+ OV <= '1';
+ Z_SIGN <= '0';
+ WHEN "010" =>
+ OV <= '0';
+ Z_SIGN <= '0';
+ WHEN "011" =>
+ OV <= '0';
+ Z_SIGN <= '1';
+ WHEN "100" =>
+ OV <= '0';
+ Z_SIGN <= '0';
+ WHEN "101" =>
+ OV <= '0';
+ Z_SIGN <= '1';
+ WHEN "110" =>
+ OV <= '0';
+ Z_SIGN <= '1';
+ WHEN "111" =>
+ OV <= '1';
+ Z_SIGN <= '1';
+ WHEN OTHERS =>
+ OV <= '0';
+ Z_SIGN <= '0';
+ END CASE;
+
+ END PROCESS SignLogic_truth_process;
+
+ -- Architecture concurrent statements
+
+
+
+ -- HDL Embedded Text Block 7 eb5
+ -- eb5 7
+ A_in <= "00" & A_SIG(23 DOWNTO 0) & "000";
+
+ -- HDL Embedded Text Block 8 eb6
+ -- eb6 8
+ B_in <= "00" & B_SIG(23 DOWNTO 0) & "000";
+
+ -- HDL Embedded Text Block 9 eb7
+ -- eb7 9
+ EXP_isINF <= '1' WHEN (OV='1' OR Z_EXP=X"FF") ELSE '0';
+
+ -- HDL Embedded Text Block 10 eb8
+ -- eb8 10
+ a_exp_in <= "0" & A_EXP;
+
+ -- HDL Embedded Text Block 11 eb9
+ -- eb9 11
+ b_exp_in <= "0" & B_EXP;
+
+
+ -- ModuleWare code(v1.1) for instance 'I4' of 'add'
+ I4combo: PROCESS (a_inv, b_inv, cin)
+ VARIABLE mw_I4t0 : std_logic_vector(29 DOWNTO 0);
+ VARIABLE mw_I4t1 : std_logic_vector(29 DOWNTO 0);
+ VARIABLE mw_I4sum : signed(29 DOWNTO 0);
+ VARIABLE mw_I4carry : std_logic;
+ BEGIN
+ mw_I4t0 := a_inv(28) & a_inv;
+ mw_I4t1 := b_inv(28) & b_inv;
+ mw_I4carry := cin;
+ mw_I4sum := signed(mw_I4t0) + signed(mw_I4t1) + mw_I4carry;
+ add_out <= conv_std_logic_vector(mw_I4sum(28 DOWNTO 0),29);
+ END PROCESS I4combo;
+
+ -- ModuleWare code(v1.1) for instance 'I13' of 'mux'
+ I13combo: PROCESS(mw_I13din0, mw_I13din1, mux_sel)
+ VARIABLE dtemp : std_logic_vector(7 DOWNTO 0);
+ BEGIN
+ CASE mux_sel IS
+ WHEN '0'|'L' => dtemp := mw_I13din0;
+ WHEN '1'|'H' => dtemp := mw_I13din1;
+ WHEN OTHERS => dtemp := (OTHERS => 'X');
+ END CASE;
+ EXP_base <= dtemp;
+ END PROCESS I13combo;
+ mw_I13din0 <= A_EXP;
+ mw_I13din1 <= B_EXP;
+
+ -- ModuleWare code(v1.1) for instance 'I7' of 'or'
+ isINF <= EXP_isINF OR isINF_tab;
+
+ -- ModuleWare code(v1.1) for instance 'I15' of 'or'
+ cin <= invert_B OR invert_A;
+
+ -- ModuleWare code(v1.1) for instance 'I17' of 'or'
+ isZ <= zero OR isZ_tab;
+
+ -- ModuleWare code(v1.1) for instance 'I3' of 'sub'
+ I3combo: PROCESS (a_exp_in, b_exp_in, cin_sub)
+ VARIABLE mw_I3t0 : std_logic_vector(9 DOWNTO 0);
+ VARIABLE mw_I3t1 : std_logic_vector(9 DOWNTO 0);
+ VARIABLE diff : signed(9 DOWNTO 0);
+ VARIABLE borrow : std_logic;
+ BEGIN
+ mw_I3t0 := a_exp_in(8) & a_exp_in;
+ mw_I3t1 := b_exp_in(8) & b_exp_in;
+ borrow := cin_sub;
+ diff := signed(mw_I3t0) - signed(mw_I3t1) - borrow;
+ EXP_diff <= conv_std_logic_vector(diff(8 DOWNTO 0),9);
+ END PROCESS I3combo;
+
+ -- ModuleWare code(v1.1) for instance 'I16' of 'xnor'
+ B_XSIGN <= NOT(B_SIGN XOR ADD_SUB);
+
+ -- Instance port mappings.
+ I8 : FPadd_normalize
+ PORT MAP (
+ EXP_in => EXP_selC,
+ SIG_in => SIG_selC,
+ EXP_out => EXP_norm,
+ SIG_out => SIG_norm,
+ zero => zero
+ );
+ I6 : FPalign
+ PORT MAP (
+ A_in => A_CS,
+ B_in => B_CS,
+ cin => cin_sub,
+ diff => EXP_diff,
+ A_out => a_align,
+ B_out => b_align
+ );
+ I14 : FPinvert
+ GENERIC MAP (
+ width => 29
+ )
+ PORT MAP (
+ A_in => a_align,
+ B_in => b_align,
+ invert_A => invert_A,
+ invert_B => invert_B,
+ A_out => a_inv,
+ B_out => b_inv
+ );
+ I11 : FPnormalize
+ GENERIC MAP (
+ SIG_width => 28
+ )
+ PORT MAP (
+ SIG_in => SIG_round,
+ EXP_in => EXP_round,
+ SIG_out => SIG_norm2,
+ EXP_out => Z_EXP
+ );
+ I10 : FPround
+ GENERIC MAP (
+ SIG_width => 28
+ )
+ PORT MAP (
+ SIG_in => SIG_norm,
+ EXP_in => EXP_norm,
+ SIG_out => SIG_round,
+ EXP_out => EXP_round
+ );
+ I12 : FPselComplement
+ GENERIC MAP (
+ SIG_width => 28
+ )
+ PORT MAP (
+ SIG_in => add_out,
+ EXP_in => EXP_base,
+ SIG_out => SIG_selC,
+ EXP_out => EXP_selC
+ );
+ I5 : FPswap
+ GENERIC MAP (
+ width => 29
+ )
+ PORT MAP (
+ A_in => A_in,
+ B_in => B_in,
+ swap_AB => EXP_diff(8),
+ A_out => A_CS,
+ B_out => B_CS
+ );
+ I2 : PackFP
+ PORT MAP (
+ SIGN => Z_SIGN,
+ EXP => Z_EXP,
+ SIG => Z_SIG,
+ isNaN => isNaN,
+ isINF => isINF,
+ isZ => isZ,
+ FP => FP_Z
+ );
+ I0 : UnpackFP
+ PORT MAP (
+ FP => FP_A,
+ SIG => A_SIG,
+ EXP => A_EXP,
+ SIGN => A_SIGN,
+ isNaN => A_isNaN,
+ isINF => A_isINF,
+ isZ => A_isZ,
+ isDN => A_isDN
+ );
+ I1 : UnpackFP
+ PORT MAP (
+ FP => FP_B,
+ SIG => B_SIG,
+ EXP => B_EXP,
+ SIGN => B_SIGN,
+ isNaN => B_isNaN,
+ isINF => B_isINF,
+ isZ => B_isZ,
+ isDN => B_isDN
+ );
+
+END single_cycle;
Index: fpuvhdl/trunk/fpuvhdl/adder/fpswap_fpswap.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/adder/fpswap_fpswap.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/adder/fpswap_fpswap.vhd (revision 5)
@@ -0,0 +1,49 @@
+--
+-- VHDL Architecture HAVOC.FPswap.FPswap
+--
+-- Created:
+-- by - Guillermo
+-- at - ITESM, 20:19:07 07/19/03
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
+--
+-- hds interface_start
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+
+ENTITY FPswap IS
+ GENERIC(
+ width : integer := 29
+ );
+ PORT(
+ A_in : IN std_logic_vector (width-1 DOWNTO 0);
+ B_in : IN std_logic_vector (width-1 DOWNTO 0);
+ swap_AB : IN std_logic;
+ A_out : OUT std_logic_vector (width-1 DOWNTO 0);
+ B_out : OUT std_logic_vector (width-1 DOWNTO 0)
+ );
+
+-- Declarations
+
+END FPswap ;
+
+
+-- hds interface_end
+ARCHITECTURE FPswap OF FPswap IS
+BEGIN
+
+PROCESS(A_in, B_in, swap_AB)
+BEGIN
+ IF (swap_AB='1') THEN
+ A_out <= B_in;
+ B_out <= A_in;
+ ELSE
+ A_out <= A_in;
+ B_out <= B_in;
+ END IF;
+END PROCESS;
+
+END FPswap;
+
Index: fpuvhdl/trunk/fpuvhdl/adder/fpalign_struct.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/adder/fpalign_struct.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/adder/fpalign_struct.vhd (revision 5)
@@ -0,0 +1,142 @@
+-- VHDL Entity HAVOC.FPalign.symbol
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPalign IS
+ PORT(
+ A_in : IN std_logic_vector (28 DOWNTO 0);
+ B_in : IN std_logic_vector (28 DOWNTO 0);
+ cin : IN std_logic;
+ diff : IN std_logic_vector (8 DOWNTO 0);
+ A_out : OUT std_logic_vector (28 DOWNTO 0);
+ B_out : OUT std_logic_vector (28 DOWNTO 0)
+ );
+
+-- Declarations
+
+END FPalign ;
+
+--
+-- VHDL Architecture HAVOC.FPalign.struct
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+
+ARCHITECTURE struct OF FPalign IS
+
+ -- Architecture declarations
+
+ -- Internal signal declarations
+ SIGNAL B_shift : std_logic_vector(28 DOWNTO 0);
+ SIGNAL diff_int : std_logic_vector(8 DOWNTO 0);
+ SIGNAL shift_B : std_logic_vector(5 DOWNTO 0);
+
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 eb1
+ -- eb1 1
+ PROCESS(diff_int, B_shift)
+ BEGIN
+ IF (diff_int(8)='1') THEN
+ IF (((NOT diff_int) + 1) > 28) THEN
+ B_out <= (OTHERS => '0');
+ ELSE
+ B_out <= B_shift;
+ END IF;
+ ELSE
+ IF (diff_int > 28) THEN
+ B_out <= (OTHERS => '0');
+ ELSE
+ B_out <= B_shift;
+ END IF;
+ END IF;
+ END PROCESS;
+
+ -- HDL Embedded Text Block 2 eb2
+ -- eb2 2
+ PROCESS(diff_int)
+ BEGIN
+ IF (diff_int(8)='1') THEN
+ shift_B <= (NOT diff_int(5 DOWNTO 0)) + 1;
+ ELSE
+ shift_B <= diff_int(5 DOWNTO 0) ;
+ END IF;
+ END PROCESS;
+
+ -- HDL Embedded Text Block 3 eb3
+ -- eb3 3
+ PROCESS(cin,diff)
+ BEGIN
+ IF ((cin='1') AND (diff(8)='1')) THEN
+ diff_int <= diff + 2;
+ ELSE
+ diff_int <= diff;
+ END IF;
+ END PROCESS;
+
+
+ -- ModuleWare code(v1.1) for instance 'I0' of 'assignment'
+ A_out <= A_in;
+
+ -- ModuleWare code(v1.1) for instance 'I1' of 'rshift'
+ I1combo : PROCESS (B_in, shift_B)
+ VARIABLE stemp : std_logic_vector (5 DOWNTO 0);
+ VARIABLE dtemp : std_logic_vector (28 DOWNTO 0);
+ VARIABLE temp : std_logic_vector (28 DOWNTO 0);
+ BEGIN
+ temp := (OTHERS=> 'X');
+ stemp := shift_B;
+ temp := B_in;
+ FOR i IN 5 DOWNTO 0 LOOP
+ IF (i < 5) THEN
+ IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
+ dtemp := (OTHERS => '0');
+ dtemp(28 - 2**i DOWNTO 0) := temp(28 DOWNTO 2**i);
+ ELSIF (stemp(i) = '0' OR stemp(i) = 'L') THEN
+ dtemp := temp;
+ ELSE
+ dtemp := (OTHERS => 'X');
+ END IF;
+ ELSE
+ IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
+ dtemp := (OTHERS => '0');
+ ELSIF (stemp(i) = '0' OR stemp(i) = 'L') THEN
+ dtemp := temp;
+ ELSE
+ dtemp := (OTHERS => 'X');
+ END IF;
+ END IF;
+ temp := dtemp;
+ END LOOP;
+ B_shift <= dtemp;
+ END PROCESS I1combo;
+
+ -- Instance port mappings.
+
+END struct;
Index: fpuvhdl/trunk/fpuvhdl/adder/fpinvert_fpinvert.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/adder/fpinvert_fpinvert.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/adder/fpinvert_fpinvert.vhd (revision 5)
@@ -0,0 +1,43 @@
+--
+-- VHDL Architecture HAVOC.FPinvert.FPinvert
+--
+-- Created:
+-- by - Guillermo
+-- at - ITESM, 20:19:07 07/19/03
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
+--
+-- hds interface_start
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+
+ENTITY FPinvert IS
+ GENERIC(
+ width : integer := 29
+ );
+ PORT(
+ A_in : IN std_logic_vector (width-1 DOWNTO 0);
+ B_in : IN std_logic_vector (width-1 DOWNTO 0);
+ invert_A : IN std_logic;
+ invert_B : IN std_logic;
+ A_out : OUT std_logic_vector (width-1 DOWNTO 0);
+ B_out : OUT std_logic_vector (width-1 DOWNTO 0)
+ );
+
+-- Declarations
+
+END FPinvert ;
+
+
+-- hds interface_end
+ARCHITECTURE FPinvert OF FPinvert IS
+BEGIN
+
+A_out <= (NOT A_in) WHEN (invert_A='1') ELSE A_in;
+
+B_out <= (NOT B_in) WHEN (invert_B='1') ELSE B_in;
+
+END FPinvert;
+
Index: fpuvhdl/trunk/fpuvhdl/adder/fpselcomplement_fpselcomplement.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/adder/fpselcomplement_fpselcomplement.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/adder/fpselcomplement_fpselcomplement.vhd (revision 5)
@@ -0,0 +1,49 @@
+--
+-- VHDL Architecture HAVOC.FPselComplement.FPselComplement
+--
+-- Created:
+-- by - Guillermo
+-- at - ITESM, 13:02:32 07/17/03
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
+--
+-- hds interface_start
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+
+ENTITY FPselComplement IS
+ GENERIC(
+ SIG_width : integer := 28
+ );
+ PORT(
+ SIG_in : IN std_logic_vector (SIG_width DOWNTO 0);
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0)
+ );
+
+-- Declarations
+
+END FPselComplement ;
+
+
+-- hds interface_end
+ARCHITECTURE FPselComplement OF FPselComplement IS
+BEGIN
+
+ EXP_out <= EXP_in;
+
+ PROCESS(SIG_in)
+ BEGIN
+ IF (SIG_in(SIG_width) = '1') THEN
+ SIG_out <= (NOT SIG_in(SIG_width-1 DOWNTO 0) + 1);
+ ELSE
+ SIG_out <= SIG_in(SIG_width-1 DOWNTO 0);
+ END IF;
+ END PROCESS;
+
+END FPselComplement;
+
Index: fpuvhdl/trunk/fpuvhdl/adder/fplzc_fplzc.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/adder/fplzc_fplzc.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/adder/fplzc_fplzc.vhd (revision 5)
@@ -0,0 +1,72 @@
+--
+-- VHDL Architecture HAVOC.FPlzc.FPlzc
+--
+-- Created:
+-- by - Guillermo
+-- at - ITESM, 08:25:27 07/20/03
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
+--
+-- hds interface_start
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+
+ENTITY FPlzc IS
+ PORT(
+ word : IN std_logic_vector (26 DOWNTO 0);
+ zero : OUT std_logic;
+ count : OUT std_logic_vector (4 DOWNTO 0)
+ );
+
+-- Declarations
+
+END FPlzc ;
+
+
+-- hds interface_end
+ARCHITECTURE FPlzc OF FPlzc IS
+BEGIN
+
+PROCESS(word)
+BEGIN
+ zero <= '0';
+-- IF (word="0000000000000000000000000000") THEN
+-- count <= "11100";
+ IF (word(26 DOWNTO 0)="000000000000000000000000000") THEN
+ count <= "11011";
+ zero <= '1';
+ ELSIF (word(26 DOWNTO 1)="00000000000000000000000000") THEN count <= "11010";
+ ELSIF (word(26 DOWNTO 2)="0000000000000000000000000") THEN count <= "11001";
+ ELSIF (word(26 DOWNTO 3)="000000000000000000000000") THEN count <= "11000";
+ ELSIF (word(26 DOWNTO 4)="00000000000000000000000") THEN count <= "10111";
+ ELSIF (word(26 DOWNTO 5)="0000000000000000000000") THEN count <= "10110";
+ ELSIF (word(26 DOWNTO 6)="000000000000000000000") THEN count <= "10101";
+ ELSIF (word(26 DOWNTO 7)="00000000000000000000") THEN count <= "10100";
+ ELSIF (word(26 DOWNTO 8)="0000000000000000000") THEN count <= "10011";
+ ELSIF (word(26 DOWNTO 9)="000000000000000000") THEN count <= "10010";
+ ELSIF (word(26 DOWNTO 10)="00000000000000000") THEN count <= "10001";
+ ELSIF (word(26 DOWNTO 11)="0000000000000000") THEN count <= "10000";
+ ELSIF (word(26 DOWNTO 12)="000000000000000") THEN count <= "01111";
+ ELSIF (word(26 DOWNTO 13)="00000000000000") THEN count <= "01110";
+ ELSIF (word(26 DOWNTO 14)="0000000000000") THEN count <= "01101";
+ ELSIF (word(26 DOWNTO 15)="000000000000") THEN count <= "01100";
+ ELSIF (word(26 DOWNTO 16)="00000000000") THEN count <= "01011";
+ ELSIF (word(26 DOWNTO 17)="0000000000") THEN count <= "01010";
+ ELSIF (word(26 DOWNTO 18)="000000000") THEN count <= "01001";
+ ELSIF (word(26 DOWNTO 19)="00000000") THEN count <= "01000";
+ ELSIF (word(26 DOWNTO 20)="0000000") THEN count <= "00111";
+ ELSIF (word(26 DOWNTO 21)="000000") THEN count <= "00110";
+ ELSIF (word(26 DOWNTO 22)="00000") THEN count <= "00101";
+ ELSIF (word(26 DOWNTO 23)="0000") THEN count <= "00100";
+ ELSIF (word(26 DOWNTO 24)="000") THEN count <= "00011";
+ ELSIF (word(26 DOWNTO 25)="00") THEN count <= "00010";
+ ELSIF (word(26)='0') THEN count <= "00001";
+ ELSE
+ count <= "00000";
+ END IF;
+END PROCESS;
+
+END FPlzc;
+
Index: fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_single_cycle.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_single_cycle.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_single_cycle.vhd (revision 5)
@@ -0,0 +1,342 @@
+-- VHDL Entity HAVOC.FPmul.symbol
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPmul IS
+ PORT(
+ FP_A : IN std_logic_vector (31 DOWNTO 0);
+ FP_B : IN std_logic_vector (31 DOWNTO 0);
+ clk : IN std_logic;
+ FP_Z : OUT std_logic_vector (31 DOWNTO 0)
+ );
+
+-- Declarations
+
+END FPmul ;
+
+--
+-- VHDL Architecture HAVOC.FPmul.single_cycle
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ARCHITECTURE single_cycle OF FPmul IS
+
+ -- Architecture declarations
+ -- Non hierarchical truthtable declarations
+
+
+
+ -- Internal signal declarations
+ SIGNAL A_EXP : std_logic_vector(7 DOWNTO 0);
+ SIGNAL A_SIG : std_logic_vector(31 DOWNTO 0);
+ SIGNAL A_SIGN : std_logic;
+ SIGNAL A_isINF : std_logic;
+ SIGNAL A_isNaN : std_logic;
+ SIGNAL A_isZ : std_logic;
+ SIGNAL B_EXP : std_logic_vector(7 DOWNTO 0);
+ SIGNAL B_SIG : std_logic_vector(31 DOWNTO 0);
+ SIGNAL B_SIGN : std_logic;
+ SIGNAL B_isINF : std_logic;
+ SIGNAL B_isNaN : std_logic;
+ SIGNAL B_isZ : std_logic;
+ SIGNAL EXP_addout : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_in : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_out : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_out_norm : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_out_round : std_logic_vector(7 DOWNTO 0);
+ SIGNAL SIGN_out : std_logic;
+ SIGNAL SIG_in : std_logic_vector(27 DOWNTO 0);
+ SIGNAL SIG_isZ : std_logic;
+ SIGNAL SIG_out : std_logic_vector(22 DOWNTO 0);
+ SIGNAL SIG_out_norm : std_logic_vector(27 DOWNTO 0);
+ SIGNAL SIG_out_norm2 : std_logic_vector(27 DOWNTO 0);
+ SIGNAL SIG_out_round : std_logic_vector(27 DOWNTO 0);
+ SIGNAL dout : std_logic;
+ SIGNAL isINF : std_logic;
+ SIGNAL isINF_tab : std_logic;
+ SIGNAL isNaN : std_logic;
+ SIGNAL isZ : std_logic;
+ SIGNAL isZ_tab : std_logic;
+ SIGNAL prod : std_logic_vector(63 DOWNTO 0);
+
+
+ -- Component Declarations
+ COMPONENT FPnormalize
+ GENERIC (
+ SIG_width : integer := 28
+ );
+ PORT (
+ SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0)
+ );
+ END COMPONENT;
+ COMPONENT FPround
+ GENERIC (
+ SIG_width : integer := 28
+ );
+ PORT (
+ SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0)
+ );
+ END COMPONENT;
+ COMPONENT PackFP
+ PORT (
+ SIGN : IN std_logic ;
+ EXP : IN std_logic_vector (7 DOWNTO 0);
+ SIG : IN std_logic_vector (22 DOWNTO 0);
+ isNaN : IN std_logic ;
+ isINF : IN std_logic ;
+ isZ : IN std_logic ;
+ FP : OUT std_logic_vector (31 DOWNTO 0)
+ );
+ END COMPONENT;
+ COMPONENT UnpackFP
+ PORT (
+ FP : IN std_logic_vector (31 DOWNTO 0);
+ SIG : OUT std_logic_vector (31 DOWNTO 0);
+ EXP : OUT std_logic_vector (7 DOWNTO 0);
+ SIGN : OUT std_logic ;
+ isNaN : OUT std_logic ;
+ isINF : OUT std_logic ;
+ isZ : OUT std_logic ;
+ isDN : OUT std_logic
+ );
+ END COMPONENT;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
+ FOR ALL : FPround USE ENTITY work.FPround;
+ FOR ALL : PackFP USE ENTITY work.PackFP;
+ FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
+ -- pragma synthesis_on
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 eb1
+ -- eb1 1
+ SIG_in <= prod(47 DOWNTO 20);
+
+ -- HDL Embedded Text Block 2 eb2
+ -- eb2
+
+ SIG_out <= SIG_out_norm2(25 DOWNTO 3);
+
+ -- HDL Embedded Text Block 3 eb3
+ -- eb3 3
+ PROCESS(isZ,isINF_tab, A_EXP, B_EXP, EXP_out)
+ BEGIN
+ IF isZ='0' THEN
+ IF isINF_tab='1' THEN
+ isINF <= '1';
+ ELSIF EXP_out=X"FF" THEN
+ isINF <='1';
+ ELSIF (A_EXP(7)='1' AND B_EXP(7)='1' AND (EXP_out(7)='0')) THEN
+ isINF <='1';
+ ELSE
+ isINF <= '0';
+ END IF;
+ ELSE
+ isINF <= '0';
+ END IF;
+ END PROCESS;
+
+ -- HDL Embedded Block 4 eb4
+ -- Non hierarchical truthtable
+ ---------------------------------------------------------------------------
+ eb4_truth_process: PROCESS(A_isINF, A_isNaN, A_isZ, B_isINF, B_isNaN, B_isZ)
+ ---------------------------------------------------------------------------
+ BEGIN
+ -- Block 1
+ IF (A_isINF = '0') AND (A_isNaN = '0') AND (A_isZ = '0') AND (B_isINF = '0') AND (B_isNaN = '0') AND (B_isZ = '0') THEN
+ isZ_tab <= '0';
+ isINF_tab <= '0';
+ isNaN <= '0';
+ ELSIF (A_isINF = '1') AND (B_isZ = '1') THEN
+ isZ_tab <= '0';
+ isINF_tab <= '0';
+ isNaN <= '1';
+ ELSIF (A_isZ = '1') AND (B_isINF = '1') THEN
+ isZ_tab <= '0';
+ isINF_tab <= '0';
+ isNaN <= '1';
+ ELSIF (A_isINF = '1') THEN
+ isZ_tab <= '0';
+ isINF_tab <= '1';
+ isNaN <= '0';
+ ELSIF (B_isINF = '1') THEN
+ isZ_tab <= '0';
+ isINF_tab <= '1';
+ isNaN <= '0';
+ ELSIF (A_isNaN = '1') THEN
+ isZ_tab <= '0';
+ isINF_tab <= '0';
+ isNaN <= '1';
+ ELSIF (B_isNaN = '1') THEN
+ isZ_tab <= '0';
+ isINF_tab <= '0';
+ isNaN <= '1';
+ ELSIF (A_isZ = '1') THEN
+ isZ_tab <= '1';
+ isINF_tab <= '0';
+ isNaN <= '0';
+ ELSIF (B_isZ = '1') THEN
+ isZ_tab <= '1';
+ isINF_tab <= '0';
+ isNaN <= '0';
+ ELSE
+ isZ_tab <= '0';
+ isINF_tab <= '0';
+ isNaN <= '0';
+ END IF;
+
+ END PROCESS eb4_truth_process;
+
+ -- Architecture concurrent statements
+
+
+
+ -- HDL Embedded Text Block 5 eb5
+ -- eb5 5
+ EXP_in <= (NOT EXP_addout(7)) & EXP_addout(6 DOWNTO 0);
+
+ -- HDL Embedded Text Block 6 eb6
+ -- eb6 6
+ PROCESS(SIG_out_norm2,A_EXP,B_EXP, EXP_out)
+ BEGIN
+ IF ( EXP_out(7)='1' AND
+ ( (A_EXP(7)='0' AND NOT (A_EXP=X"7F")) AND
+ (B_EXP(7)='0' AND NOT (B_EXP=X"7F")) ) ) OR
+ (SIG_out_norm2(26 DOWNTO 3)=X"000000") THEN
+ -- Underflow or zero significand
+ SIG_isZ <= '1';
+ ELSE
+ SIG_isZ <= '0';
+ END IF;
+ END PROCESS;
+
+
+ -- ModuleWare code(v1.1) for instance 'I4' of 'add'
+ I4combo: PROCESS (A_EXP, B_EXP, dout)
+ VARIABLE mw_I4t0 : std_logic_vector(8 DOWNTO 0);
+ VARIABLE mw_I4t1 : std_logic_vector(8 DOWNTO 0);
+ VARIABLE mw_I4sum : unsigned(8 DOWNTO 0);
+ VARIABLE mw_I4carry : std_logic;
+ BEGIN
+ mw_I4t0 := '0' & A_EXP;
+ mw_I4t1 := '0' & B_EXP;
+ mw_I4carry := dout;
+ mw_I4sum := unsigned(mw_I4t0) + unsigned(mw_I4t1) + mw_I4carry;
+ EXP_addout <= conv_std_logic_vector(mw_I4sum(7 DOWNTO 0),8);
+ END PROCESS I4combo;
+
+ -- ModuleWare code(v1.1) for instance 'I2' of 'mult'
+ I2combo : PROCESS (A_SIG, B_SIG)
+ VARIABLE dtemp : unsigned(63 DOWNTO 0);
+ BEGIN
+ dtemp := (unsigned(A_SIG) * unsigned(B_SIG));
+ prod <= std_logic_vector(dtemp);
+ END PROCESS I2combo;
+
+ -- ModuleWare code(v1.1) for instance 'I7' of 'or'
+ isZ <= SIG_isZ OR isZ_tab;
+
+ -- ModuleWare code(v1.1) for instance 'I6' of 'vdd'
+ dout <= '1';
+
+ -- ModuleWare code(v1.1) for instance 'I3' of 'xor'
+ SIGN_out <= A_SIGN XOR B_SIGN;
+
+ -- Instance port mappings.
+ I9 : FPnormalize
+ GENERIC MAP (
+ SIG_width => 28
+ )
+ PORT MAP (
+ SIG_in => SIG_in,
+ EXP_in => EXP_in,
+ SIG_out => SIG_out_norm,
+ EXP_out => EXP_out_norm
+ );
+ I10 : FPnormalize
+ GENERIC MAP (
+ SIG_width => 28
+ )
+ PORT MAP (
+ SIG_in => SIG_out_round,
+ EXP_in => EXP_out_round,
+ SIG_out => SIG_out_norm2,
+ EXP_out => EXP_out
+ );
+ I11 : FPround
+ GENERIC MAP (
+ SIG_width => 28
+ )
+ PORT MAP (
+ SIG_in => SIG_out_norm,
+ EXP_in => EXP_out_norm,
+ SIG_out => SIG_out_round,
+ EXP_out => EXP_out_round
+ );
+ I5 : PackFP
+ PORT MAP (
+ SIGN => SIGN_out,
+ EXP => EXP_out,
+ SIG => SIG_out,
+ isNaN => isNaN,
+ isINF => isINF,
+ isZ => isZ,
+ FP => FP_Z
+ );
+ I0 : UnpackFP
+ PORT MAP (
+ FP => FP_A,
+ SIG => A_SIG,
+ EXP => A_EXP,
+ SIGN => A_SIGN,
+ isNaN => A_isNaN,
+ isINF => A_isINF,
+ isZ => A_isZ,
+ isDN => OPEN
+ );
+ I1 : UnpackFP
+ PORT MAP (
+ FP => FP_B,
+ SIG => B_SIG,
+ EXP => B_EXP,
+ SIGN => B_SIGN,
+ isNaN => B_isNaN,
+ isINF => B_isINF,
+ isZ => B_isZ,
+ isDN => OPEN
+ );
+
+END single_cycle;
Index: fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_pipeline.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_pipeline.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_pipeline.vhd (revision 5)
@@ -0,0 +1,229 @@
+-- VHDL Entity HAVOC.FPmul.symbol
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPmul IS
+ PORT(
+ FP_A : IN std_logic_vector (31 DOWNTO 0);
+ FP_B : IN std_logic_vector (31 DOWNTO 0);
+ clk : IN std_logic;
+ FP_Z : OUT std_logic_vector (31 DOWNTO 0)
+ );
+
+-- Declarations
+
+END FPmul ;
+
+--
+-- VHDL Architecture HAVOC.FPmul.pipeline
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ARCHITECTURE pipeline OF FPmul IS
+
+ -- Architecture declarations
+
+ -- Internal signal declarations
+ SIGNAL A_EXP : std_logic_vector(7 DOWNTO 0);
+ SIGNAL A_SIG : std_logic_vector(31 DOWNTO 0);
+ SIGNAL B_EXP : std_logic_vector(7 DOWNTO 0);
+ SIGNAL B_SIG : std_logic_vector(31 DOWNTO 0);
+ SIGNAL EXP_in : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_neg : std_logic;
+ SIGNAL EXP_neg_stage2 : std_logic;
+ SIGNAL EXP_out_round : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_pos : std_logic;
+ SIGNAL EXP_pos_stage2 : std_logic;
+ SIGNAL SIGN_out : std_logic;
+ SIGNAL SIGN_out_stage1 : std_logic;
+ SIGNAL SIGN_out_stage2 : std_logic;
+ SIGNAL SIG_in : std_logic_vector(27 DOWNTO 0);
+ SIGNAL SIG_out_round : std_logic_vector(27 DOWNTO 0);
+ SIGNAL isINF_stage1 : std_logic;
+ SIGNAL isINF_stage2 : std_logic;
+ SIGNAL isINF_tab : std_logic;
+ SIGNAL isNaN : std_logic;
+ SIGNAL isNaN_stage1 : std_logic;
+ SIGNAL isNaN_stage2 : std_logic;
+ SIGNAL isZ_tab : std_logic;
+ SIGNAL isZ_tab_stage1 : std_logic;
+ SIGNAL isZ_tab_stage2 : std_logic;
+
+
+ -- Component Declarations
+ COMPONENT FPmul_stage1
+ PORT (
+ FP_A : IN std_logic_vector (31 DOWNTO 0);
+ FP_B : IN std_logic_vector (31 DOWNTO 0);
+ clk : IN std_logic ;
+ A_EXP : OUT std_logic_vector (7 DOWNTO 0);
+ A_SIG : OUT std_logic_vector (31 DOWNTO 0);
+ B_EXP : OUT std_logic_vector (7 DOWNTO 0);
+ B_SIG : OUT std_logic_vector (31 DOWNTO 0);
+ SIGN_out_stage1 : OUT std_logic ;
+ isINF_stage1 : OUT std_logic ;
+ isNaN_stage1 : OUT std_logic ;
+ isZ_tab_stage1 : OUT std_logic
+ );
+ END COMPONENT;
+ COMPONENT FPmul_stage2
+ PORT (
+ A_EXP : IN std_logic_vector (7 DOWNTO 0);
+ A_SIG : IN std_logic_vector (31 DOWNTO 0);
+ B_EXP : IN std_logic_vector (7 DOWNTO 0);
+ B_SIG : IN std_logic_vector (31 DOWNTO 0);
+ SIGN_out_stage1 : IN std_logic ;
+ clk : IN std_logic ;
+ isINF_stage1 : IN std_logic ;
+ isNaN_stage1 : IN std_logic ;
+ isZ_tab_stage1 : IN std_logic ;
+ EXP_in : OUT std_logic_vector (7 DOWNTO 0);
+ EXP_neg_stage2 : OUT std_logic ;
+ EXP_pos_stage2 : OUT std_logic ;
+ SIGN_out_stage2 : OUT std_logic ;
+ SIG_in : OUT std_logic_vector (27 DOWNTO 0);
+ isINF_stage2 : OUT std_logic ;
+ isNaN_stage2 : OUT std_logic ;
+ isZ_tab_stage2 : OUT std_logic
+ );
+ END COMPONENT;
+ COMPONENT FPmul_stage3
+ PORT (
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ EXP_neg_stage2 : IN std_logic ;
+ EXP_pos_stage2 : IN std_logic ;
+ SIGN_out_stage2 : IN std_logic ;
+ SIG_in : IN std_logic_vector (27 DOWNTO 0);
+ clk : IN std_logic ;
+ isINF_stage2 : IN std_logic ;
+ isNaN_stage2 : IN std_logic ;
+ isZ_tab_stage2 : IN std_logic ;
+ EXP_neg : OUT std_logic ;
+ EXP_out_round : OUT std_logic_vector (7 DOWNTO 0);
+ EXP_pos : OUT std_logic ;
+ SIGN_out : OUT std_logic ;
+ SIG_out_round : OUT std_logic_vector (27 DOWNTO 0);
+ isINF_tab : OUT std_logic ;
+ isNaN : OUT std_logic ;
+ isZ_tab : OUT std_logic
+ );
+ END COMPONENT;
+ COMPONENT FPmul_stage4
+ PORT (
+ EXP_neg : IN std_logic ;
+ EXP_out_round : IN std_logic_vector (7 DOWNTO 0);
+ EXP_pos : IN std_logic ;
+ SIGN_out : IN std_logic ;
+ SIG_out_round : IN std_logic_vector (27 DOWNTO 0);
+ clk : IN std_logic ;
+ isINF_tab : IN std_logic ;
+ isNaN : IN std_logic ;
+ isZ_tab : IN std_logic ;
+ FP_Z : OUT std_logic_vector (31 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : FPmul_stage1 USE ENTITY work.FPmul_stage1;
+ FOR ALL : FPmul_stage2 USE ENTITY work.FPmul_stage2;
+ FOR ALL : FPmul_stage3 USE ENTITY work.FPmul_stage3;
+ FOR ALL : FPmul_stage4 USE ENTITY work.FPmul_stage4;
+ -- pragma synthesis_on
+
+
+BEGIN
+
+ -- Instance port mappings.
+ I1 : FPmul_stage1
+ PORT MAP (
+ FP_A => FP_A,
+ FP_B => FP_B,
+ clk => clk,
+ A_EXP => A_EXP,
+ A_SIG => A_SIG,
+ B_EXP => B_EXP,
+ B_SIG => B_SIG,
+ SIGN_out_stage1 => SIGN_out_stage1,
+ isINF_stage1 => isINF_stage1,
+ isNaN_stage1 => isNaN_stage1,
+ isZ_tab_stage1 => isZ_tab_stage1
+ );
+ I2 : FPmul_stage2
+ PORT MAP (
+ A_EXP => A_EXP,
+ A_SIG => A_SIG,
+ B_EXP => B_EXP,
+ B_SIG => B_SIG,
+ SIGN_out_stage1 => SIGN_out_stage1,
+ clk => clk,
+ isINF_stage1 => isINF_stage1,
+ isNaN_stage1 => isNaN_stage1,
+ isZ_tab_stage1 => isZ_tab_stage1,
+ EXP_in => EXP_in,
+ EXP_neg_stage2 => EXP_neg_stage2,
+ EXP_pos_stage2 => EXP_pos_stage2,
+ SIGN_out_stage2 => SIGN_out_stage2,
+ SIG_in => SIG_in,
+ isINF_stage2 => isINF_stage2,
+ isNaN_stage2 => isNaN_stage2,
+ isZ_tab_stage2 => isZ_tab_stage2
+ );
+ I3 : FPmul_stage3
+ PORT MAP (
+ EXP_in => EXP_in,
+ EXP_neg_stage2 => EXP_neg_stage2,
+ EXP_pos_stage2 => EXP_pos_stage2,
+ SIGN_out_stage2 => SIGN_out_stage2,
+ SIG_in => SIG_in,
+ clk => clk,
+ isINF_stage2 => isINF_stage2,
+ isNaN_stage2 => isNaN_stage2,
+ isZ_tab_stage2 => isZ_tab_stage2,
+ EXP_neg => EXP_neg,
+ EXP_out_round => EXP_out_round,
+ EXP_pos => EXP_pos,
+ SIGN_out => SIGN_out,
+ SIG_out_round => SIG_out_round,
+ isINF_tab => isINF_tab,
+ isNaN => isNaN,
+ isZ_tab => isZ_tab
+ );
+ I4 : FPmul_stage4
+ PORT MAP (
+ EXP_neg => EXP_neg,
+ EXP_out_round => EXP_out_round,
+ EXP_pos => EXP_pos,
+ SIGN_out => SIGN_out,
+ SIG_out_round => SIG_out_round,
+ clk => clk,
+ isINF_tab => isINF_tab,
+ isNaN => isNaN,
+ isZ_tab => isZ_tab,
+ FP_Z => FP_Z
+ );
+
+END pipeline;
Index: fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_stage1_struct.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_stage1_struct.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_stage1_struct.vhd (revision 5)
@@ -0,0 +1,201 @@
+-- VHDL Entity HAVOC.FPmul_stage1.interface
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPmul_stage1 IS
+ PORT(
+ FP_A : IN std_logic_vector (31 DOWNTO 0);
+ FP_B : IN std_logic_vector (31 DOWNTO 0);
+ clk : IN std_logic;
+ A_EXP : OUT std_logic_vector (7 DOWNTO 0);
+ A_SIG : OUT std_logic_vector (31 DOWNTO 0);
+ B_EXP : OUT std_logic_vector (7 DOWNTO 0);
+ B_SIG : OUT std_logic_vector (31 DOWNTO 0);
+ SIGN_out_stage1 : OUT std_logic;
+ isINF_stage1 : OUT std_logic;
+ isNaN_stage1 : OUT std_logic;
+ isZ_tab_stage1 : OUT std_logic
+ );
+
+-- Declarations
+
+END FPmul_stage1 ;
+
+--
+-- VHDL Architecture HAVOC.FPmul_stage1.struct
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+
+ARCHITECTURE struct OF FPmul_stage1 IS
+
+ -- Architecture declarations
+ -- Non hierarchical truthtable declarations
+
+
+
+ -- Internal signal declarations
+ SIGNAL A_EXP_int : std_logic_vector(7 DOWNTO 0);
+ SIGNAL A_SIGN : std_logic;
+ SIGNAL A_SIG_int : std_logic_vector(31 DOWNTO 0);
+ SIGNAL A_isINF : std_logic;
+ SIGNAL A_isNaN : std_logic;
+ SIGNAL A_isZ : std_logic;
+ SIGNAL B_EXP_int : std_logic_vector(7 DOWNTO 0);
+ SIGNAL B_SIGN : std_logic;
+ SIGNAL B_SIG_int : std_logic_vector(31 DOWNTO 0);
+ SIGNAL B_isINF : std_logic;
+ SIGNAL B_isNaN : std_logic;
+ SIGNAL B_isZ : std_logic;
+ SIGNAL SIGN_out_int : std_logic;
+ SIGNAL isINF_int : std_logic;
+ SIGNAL isNaN_int : std_logic;
+ SIGNAL isZ_tab_int : std_logic;
+
+
+ -- Component Declarations
+ COMPONENT UnpackFP
+ PORT (
+ FP : IN std_logic_vector (31 DOWNTO 0);
+ SIG : OUT std_logic_vector (31 DOWNTO 0);
+ EXP : OUT std_logic_vector (7 DOWNTO 0);
+ SIGN : OUT std_logic ;
+ isNaN : OUT std_logic ;
+ isINF : OUT std_logic ;
+ isZ : OUT std_logic ;
+ isDN : OUT std_logic
+ );
+ END COMPONENT;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
+ -- pragma synthesis_on
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 latch
+ -- latch 1
+
+ PROCESS(clk)
+ BEGIN
+ IF RISING_EDGE(clk) THEN
+ SIGN_out_stage1 <= SIGN_out_int;
+ A_EXP <= A_EXP_int;
+ A_SIG <= A_SIG_int;
+ isINF_stage1 <= isINF_int;
+ isNaN_stage1 <= isNaN_int;
+ isZ_tab_stage1 <= isZ_tab_int;
+ B_EXP <= B_EXP_int;
+ B_SIG <= B_SIG_int;
+ END IF;
+ END PROCESS;
+
+ -- HDL Embedded Block 2 exceptions
+ -- Non hierarchical truthtable
+ ---------------------------------------------------------------------------
+ exceptions_truth_process: PROCESS(A_isINF, A_isNaN, A_isZ, B_isINF, B_isNaN, B_isZ)
+ ---------------------------------------------------------------------------
+ BEGIN
+ -- Block 1
+ IF (A_isINF = '0') AND (A_isNaN = '0') AND (A_isZ = '0') AND (B_isINF = '0') AND (B_isNaN = '0') AND (B_isZ = '0') THEN
+ isZ_tab_int <= '0';
+ isINF_int <= '0';
+ isNaN_int <= '0';
+ ELSIF (A_isINF = '1') AND (B_isZ = '1') THEN
+ isZ_tab_int <= '0';
+ isINF_int <= '0';
+ isNaN_int <= '1';
+ ELSIF (A_isZ = '1') AND (B_isINF = '1') THEN
+ isZ_tab_int <= '0';
+ isINF_int <= '0';
+ isNaN_int <= '1';
+ ELSIF (A_isINF = '1') THEN
+ isZ_tab_int <= '0';
+ isINF_int <= '1';
+ isNaN_int <= '0';
+ ELSIF (B_isINF = '1') THEN
+ isZ_tab_int <= '0';
+ isINF_int <= '1';
+ isNaN_int <= '0';
+ ELSIF (A_isNaN = '1') THEN
+ isZ_tab_int <= '0';
+ isINF_int <= '0';
+ isNaN_int <= '1';
+ ELSIF (B_isNaN = '1') THEN
+ isZ_tab_int <= '0';
+ isINF_int <= '0';
+ isNaN_int <= '1';
+ ELSIF (A_isZ = '1') THEN
+ isZ_tab_int <= '1';
+ isINF_int <= '0';
+ isNaN_int <= '0';
+ ELSIF (B_isZ = '1') THEN
+ isZ_tab_int <= '1';
+ isINF_int <= '0';
+ isNaN_int <= '0';
+ ELSE
+ isZ_tab_int <= '0';
+ isINF_int <= '0';
+ isNaN_int <= '0';
+ END IF;
+
+ END PROCESS exceptions_truth_process;
+
+ -- Architecture concurrent statements
+
+
+
+
+ -- ModuleWare code(v1.1) for instance 'I3' of 'xor'
+ SIGN_out_int <= A_SIGN XOR B_SIGN;
+
+ -- Instance port mappings.
+ I0 : UnpackFP
+ PORT MAP (
+ FP => FP_A,
+ SIG => A_SIG_int,
+ EXP => A_EXP_int,
+ SIGN => A_SIGN,
+ isNaN => A_isNaN,
+ isINF => A_isINF,
+ isZ => A_isZ,
+ isDN => OPEN
+ );
+ I1 : UnpackFP
+ PORT MAP (
+ FP => FP_B,
+ SIG => B_SIG_int,
+ EXP => B_EXP_int,
+ SIGN => B_SIGN,
+ isNaN => B_isNaN,
+ isINF => B_isINF,
+ isZ => B_isZ,
+ isDN => OPEN
+ );
+
+END struct;
Index: fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_stage2_struct.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_stage2_struct.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_stage2_struct.vhd (revision 5)
@@ -0,0 +1,143 @@
+-- VHDL Entity HAVOC.FPmul_stage2.interface
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPmul_stage2 IS
+ PORT(
+ A_EXP : IN std_logic_vector (7 DOWNTO 0);
+ A_SIG : IN std_logic_vector (31 DOWNTO 0);
+ B_EXP : IN std_logic_vector (7 DOWNTO 0);
+ B_SIG : IN std_logic_vector (31 DOWNTO 0);
+ SIGN_out_stage1 : IN std_logic;
+ clk : IN std_logic;
+ isINF_stage1 : IN std_logic;
+ isNaN_stage1 : IN std_logic;
+ isZ_tab_stage1 : IN std_logic;
+ EXP_in : OUT std_logic_vector (7 DOWNTO 0);
+ EXP_neg_stage2 : OUT std_logic;
+ EXP_pos_stage2 : OUT std_logic;
+ SIGN_out_stage2 : OUT std_logic;
+ SIG_in : OUT std_logic_vector (27 DOWNTO 0);
+ isINF_stage2 : OUT std_logic;
+ isNaN_stage2 : OUT std_logic;
+ isZ_tab_stage2 : OUT std_logic
+ );
+
+-- Declarations
+
+END FPmul_stage2 ;
+
+--
+-- VHDL Architecture HAVOC.FPmul_stage2.struct
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+
+ARCHITECTURE struct OF FPmul_stage2 IS
+
+ -- Architecture declarations
+
+ -- Internal signal declarations
+ SIGNAL EXP_in_int : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_neg_int : std_logic;
+ SIGNAL EXP_pos_int : std_logic;
+ SIGNAL SIG_in_int : std_logic_vector(27 DOWNTO 0);
+ SIGNAL dout : std_logic;
+ SIGNAL dout1 : std_logic_vector(7 DOWNTO 0);
+ SIGNAL prod : std_logic_vector(63 DOWNTO 0);
+
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 sig
+ -- eb1 1
+ SIG_in_int <= prod(47 DOWNTO 20);
+
+ -- HDL Embedded Text Block 2 inv
+ -- eb5 5
+ EXP_in_int <= (NOT dout1(7)) & dout1(6 DOWNTO 0);
+
+ -- HDL Embedded Text Block 3 latch
+ -- eb2 2
+
+ PROCESS(clk)
+ BEGIN
+ IF RISING_EDGE(clk) THEN
+ EXP_in <= EXP_in_int;
+ SIG_in <= SIG_in_int;
+ EXP_pos_stage2 <= EXP_pos_int;
+ EXP_neg_stage2 <= EXP_neg_int;
+ END IF;
+ END PROCESS;
+
+ -- HDL Embedded Text Block 4 latch2
+ -- latch2 4
+ PROCESS(clk)
+ BEGIN
+ IF RISING_EDGE(clk) THEN
+ isINF_stage2 <= isINF_stage1;
+ isNaN_stage2 <= isNaN_stage1;
+ isZ_tab_stage2 <= isZ_tab_stage1;
+ SIGN_out_stage2 <= SIGN_out_stage1;
+ END IF;
+ END PROCESS;
+
+ -- HDL Embedded Text Block 5 eb1
+ -- exp_pos 5
+ EXP_pos_int <= A_EXP(7) AND B_EXP(7);
+-- EXP_neg_int <= NOT(A_EXP(7) OR B_EXP(7));
+ EXP_neg_int <= '1' WHEN ( (A_EXP(7)='0' AND NOT (A_EXP=X"7F")) AND (B_EXP(7)='0' AND NOT (B_EXP=X"7F")) ) ELSE '0';
+
+
+ -- ModuleWare code(v1.1) for instance 'I4' of 'add'
+ I4combo: PROCESS (A_EXP, B_EXP, dout)
+ VARIABLE mw_I4t0 : std_logic_vector(8 DOWNTO 0);
+ VARIABLE mw_I4t1 : std_logic_vector(8 DOWNTO 0);
+ VARIABLE mw_I4sum : unsigned(8 DOWNTO 0);
+ VARIABLE mw_I4carry : std_logic;
+ BEGIN
+ mw_I4t0 := '0' & A_EXP;
+ mw_I4t1 := '0' & B_EXP;
+ mw_I4carry := dout;
+ mw_I4sum := unsigned(mw_I4t0) + unsigned(mw_I4t1) + mw_I4carry;
+ dout1 <= conv_std_logic_vector(mw_I4sum(7 DOWNTO 0),8);
+ END PROCESS I4combo;
+
+ -- ModuleWare code(v1.1) for instance 'I2' of 'mult'
+ I2combo : PROCESS (A_SIG, B_SIG)
+ VARIABLE dtemp : unsigned(63 DOWNTO 0);
+ BEGIN
+ dtemp := (unsigned(A_SIG) * unsigned(B_SIG));
+ prod <= std_logic_vector(dtemp);
+ END PROCESS I2combo;
+
+ -- ModuleWare code(v1.1) for instance 'I6' of 'vdd'
+ dout <= '1';
+
+ -- Instance port mappings.
+
+END struct;
Index: fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_stage3_struct.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_stage3_struct.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_stage3_struct.vhd (revision 5)
@@ -0,0 +1,149 @@
+-- VHDL Entity HAVOC.FPmul_stage3.interface
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPmul_stage3 IS
+ PORT(
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ EXP_neg_stage2 : IN std_logic;
+ EXP_pos_stage2 : IN std_logic;
+ SIGN_out_stage2 : IN std_logic;
+ SIG_in : IN std_logic_vector (27 DOWNTO 0);
+ clk : IN std_logic;
+ isINF_stage2 : IN std_logic;
+ isNaN_stage2 : IN std_logic;
+ isZ_tab_stage2 : IN std_logic;
+ EXP_neg : OUT std_logic;
+ EXP_out_round : OUT std_logic_vector (7 DOWNTO 0);
+ EXP_pos : OUT std_logic;
+ SIGN_out : OUT std_logic;
+ SIG_out_round : OUT std_logic_vector (27 DOWNTO 0);
+ isINF_tab : OUT std_logic;
+ isNaN : OUT std_logic;
+ isZ_tab : OUT std_logic
+ );
+
+-- Declarations
+
+END FPmul_stage3 ;
+
+--
+-- VHDL Architecture HAVOC.FPmul_stage3.struct
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ARCHITECTURE struct OF FPmul_stage3 IS
+
+ -- Architecture declarations
+
+ -- Internal signal declarations
+ SIGNAL EXP_out : std_logic_vector(7 DOWNTO 0);
+ SIGNAL EXP_out_norm : std_logic_vector(7 DOWNTO 0);
+ SIGNAL SIG_out : std_logic_vector(27 DOWNTO 0);
+ SIGNAL SIG_out_norm : std_logic_vector(27 DOWNTO 0);
+
+
+ -- Component Declarations
+ COMPONENT FPnormalize
+ GENERIC (
+ SIG_width : integer := 28
+ );
+ PORT (
+ SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0)
+ );
+ END COMPONENT;
+ COMPONENT FPround
+ GENERIC (
+ SIG_width : integer := 28
+ );
+ PORT (
+ SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
+ FOR ALL : FPround USE ENTITY work.FPround;
+ -- pragma synthesis_on
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 latch
+ -- latch 1
+ PROCESS(clk)
+ BEGIN
+ IF RISING_EDGE(clk) THEN
+ EXP_out_round <= EXP_out;
+ SIG_out_round <= SIG_out;
+ END IF;
+ END PROCESS;
+
+ -- HDL Embedded Text Block 2 latch2
+ -- latch2 2
+ PROCESS(clk)
+ BEGIN
+ IF RISING_EDGE(clk) THEN
+ isINF_tab <= isINF_stage2;
+ isNaN <= isNaN_stage2;
+ isZ_tab <= isZ_tab_stage2;
+ SIGN_out <= SIGN_out_stage2;
+ EXP_pos <= EXP_pos_stage2;
+ EXP_neg <= EXP_neg_stage2;
+ END IF;
+ END PROCESS;
+
+
+ -- Instance port mappings.
+ I9 : FPnormalize
+ GENERIC MAP (
+ SIG_width => 28
+ )
+ PORT MAP (
+ SIG_in => SIG_in,
+ EXP_in => EXP_in,
+ SIG_out => SIG_out_norm,
+ EXP_out => EXP_out_norm
+ );
+ I11 : FPround
+ GENERIC MAP (
+ SIG_width => 28
+ )
+ PORT MAP (
+ SIG_in => SIG_out_norm,
+ EXP_in => EXP_out_norm,
+ SIG_out => SIG_out,
+ EXP_out => EXP_out
+ );
+
+END struct;
Index: fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_stage4_struct.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_stage4_struct.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/multiplier/fpmul_stage4_struct.vhd (revision 5)
@@ -0,0 +1,161 @@
+-- VHDL Entity HAVOC.FPmul_stage4.interface
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- 2003-2004. V1.0
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY FPmul_stage4 IS
+ PORT(
+ EXP_neg : IN std_logic;
+ EXP_out_round : IN std_logic_vector (7 DOWNTO 0);
+ EXP_pos : IN std_logic;
+ SIGN_out : IN std_logic;
+ SIG_out_round : IN std_logic_vector (27 DOWNTO 0);
+ clk : IN std_logic;
+ isINF_tab : IN std_logic;
+ isNaN : IN std_logic;
+ isZ_tab : IN std_logic;
+ FP_Z : OUT std_logic_vector (31 DOWNTO 0)
+ );
+
+-- Declarations
+
+END FPmul_stage4 ;
+
+--
+-- VHDL Architecture HAVOC.FPmul_stage4.struct
+--
+-- Created by
+-- Guillermo Marcus, gmarcus@ieee.org
+-- using Mentor Graphics FPGA Advantage tools.
+--
+-- Visit "http://fpga.mty.itesm.mx" for more info.
+--
+-- Copyright 2003-2004. V1.0
+--
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ARCHITECTURE struct OF FPmul_stage4 IS
+
+ -- Architecture declarations
+
+ -- Internal signal declarations
+ SIGNAL EXP_out : std_logic_vector(7 DOWNTO 0);
+ SIGNAL FP : std_logic_vector(31 DOWNTO 0);
+ SIGNAL SIG_isZ : std_logic;
+ SIGNAL SIG_out : std_logic_vector(22 DOWNTO 0);
+ SIGNAL SIG_out_norm2 : std_logic_vector(27 DOWNTO 0);
+ SIGNAL isINF : std_logic;
+ SIGNAL isZ : std_logic;
+
+
+ -- Component Declarations
+ COMPONENT FPnormalize
+ GENERIC (
+ SIG_width : integer := 28
+ );
+ PORT (
+ SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0)
+ );
+ END COMPONENT;
+ COMPONENT PackFP
+ PORT (
+ SIGN : IN std_logic ;
+ EXP : IN std_logic_vector (7 DOWNTO 0);
+ SIG : IN std_logic_vector (22 DOWNTO 0);
+ isNaN : IN std_logic ;
+ isINF : IN std_logic ;
+ isZ : IN std_logic ;
+ FP : OUT std_logic_vector (31 DOWNTO 0)
+ );
+ END COMPONENT;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
+ FOR ALL : PackFP USE ENTITY work.PackFP;
+ -- pragma synthesis_on
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 trim
+ -- trim 1
+ SIG_out <= SIG_out_norm2(25 DOWNTO 3);
+
+ -- HDL Embedded Text Block 2 zero
+ -- zero 2
+ SIG_isZ <= '1' WHEN ((SIG_out_norm2(26 DOWNTO 3)=X"000000") OR
+ (EXP_neg='1' AND EXP_out(7)='1')) ELSE '0';
+
+ -- HDL Embedded Text Block 3 isINF_logic
+ -- isINF_logic 3
+ PROCESS(isZ,isINF_tab, EXP_pos, EXP_out)
+ BEGIN
+ IF isZ='0' THEN
+ IF isINF_tab='1' THEN
+ isINF <= '1';
+ ELSIF EXP_out=X"FF" THEN
+ isINF <='1';
+ ELSIF ((EXP_pos='1') AND (EXP_out(7)='0')) THEN
+ isINF <='1';
+ ELSE
+ isINF <= '0';
+ END IF;
+ ELSE
+ isINF <= '0';
+ END IF;
+ END PROCESS;
+
+ -- HDL Embedded Text Block 4 latch
+ -- latch 4
+ PROCESS(clk)
+ BEGIN
+ IF RISING_EDGE(clk) THEN
+ FP_Z <= FP;
+ END IF;
+ END PROCESS;
+
+
+ -- ModuleWare code(v1.1) for instance 'I2' of 'or'
+ isZ <= SIG_isZ OR isZ_tab;
+
+ -- Instance port mappings.
+ I1 : FPnormalize
+ GENERIC MAP (
+ SIG_width => 28
+ )
+ PORT MAP (
+ SIG_in => SIG_out_round,
+ EXP_in => EXP_out_round,
+ SIG_out => SIG_out_norm2,
+ EXP_out => EXP_out
+ );
+ I3 : PackFP
+ PORT MAP (
+ SIGN => SIGN_out,
+ EXP => EXP_out,
+ SIG => SIG_out,
+ isNaN => isNaN,
+ isINF => isINF,
+ isZ => isZ,
+ FP => FP
+ );
+
+END struct;
Index: fpuvhdl/trunk/fpuvhdl/gpl.txt
===================================================================
--- fpuvhdl/trunk/fpuvhdl/gpl.txt (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/gpl.txt (revision 5)
@@ -0,0 +1,340 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users. This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it. (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.) You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+ To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+ For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have. You must make sure that they, too, receive or can get the
+source code. And you must show them these terms so they know their
+rights.
+
+ We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+ Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software. If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
+authors' reputations.
+
+ Finally, any free program is threatened constantly by software
+patents. We wish to avoid the danger that redistributors of a free
+program will individually obtain patent licenses, in effect making the
+program proprietary. To prevent this, we have made it clear that any
+patent must be licensed for everyone's free use or not licensed at all.
+
+ The precise terms and conditions for copying, distribution and
+modification follow.
+
+ GNU GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
+under the terms of this General Public License. The "Program", below,
+refers to any such program or work, and a "work based on the Program"
+means either the Program or any derivative work under copyright law:
+that is to say, a work containing the Program or a portion of it,
+either verbatim or with modifications and/or translated into another
+language. (Hereinafter, translation is included without limitation in
+the term "modification".) Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope. The act of
+running the Program is not restricted, and the output from the Program
+is covered only if its contents constitute a work based on the
+Program (independent of having been made by running the Program).
+Whether that is true depends on what the Program does.
+
+ 1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
+conspicuously and appropriately publish on each copy an appropriate
+copyright notice and disclaimer of warranty; keep intact all the
+notices that refer to this License and to the absence of any warranty;
+and give any other recipients of the Program a copy of this License
+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
+you may at your option offer warranty protection in exchange for a fee.
+
+ 2. You may modify your copy or copies of the Program or any portion
+of it, thus forming a work based on the Program, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+ a) You must cause the modified files to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+ b) You must cause any work that you distribute or publish, that in
+ whole or in part contains or is derived from the Program or any
+ part thereof, to be licensed as a whole at no charge to all third
+ parties under the terms of this License.
+
+ c) If the modified program normally reads commands interactively
+ when run, you must cause it, when started running for such
+ interactive use in the most ordinary way, to print or display an
+ announcement including an appropriate copyright notice and a
+ notice that there is no warranty (or else, saying that you provide
+ a warranty) and that users may redistribute the program under
+ these conditions, and telling the user how to view a copy of this
+ License. (Exception: if the Program itself is interactive but
+ does not normally print such an announcement, your work based on
+ the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole. If
+identifiable sections of that work are not derived from the Program,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works. But when you
+distribute the same sections as part of a whole which is a work based
+on the Program, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program
+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+ 3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
+Sections 1 and 2 above provided that you also do one of the following:
+
+ a) Accompany it with the complete corresponding machine-readable
+ source code, which must be distributed under the terms of Sections
+ 1 and 2 above on a medium customarily used for software interchange; or,
+
+ b) Accompany it with a written offer, valid for at least three
+ years, to give any third party, for a charge no more than your
+ cost of physically performing source distribution, a complete
+ machine-readable copy of the corresponding source code, to be
+ distributed under the terms of Sections 1 and 2 above on a medium
+ customarily used for software interchange; or,
+
+ c) Accompany it with the information you received as to the offer
+ to distribute corresponding source code. (This alternative is
+ allowed only for noncommercial distribution and only if you
+ received the program in object code or executable form with such
+ an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it. For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
+control compilation and installation of the executable. However, as a
+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License. Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+ 5. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Program or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+ 6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+ 7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all. For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded. In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+ 9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time. Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation. If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+ 10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission. For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this. Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+ NO WARRANTY
+
+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+ 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+ To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+
+ Copyright (C)
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+ Gnomovision version 69, Copyright (C) year name of author
+ Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+ `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+ , 1 April 1989
+ Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs. If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library. If this is what you want to do, use the GNU Library General
+Public License instead of this License.
Index: fpuvhdl/trunk/fpuvhdl/gpl.html
===================================================================
--- fpuvhdl/trunk/fpuvhdl/gpl.html (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/gpl.html (revision 5)
@@ -0,0 +1,587 @@
+
+
+
+GNU General Public License - GNU Project - Free Software Foundation (FSF)
+
+
+
+
+![[image of a Philosophical GNU]](/graphics/philosophical-gnu-sm.jpg)
+
+
+
+
+
+
+
+
+
+[
+ Czech
+| English
+| Japanese
+]
+
+
+
+
+
+
+ +
+ +
+ + +
GNU General Public License
+
+
+
+
+
+
+
+
+
+
+[
+ Czech
+| English
+| Japanese
+]
+
+
+
+
+
++
-
+
- What to do if you see a + possible GPL violation +
- Translations + of the GPL +
- GPL Frequently Asked Questions +
- The GNU General Public License (GPL) + in plain text format +
- The GNU General Public License (GPL) + in Texinfo format +
- The GNU General Public License (GPL) + in LaTeX format +
- The GNU General Public License (GPL) + as an appendix in DocBook format +
+
+ +
+ +
Table of Contents
+-
+
+
- GNU GENERAL PUBLIC LICENSE + +
+ +
+ +
+ + + +
GNU GENERAL PUBLIC LICENSE
++Version 2, June 1991 + +
+ +
+Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+Everyone is permitted to copy and distribute verbatim copies
+of this license document, but changing it is not allowed.
+
+
+
+
+Preamble
+ ++ The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Library General Public License instead.) You can apply it to +your programs, too. + +
++ When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + +
++ To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + +
++ For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. And you must show them these terms so they know their +rights. + +
++ We protect your rights with two steps: (1) copyright the software, and +(2) offer you this license which gives you legal permission to copy, +distribute and/or modify the software. + +
++ Also, for each author's protection and ours, we want to make certain +that everyone understands that there is no warranty for this free +software. If the software is modified by someone else and passed on, we +want its recipients to know that what they have is not the original, so +that any problems introduced by others will not reflect on the original +authors' reputations. + +
++ Finally, any free program is threatened constantly by software +patents. We wish to avoid the danger that redistributors of a free +program will individually obtain patent licenses, in effect making the +program proprietary. To prevent this, we have made it clear that any +patent must be licensed for everyone's free use or not licensed at all. + +
++ The precise terms and conditions for copying, distribution and +modification follow. + +
+ + +TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+ + ++ +0. + This License applies to any program or other work which contains +a notice placed by the copyright holder saying it may be distributed +under the terms of this General Public License. The "Program", below, +refers to any such program or work, and a "work based on the Program" +means either the Program or any derivative work under copyright law: +that is to say, a work containing the Program or a portion of it, +either verbatim or with modifications and/or translated into another +language. (Hereinafter, translation is included without limitation in +the term "modification".) Each licensee is addressed as "you". +
+ +Activities other than copying, distribution and modification are not +covered by this License; they are outside its scope. The act of +running the Program is not restricted, and the output from the Program +is covered only if its contents constitute a work based on the +Program (independent of having been made by running the Program). +Whether that is true depends on what the Program does. + +
+ +1. + You may copy and distribute verbatim copies of the Program's +source code as you receive it, in any medium, provided that you +conspicuously and appropriately publish on each copy an appropriate +copyright notice and disclaimer of warranty; keep intact all the +notices that refer to this License and to the absence of any warranty; +and give any other recipients of the Program a copy of this License +along with the Program. +
+ +You may charge a fee for the physical act of transferring a copy, and +you may at your option offer warranty protection in exchange for a fee. +
+ +2. + You may modify your copy or copies of the Program or any portion +of it, thus forming a work based on the Program, and copy and +distribute such modifications or work under the terms of Section 1 +above, provided that you also meet all of these conditions: +
+ +
-
+
+
- a)
+ You must cause the modified files to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+
+
- b)
+ You must cause any work that you distribute or publish, that in
+ whole or in part contains or is derived from the Program or any
+ part thereof, to be licensed as a whole at no charge to all third
+ parties under the terms of this License.
+
+
+
- c) + If the modified program normally reads commands interactively + when run, you must cause it, when started running for such + interactive use in the most ordinary way, to print or display an + announcement including an appropriate copyright notice and a + notice that there is no warranty (or else, saying that you provide + a warranty) and that users may redistribute the program under + these conditions, and telling the user how to view a copy of this + License. (Exception: if the Program itself is interactive but + does not normally print such an announcement, your work based on + the Program is not required to print an announcement.) +
+ +Thus, it is not the intent of this section to claim rights or contest +your rights to work written entirely by you; rather, the intent is to +exercise the right to control the distribution of derivative or +collective works based on the Program. +
+ +In addition, mere aggregation of another work not based on the Program +with the Program (or with a work based on the Program) on a volume of +a storage or distribution medium does not bring the other work under +the scope of this License. + +
+ +3. + You may copy and distribute the Program (or a work based on it, +under Section 2) in object code or executable form under the terms of +Sections 1 and 2 above provided that you also do one of the following: + + + + +
-
+
+
- a)
+ Accompany it with the complete corresponding machine-readable
+ source code, which must be distributed under the terms of Sections
+ 1 and 2 above on a medium customarily used for software interchange; or,
+
+
+
- b)
+ Accompany it with a written offer, valid for at least three
+ years, to give any third party, for a charge no more than your
+ cost of physically performing source distribution, a complete
+ machine-readable copy of the corresponding source code, to be
+ distributed under the terms of Sections 1 and 2 above on a medium
+ customarily used for software interchange; or,
+
+
+
- c) + Accompany it with the information you received as to the offer + to distribute corresponding source code. (This alternative is + allowed only for noncommercial distribution and only if you + received the program in object code or executable form with such + an offer, in accord with Subsection b above.) +
+ +If distribution of executable or object code is made by offering +access to copy from a designated place, then offering equivalent +access to copy the source code from the same place counts as +distribution of the source code, even though third parties are not +compelled to copy the source along with the object code. +
+ +4. + You may not copy, modify, sublicense, or distribute the Program +except as expressly provided under this License. Any attempt +otherwise to copy, modify, sublicense or distribute the Program is +void, and will automatically terminate your rights under this License. +However, parties who have received copies, or rights, from you under +this License will not have their licenses terminated so long as such +parties remain in full compliance. + +
+ +5. + You are not required to accept this License, since you have not +signed it. However, nothing else grants you permission to modify or +distribute the Program or its derivative works. These actions are +prohibited by law if you do not accept this License. Therefore, by +modifying or distributing the Program (or any work based on the +Program), you indicate your acceptance of this License to do so, and +all its terms and conditions for copying, distributing or modifying +the Program or works based on it. + +
+ +6. + Each time you redistribute the Program (or any work based on the +Program), the recipient automatically receives a license from the +original licensor to copy, distribute or modify the Program subject to +these terms and conditions. You may not impose any further +restrictions on the recipients' exercise of the rights granted herein. +You are not responsible for enforcing compliance by third parties to +this License. + +
+ +7. + If, as a consequence of a court judgment or allegation of patent +infringement or for any other reason (not limited to patent issues), +conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot +distribute so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you +may not distribute the Program at all. For example, if a patent +license would not permit royalty-free redistribution of the Program by +all those who receive copies directly or indirectly through you, then +the only way you could satisfy both it and this License would be to +refrain entirely from distribution of the Program. +
+ +If any portion of this section is held invalid or unenforceable under +any particular circumstance, the balance of the section is intended to +apply and the section as a whole is intended to apply in other +circumstances. +
+ +It is not the purpose of this section to induce you to infringe any +patents or other property right claims or to contest validity of any +such claims; this section has the sole purpose of protecting the +integrity of the free software distribution system, which is +implemented by public license practices. Many people have made +generous contributions to the wide range of software distributed +through that system in reliance on consistent application of that +system; it is up to the author/donor to decide if he or she is willing +to distribute software through any other system and a licensee cannot +impose that choice. +
+ +This section is intended to make thoroughly clear what is believed to +be a consequence of the rest of this License. + +
+ +8. + If the distribution and/or use of the Program is restricted in +certain countries either by patents or by copyrighted interfaces, the +original copyright holder who places the Program under this License +may add an explicit geographical distribution limitation excluding +those countries, so that distribution is permitted only in or among +countries not thus excluded. In such case, this License incorporates +the limitation as if written in the body of this License. + +
+ +9. + The Free Software Foundation may publish revised and/or new versions +of the General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. +
+ +Each version is given a distinguishing version number. If the Program +specifies a version number of this License which applies to it and "any +later version", you have the option of following the terms and conditions +either of that version or of any later version published by the Free +Software Foundation. If the Program does not specify a version number of +this License, you may choose any version ever published by the Free Software +Foundation. + +
+ + +10. + If you wish to incorporate parts of the Program into other free +programs whose distribution conditions are different, write to the author +to ask for permission. For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + + +
NO WARRANTY
+ ++ +11. + BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + +
+ +12. + IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + +
+ + +
END OF TERMS AND CONDITIONS
+ + + +How to Apply These Terms to Your New Programs
+ ++ If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + +
++ To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + +
+ +
+one line to give the program's name and an idea of what it does.
+Copyright (C) yyyy name of author
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+
++Also add information on how to contact you by electronic and paper mail. + +
++If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + +
+ +
+Gnomovision version 69, Copyright (C) year name of author
+Gnomovision comes with ABSOLUTELY NO WARRANTY; for details
+type `show w'. This is free software, and you are welcome
+to redistribute it under certain conditions; type `show c'
+for details.
+
+
++The hypothetical commands `show w' and `show c' should show +the appropriate parts of the General Public License. Of course, the +commands you use may be called something other than `show w' and +`show c'; they could even be mouse-clicks or menu items--whatever +suits your program. + +
++You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + +
+ +
+Yoyodyne, Inc., hereby disclaims all copyright
+interest in the program `Gnomovision'
+(which makes passes at compilers) written
+by James Hacker.
+
+signature of Ty Coon, 1 April 1989
+Ty Coon, President of Vice
+
+
++This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the +GNU Lesser General Public License +instead of this License. + +
+ +
+ + +
+ +
+
+
+
+
Index: fpuvhdl/trunk/fpuvhdl/common/packfp_packfp.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/common/packfp_packfp.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/common/packfp_packfp.vhd (revision 5)
@@ -0,0 +1,58 @@
+--
+-- VHDL Architecture HAVOC.PackFP.PackFP
+--
+-- Created:
+-- by - Guillermo
+-- at - ITESM, 09:57:50 07/16/03
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
+--
+-- hds interface_start
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+
+ENTITY PackFP IS
+ PORT(
+ SIGN : IN std_logic;
+ EXP : IN std_logic_vector (7 DOWNTO 0);
+ SIG : IN std_logic_vector (22 DOWNTO 0);
+ isNaN : IN std_logic;
+ isINF : IN std_logic;
+ isZ : IN std_logic;
+ FP : OUT std_logic_vector (31 DOWNTO 0)
+ );
+
+-- Declarations
+
+END PackFP ;
+
+
+-- hds interface_end
+ARCHITECTURE PackFP OF PackFP IS
+BEGIN
+PROCESS(isNaN,isINF,isZ,SIGN,EXP,SIG)
+BEGIN
+
+ IF (isNaN='1') THEN
+ FP(31) <= SIGN;
+ FP(30 DOWNTO 23) <= X"FF";
+ FP(22 DOWNTO 0) <= "100" & X"00000";
+ ELSIF (isINF='1') THEN
+ FP(31) <= SIGN;
+ FP(30 DOWNTO 23) <= X"FF";
+ FP(22 DOWNTO 0) <= (OTHERS => '0');
+ ELSIF (isZ='1') THEN
+ FP(31) <= SIGN;
+ FP(30 DOWNTO 23) <= X"00";
+ FP(22 DOWNTO 0) <= (OTHERS => '0');
+ ELSE
+ FP(31) <= SIGN;
+ FP(30 DOWNTO 23) <= EXP;
+ FP(22 DOWNTO 0) <= SIG;
+ END IF;
+END PROCESS;
+
+END PackFP;
+
Index: fpuvhdl/trunk/fpuvhdl/common/fpround_fpround.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/common/fpround_fpround.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/common/fpround_fpround.vhd (revision 5)
@@ -0,0 +1,50 @@
+--
+-- VHDL Architecture HAVOC.FPround.FPround
+--
+-- Created:
+-- by - Guillermo
+-- at - ITESM, 11:08:16 07/16/03
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
+--
+-- hds interface_start
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+
+ENTITY FPround IS
+ GENERIC(
+ SIG_width : integer := 28
+ );
+ PORT(
+ SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0)
+ );
+
+-- Declarations
+
+END FPround ;
+
+
+-- hds interface_end
+ARCHITECTURE FPround OF FPround IS
+BEGIN
+ EXP_out <= EXP_in;
+
+PROCESS(SIG_in)
+BEGIN
+-- IF ((SIG_in(2)='0') OR ((SIG_in(3)='0') AND (SIG_in(1)='0') AND (SIG_in(0)='0'))) THEN
+-- IF ((SIG_in(2)='0') OR ((SIG_in(3)='0') AND (SIG_in(2)='1') AND (SIG_in(1)='0') AND (SIG_in(0)='0'))) THEN
+ IF (SIG_in(2)='0') THEN
+ SIG_out <= SIG_in;
+ ELSE
+ SIG_out <= (SIG_in(SIG_width-1 DOWNTO 3) + 1) & "000";
+ END IF;
+END PROCESS;
+
+END FPround;
+
Index: fpuvhdl/trunk/fpuvhdl/common/fpnormalize_fpnormalize.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/common/fpnormalize_fpnormalize.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/common/fpnormalize_fpnormalize.vhd (revision 5)
@@ -0,0 +1,49 @@
+--
+-- VHDL Architecture HAVOC.FPnormalize.FPnormalize
+--
+-- Created:
+-- by - Guillermo
+-- at - ITESM, 10:51:00 07/16/03
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
+--
+-- hds interface_start
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+
+ENTITY FPnormalize IS
+ GENERIC(
+ SIG_width : integer := 28
+ );
+ PORT(
+ SIG_in : IN std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_in : IN std_logic_vector (7 DOWNTO 0);
+ SIG_out : OUT std_logic_vector (SIG_width-1 DOWNTO 0);
+ EXP_out : OUT std_logic_vector (7 DOWNTO 0)
+ );
+
+-- Declarations
+
+END FPnormalize ;
+
+
+-- hds interface_end
+ARCHITECTURE FPnormalize OF FPnormalize IS
+BEGIN
+
+PROCESS(SIG_in, EXP_in)
+BEGIN
+ IF (SIG_in( SIG_width-1 )='1') THEN
+ SIG_out <= '0' & SIG_in(SIG_width-1 DOWNTO 2) & (SIG_in(1) AND SIG_in(0));
+ EXP_out <= EXP_in + 1;
+ ELSE
+ SIG_out <= SIG_in;
+ EXP_out <= EXP_in;
+ END IF;
+END PROCESS;
+
+END FPnormalize;
+
Index: fpuvhdl/trunk/fpuvhdl/common/unpackfp_unpackfp.vhd
===================================================================
--- fpuvhdl/trunk/fpuvhdl/common/unpackfp_unpackfp.vhd (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/common/unpackfp_unpackfp.vhd (revision 5)
@@ -0,0 +1,60 @@
+--
+-- VHDL Architecture HAVOC.UnpackFP.UnpackFP
+--
+-- Created:
+-- by - Guillermo
+-- at - ITESM, 09:06:00 07/16/03
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
+--
+-- hds interface_start
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY UnpackFP IS
+ PORT(
+ FP : IN std_logic_vector (31 DOWNTO 0);
+ SIG : OUT std_logic_vector (31 DOWNTO 0);
+ EXP : OUT std_logic_vector (7 DOWNTO 0);
+ SIGN : OUT std_logic;
+ isNaN : OUT std_logic;
+ isINF : OUT std_logic;
+ isZ : OUT std_logic;
+ isDN : OUT std_logic
+ );
+
+-- Declarations
+
+END UnpackFP ;
+
+
+-- hds interface_end
+ARCHITECTURE UnpackFP OF UnpackFP IS
+ SIGNAL exp_int : std_logic_vector(7 DOWNTO 0);
+ SIGNAL sig_int : std_logic_vector(22 DOWNTO 0);
+ SIGNAL expZ, expFF, sigZ : std_logic;
+BEGIN
+ exp_int <= FP(30 DOWNTO 23);
+ sig_int <= FP(22 DOWNTO 0);
+
+ SIGN <= FP(31);
+ EXP <= exp_int;
+ SIG(22 DOWNTO 0) <= sig_int;
+
+ expZ <= '1' WHEN (exp_int=X"00") ELSE '0';
+ expFF <= '1' WHEN (exp_int=X"FF") ELSE '0';
+
+ sigZ <= '1' WHEN (sig_int="00000000000000000000000") ELSE '0';
+
+ isNaN <= expFF AND (NOT sigZ);
+ isINF <= expFF AND sigZ;
+ isZ <= expZ AND sigZ;
+ isDN <= expZ AND (NOT sigZ);
+
+ -- Restore hidden 1.ffff when not zero or denormal
+ SIG(23) <= NOT expZ;
+
+ SIG(31 DOWNTO 24) <= (OTHERS => '0');
+END UnpackFP;
+
Index: fpuvhdl/trunk/fpuvhdl/README.txt
===================================================================
--- fpuvhdl/trunk/fpuvhdl/README.txt (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl/README.txt (revision 5)
@@ -0,0 +1,45 @@
+*****************************************************************************
+Floating Point Single Precision Adder and Multiplier
+Copyright (C) 2003-2004 Guillermo Marcus
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+*****************************************************************************
+
+
+ReadMe File
+-----------
+
+This archive contains the VHDL code for the FP adder and multiplier. It is structured in 3 directories:
+
+adder - adder specific files
+multiplier - multiplier specific files
+common - files common to the adder and multiplier
+
+Please note that files may require modification to work in your particular system.
+
+
+LICENSE
+-------
+
+As stated above. This license applies to all files in this package. Please check gpl.txt or gpl.html for a full license information.
+
+
+QUESTIONS / COMMENTS
+--------------------
+
+Any questions, comments regarding this package, please contact:
+
+Guillermo Marcus
+gmarcus@ieee.org, gmarcus@itesm.mx
Index: fpuvhdl/trunk/fpuvhdl.zip
===================================================================
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===================================================================
--- fpuvhdl/trunk/fpuvhdl.zip (nonexistent)
+++ fpuvhdl/trunk/fpuvhdl.zip (revision 5)
+Return to the GNU Project home page. +
+ +
+Please send FSF & GNU inquiries to
+gnu@gnu.org.
+There are also other ways to contact
+the FSF.
+
+Please send broken links and other corrections (or suggestions) to
+webmasters@gnu.org.
+
+Please see the +Translations +README for information on coordinating and submitting +translations of this article. +
+ +
+Copyright notice above.
+59 Temple Place - Suite 330, Boston, MA 02111, USA
+
+Verbatim copying and distribution of this entire article is
+permitted in any medium without royalty provided this notice is
+preserved.
+
+Updated: + +$Date: 2004-11-05 14:06:28 $ $Author: gmarcus $ + +
+
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fpuvhdl/trunk
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fpuvhdl/web_uploads
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