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URL https://opencores.org/ocsvn/ft245r_interface/ft245r_interface/trunk

Subversion Repositories ft245r_interface

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    /ft245r_interface
    from Rev 6 to Rev 7
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Rev 6 → Rev 7

/branches/ft245r_avalon/ft245_avalon.vhd
0,0 → 1,139
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
-- clk_cycle_duration:
-- 20 - 2.5ns (400MHz)
-- 10 - 5ns (200MHz)
-- 5 - 10ns (100MHz)
-- 1 - 20ns (50MHz)
 
entity ft245_avalon is
generic(clk_cycle_duration : integer := 20);
port
(
clk : in std_logic;
pwrite : in std_logic;
pread : in std_logic;
readdata : out std_logic_vector(31 downto 0);
writedata : in std_logic_vector(31 downto 0);
resetn : in std_logic;
address : in std_logic_vector(3 downto 0);
-- FT245 interface
ft_rxf : in std_logic;
ft_txe : in std_logic;
ft_rd : out std_logic;
ft_wr : out std_logic;
ft_data : inout std_logic_vector(7 downto 0);
ft_reset : out std_logic
);
end ft245_avalon;
 
architecture action of ft245_avalon is
component ft245_rcv
generic(clock_cycle : integer);
port
(
clk, n_rxf, rd : in std_logic;
data_in : in std_logic_vector(7 downto 0);
n_rd, ready : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end component;
signal rcv_data_in : std_logic_vector(7 downto 0);
signal rcv_rd : std_logic;
signal rcv_ready : std_logic;
signal rcv_data_out : std_logic_vector(7 downto 0);
component ft245_snd
generic(clock_cycle : integer);
port
(
clk, n_txe, wr : in std_logic;
data_in : in std_logic_vector(7 downto 0);
n_wr, ready : out std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end component;
signal snd_data_out : std_logic_vector(7 downto 0);
signal snd_wr : std_logic;
signal snd_ready : std_logic;
signal snd_data_in : std_logic_vector(7 downto 0);
signal prev_pread : std_logic;
signal prev_pwrite : std_logic;
signal prev_address : std_logic_vector(3 downto 0);
begin
RCV:ft245_rcv
generic map(clock_cycle => clk_cycle_duration)
port map
(
clk => clk,
n_rxf => ft_rxf,
rd => rcv_rd,
data_in => rcv_data_in,
n_rd => ft_rd,
ready => rcv_ready,
data_out => rcv_data_out
);
SND:ft245_snd
generic map(clock_cycle => clk_cycle_duration)
port map
(
clk => clk,
n_txe => ft_txe,
wr => snd_wr,
data_in => snd_data_in,
n_wr => ft_wr,
ready => snd_ready,
data_out => snd_data_out
);
 
ft_reset <= resetn;
-- readdata(7 downto 0) <= rcv_data_out;
-- readdata(8) <= rcv_ready;
-- readdata(9) <= snd_ready;
 
-- Changed the addressing within the component
readdata(7 downto 0) <= rcv_data_out when address = "0000" else
"000000"&snd_ready&rcv_ready when address = "0001" else
x"ff";
readdata(31 downto 8) <= x"000000";
rcv_rd <= '1' when (prev_pread = '0' and pread = '1' and rcv_ready = '1' and prev_address = "0000") else
'0';
snd_wr <= '1' when (prev_pwrite = '0' and pwrite = '1' and snd_ready = '1') else
'0';
snd_data_in <= writedata(7 downto 0);
ft_data <= snd_data_out when snd_ready = '0' else
"ZZZZZZZZ";
rcv_data_in <= ft_data;
TRACK_ADDRESS:process(clk, address)
begin
if(rising_edge(clk))then
prev_address <= address;
end if;
end process;
TOGGLE_RD:process(clk, pread)
begin
if(rising_edge(clk))then
prev_pread <= pread;
end if;
end process;
TOGGLE_WR:process(clk, pwrite)
begin
if(rising_edge(clk))then
prev_pwrite <= pwrite;
end if;
end process;
end action;
/branches/ft245r_avalon/ft245_snd.vhd
0,0 → 1,85
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
entity ft245_snd is
generic(clock_cycle : integer);
port
(
clk : in std_logic;
data_in : in std_logic_vector(7 downto 0);
n_wr : out std_logic := '0';
n_txe : in std_logic;
-- system interface
ready : out std_logic := '0'; -- goes high when there's a byte available for reading
wr : in std_logic; -- invalidates current byte
data_out : out std_logic_vector(7 downto 0)
);
end ft245_snd;
 
 
architecture action of ft245_snd is
constant t7 : integer := integer(100.0 / (50.0 / real(clock_cycle)));
constant t8 : integer := integer(50.0 / (50.0 / real(clock_cycle)));
constant t9 : integer := integer(20.0 / (50.0 / real(clock_cycle)));
constant t11: integer := integer(25.0 / (50.0 / real(clock_cycle)));
constant t12: integer := integer(80.0 / (50.0 / real(clock_cycle)));
type state_t is
(
S_IDLE,
S_WR_HIGH,
S_WR_LOW,
S_DELAY,
S_END
);
signal state : state_t := S_IDLE;
signal n_state : state_t := S_IDLE;
signal delay : integer := 0;
begin
 
ready <= '1' when n_txe = '0' and state = S_IDLE else '0';
-- n_wr <= '1' when (state = S_WR_HIGH or n_state = S_WR_HIGH) else '0';
process(clk, n_txe, wr)
begin
if(rising_edge(clk))then
case state is
when S_IDLE =>
if(wr = '1' and n_txe = '0')then
n_wr <= '1';
delay <= t7;
data_out <= data_in;
n_state <= S_WR_HIGH;
state <= S_DELAY;
end if;
when S_WR_HIGH =>
delay <= t8;
n_state <= S_WR_LOW;
state <= S_DELAY;
n_wr <= '0';
when S_WR_LOW =>
delay <= t12 - t8;
n_state <= S_END;
state <= S_DELAY;
when S_DELAY =>
if(delay > 0)then
delay <= delay - 1;
else
state <= n_state;
end if;
when S_END =>
state <= S_IDLE;
when others =>
state <= S_IDLE;
end case;
end if;
end process;
end action;
/branches/ft245r_avalon/ft245_rcv.vhd
0,0 → 1,93
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
entity ft245_rcv is
generic(clock_cycle : integer);
port
(
clk : in std_logic;
data_in : in std_logic_vector(7 downto 0);
n_rd : out std_logic := '1';
n_rxf : in std_logic;
-- system interface
ready : out std_logic := '0'; -- goes high when there's a byte available for reading
rd : in std_logic; -- invalidates current byte
data_out : out std_logic_vector(7 downto 0)
);
end ft245_rcv;
 
 
architecture action of ft245_rcv is
constant t1 : integer := integer(100.0 / (50.0 / real(clock_cycle)));
constant t3 : integer := integer(40.0 / (50.0 / real(clock_cycle)));
constant t5 : integer := integer(25.0 / (50.0 / real(clock_cycle)));
constant t6 : integer := integer(80.0 / (50.0 / real(clock_cycle)));
constant t2 : integer := integer((50.0 + 80.0) / (50.0 / real(clock_cycle)));
type state_t is
(
S_IDLE,
S_RD_LOW,
S_RD_HIGH,
S_DELAY,
S_END
);
signal state : state_t := S_IDLE;
signal n_state : state_t := S_IDLE;
signal delay : integer := 0;
signal can_read : std_logic:= '1';
begin
 
ready <= '1' when state = S_END else '0';
 
process(clk, n_rxf, rd)
begin
if(rd = '1')then
state <= S_IDLE;
elsif(rising_edge(clk))then
case state is
when S_IDLE =>
if(n_rxf = '0')then
n_rd <= '0';
n_state <= S_RD_LOW;
state <= S_DELAY;
delay <= t3;
end if;
when S_RD_LOW =>
-- data_out <= data_in;
n_state <= S_RD_HIGH;
state <= S_DELAY;
delay <= t1 - t3;
when S_RD_HIGH =>
data_out <= data_in;
n_rd <= '1';
n_state <= S_END;
state <= S_DELAY;
delay <= t6;
when S_END =>
if(rd = '1')then
state <= S_IDLE;
else
state <= S_END;
end if;
when S_DELAY =>
if(delay > 0)then
delay <= delay - 1;
else
state <= n_state;
end if;
when others =>
state <= S_IDLE;
end case;
end if;
end process;
end action;

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