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/rtl/verilog2/fpCompare128.sv
0,0 → 1,83
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2007-2023 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// fpCompare128.sv |
// - floating point comparison unit |
// - IEEE 754 representation |
// |
// |
// This source file is free software: you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or |
// (at your option) any later version. |
// |
// This source file is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
// GNU General Public License for more details. |
// |
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// |
// ============================================================================ |
|
import fp128Pkg::*; |
|
module fpCompare128(a, b, o, inf, nan, snan); |
input FP128 a, b; |
output [15:0] o; |
reg [15:0] o; |
output inf; |
output nan; |
output snan; |
|
// Decompose the operands |
wire sa; |
wire sb; |
wire [fp128Pkg::EMSB:0] xa; |
wire [fp128Pkg::EMSB:0] xb; |
wire [fp128Pkg::FMSB:0] ma; |
wire [fp128Pkg::FMSB:0] mb; |
wire az, bz; |
wire nan_a, nan_b; |
wire infa, infb; |
|
fpDecomp128 u1(.i(a), .sgn(sa), .exp(xa), .man(ma), .vz(az), .inf(infa), .xinf(), .qnan(), .snan(), .nan(nan_a) ); |
fpDecomp128 u2(.i(b), .sgn(sb), .exp(xb), .man(mb), .vz(bz), .inf(infb), .xinf(), .qnan(), .snan(), .nan(nan_b) ); |
|
wire unordered = nan_a | nan_b; |
|
wire eq = !unordered & ((az & bz) || (a==b)); // special test for zero |
wire ne = !((az & bz) || (a==b)); // special test for zero |
wire gt1 = ({xa,ma} > {xb,mb}) | (infa & ~infb); |
wire lt1 = ({xa,ma} < {xb,mb}) | (infb & ~infa); |
|
wire lt = sa ^ sb ? sa & !(az & bz): sa ? gt1 : lt1; |
|
always_comb |
begin |
o = 'd0; |
o[0] = eq; |
o[1] = lt & !unordered; |
o[2] = (lt|eq) & !unordered; |
o[3] = lt1; |
o[4] = unordered; |
o[7:5] = 3'd0; |
o[8] = ne; |
o[9] = ~lt & !unordered; |
o[10] = ~(lt|eq) & !unordered; |
o[11] = ~lt1; |
o[12] = ~unordered; |
end |
|
// an unorder comparison will signal a nan exception |
//assign nanx = op!=`FCOR && op!=`FCUN && unordered; |
assign nan = nan_a|nan_b|(infa & infb); |
assign snan = (nan_a & ~ma[fp128Pkg::FMSB]) | (nan_b & ~mb[fp128Pkg::FMSB]); |
assign inf = infa&infb; |
|
endmodule |
/rtl/verilog2/fpCompare32.sv
0,0 → 1,83
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2007-2023 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// fpCompare32.sv |
// - floating point comparison unit |
// - IEEE 754 representation |
// |
// |
// This source file is free software: you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or |
// (at your option) any later version. |
// |
// This source file is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
// GNU General Public License for more details. |
// |
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// |
// ============================================================================ |
|
import fp32Pkg::*; |
|
module fpCompare32(a, b, o, inf, nan, snan); |
input FP32 a, b; |
output [15:0] o; |
reg [15:0] o; |
output inf; |
output nan; |
output snan; |
|
// Decompose the operands |
wire sa; |
wire sb; |
wire [fp32Pkg::EMSB:0] xa; |
wire [fp32Pkg::EMSB:0] xb; |
wire [fp32Pkg::FMSB:0] ma; |
wire [fp32Pkg::FMSB:0] mb; |
wire az, bz; |
wire nan_a, nan_b; |
wire infa, infb; |
|
fpDecomp32 u1(.i(a), .sgn(sa), .exp(xa), .man(ma), .vz(az), .inf(infa), .qnan(), .snan(), .nan(nan_a) ); |
fpDecomp32 u2(.i(b), .sgn(sb), .exp(xb), .man(mb), .vz(bz), .inf(infb), .qnan(), .snan(), .nan(nan_b) ); |
|
wire unordered = nan_a | nan_b; |
|
wire eq = !unordered & ((az & bz) || (a==b)); // special test for zero |
wire ne = !((az & bz) || (a==b)); // special test for zero |
wire gt1 = ({xa,ma} > {xb,mb}) | (infa & ~binf); |
wire lt1 = ({xa,ma} < {xb,mb}) | (infb & ~ainf); |
|
wire lt = sa ^ sb ? sa & !(az & bz): sa ? gt1 : lt1; |
|
always_comb |
begin |
o = 'd0; |
o[0] = eq; |
o[1] = lt & !unordered; |
o[2] = (lt|eq) & !unordered; |
o[3] = lt1; |
o[4] = unordered; |
o[7:5] = 3'd0; |
o[8] = ne; |
o[9] = ~lt & !unordered; |
o[10] = ~(lt|eq) & !unordered; |
o[11] = ~lt1; |
o[12] = ~unordered; |
end |
|
// an unorder comparison will signal a nan exception |
//assign nanx = op!=`FCOR && op!=`FCUN && unordered; |
assign nan = nan_a|nan_b|(infa & infb); |
assign snan = (nan_a & ~ma[fp32Pkg::FMSB]) | (nan_b & ~mb[fp32Pkg::FMSB]); |
assign inf = infa & infb; |
|
endmodule |
/rtl/verilog2/fpCompare64.sv
0,0 → 1,83
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2007-2023 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// fpCompare64.sv |
// - floating point comparison unit |
// - IEEE 754 representation |
// |
// |
// This source file is free software: you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or |
// (at your option) any later version. |
// |
// This source file is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
// GNU General Public License for more details. |
// |
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// |
// ============================================================================ |
|
import fp64Pkg::*; |
|
module fpCompare64(a, b, o, inf, nan, snan); |
input FP64 a, b; |
output [15:0] o; |
reg [15:0] o; |
output inf; |
output nan; |
output snan; |
|
// Decompose the operands |
wire sa; |
wire sb; |
wire [fp64Pkg::EMSB:0] xa; |
wire [fp64Pkg::EMSB:0] xb; |
wire [fp64Pkg::FMSB:0] ma; |
wire [fp64Pkg::FMSB:0] mb; |
wire az, bz; |
wire nan_a, nan_b; |
wire infa, infb; |
|
fpDecomp64 u1(.i(a), .sgn(sa), .exp(xa), .man(ma), .vz(az), .inf(infa), .qnan(), .snan(), .nan(nan_a) ); |
fpDecomp64 u2(.i(b), .sgn(sb), .exp(xb), .man(mb), .vz(bz), .inf(infb), .qnan(), .snan(), .nan(nan_b) ); |
|
wire unordered = nan_a | nan_b; |
|
wire eq = !unordered & ((az & bz) || (a==b)); // special test for zero |
wire ne = !((az & bz) || (a==b)); // special test for zero |
wire gt1 = ({xa,ma} > {xb,mb}) | (infa & ~infb); |
wire lt1 = ({xa,ma} < {xb,mb}) | (infb & ~infa); |
|
wire lt = sa ^ sb ? sa & !(az & bz): sa ? gt1 : lt1; |
|
always_comb |
begin |
o = 'd0; |
o[0] = eq; |
o[1] = lt & !unordered; |
o[2] = (lt|eq) & !unordered; |
o[3] = lt1; |
o[4] = unordered; |
o[7:5] = 3'd0; |
o[8] = ne; |
o[9] = ~lt & !unordered; |
o[10] = ~(lt|eq) & !unordered; |
o[11] = ~lt1; |
o[12] = ~unordered; |
end |
|
// an unorder comparison will signal a nan exception |
//assign nanx = op!=`FCOR && op!=`FCUN && unordered; |
assign nan = nan_a|nan_b|(infa & infb); |
assign snan = (nan_a & ~ma[fp64Pkg::FMSB]) | (nan_b & ~mb[fp64Pkg::FMSB]); |
assign inf = infa & infb; |
|
endmodule |
/rtl/verilog2/fpCordic.sv
0,0 → 1,331
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2013-2023 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// |
// BSD 3-Clause License |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions are met: |
// |
// 1. Redistributions of source code must retain the above copyright notice, this |
// list of conditions and the following disclaimer. |
// |
// 2. Redistributions in binary form must reproduce the above copyright notice, |
// this list of conditions and the following disclaimer in the documentation |
// and/or other materials provided with the distribution. |
// |
// 3. Neither the name of the copyright holder nor the names of its |
// contributors may be used to endorse or promote products derived from |
// this software without specific prior written permission. |
// |
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
// |
// ============================================================================ |
|
module fpCordic(rst, clk, arctan, ld, phase_i, xval_i, yval_i, xval_o, yval_o, phase_o, done); |
parameter NSTAGES = 54; |
parameter IW = 54; |
parameter OW = 54; |
parameter WW = 60; |
parameter PW = 60; |
parameter INV_GAIN = 54'h26dd3b6a10d798; // 2^54 / gain |
input rst; |
input clk; |
input arctan; |
input ld; |
input [PW-1:0] phase_i; |
input [IW-1:0] xval_i; |
input [IW-1:0] yval_i; |
output reg [OW-1:0] xval_o; |
output reg [OW-1:0] yval_o; |
output reg [PW-1:0] phase_o; |
output done; |
|
integer nn; |
wire [WW-1:0] cordic_angle [0:NSTAGES+2]; |
assign cordic_angle[0] = 60'h200000000000000; // 45.000000000000000000000000 deg |
assign cordic_angle[1] = 60'h12e4051d9df3080; // 26.565051177077990018915443 deg |
assign cordic_angle[2] = 60'h09fb385b5ee39e8; // 14.036243467926476924390045 deg |
assign cordic_angle[3] = 60'h051111d41ddd9a4; // 7.125016348901797691439697 deg |
assign cordic_angle[4] = 60'h028b0d430e589b0; // 3.576334374997351517322386 deg |
assign cordic_angle[5] = 60'h0145d7e15904628; // 1.789910608246069401161549 deg |
assign cordic_angle[6] = 60'h00a2f61e5c28263; // 0.895173710211074391551733 deg |
assign cordic_angle[7] = 60'h00517c5511d442b; // 0.447614170860553051145558 deg |
assign cordic_angle[8] = 60'h0028be5346d0c33; // 0.223810500368538084492442 deg |
assign cordic_angle[9] = 60'h00145f2ebb30ab3; // 0.111905677066206896141942 deg |
assign cordic_angle[10] = 60'h000a2f980091ba7; // 0.055952891893803667622276 deg |
assign cordic_angle[11] = 60'h000517cc14a80cb; // 0.027976452617003676193175 deg |
assign cordic_angle[12] = 60'h00028be60cdfec6; // 0.013988227142265016386680 deg |
assign cordic_angle[13] = 60'h000145f306c172f; // 0.006994113675352918273187 deg |
assign cordic_angle[14] = 60'h0000a2f9836ae91; // 0.003497056850704011263936 deg |
assign cordic_angle[15] = 60'h0000517cc1b6ba7; // 0.001748528426980449539466 deg |
assign cordic_angle[16] = 60'h000028be60db85f; // 0.000874264213693780258170 deg |
assign cordic_angle[17] = 60'h0000145f306dc81; // 0.000437132106872334565140 deg |
assign cordic_angle[18] = 60'h00000a2f9836e4a; // 0.000218566053439347843853 deg |
assign cordic_angle[19] = 60'h00000517cc1b726; // 0.000109283026720071498863 deg |
assign cordic_angle[20] = 60'h0000028be60db93; // 0.000054641513360085439772 deg |
assign cordic_angle[21] = 60'h00000145f306dc9; // 0.000027320756680048933720 deg |
assign cordic_angle[22] = 60'h000000a2f9836e4; // 0.000013660378340025242742 deg |
assign cordic_angle[23] = 60'h000000517cc1b72; // 0.000006830189170012718780 deg |
assign cordic_angle[24] = 60'h00000028be60db9; // 0.000003415094585006371248 deg |
assign cordic_angle[25] = 60'h000000145f306dc; // 0.000001707547292503187107 deg |
assign cordic_angle[26] = 60'h0000000a2f9836e; // 0.000000853773646251593765 deg |
assign cordic_angle[27] = 60'h0000000517cc1b7; // 0.000000426886823125796935 deg |
assign cordic_angle[28] = 60'h000000028be60db; // 0.000000213443411562898468 deg |
assign cordic_angle[29] = 60'h0000000145f306d; // 0.000000106721705781449234 deg |
assign cordic_angle[30] = 60'h00000000a2f9836; // 0.000000053360852890724617 deg |
assign cordic_angle[31] = 60'h00000000517cc1b; // 0.000000026680426445362308 deg |
assign cordic_angle[32] = 60'h0000000028be60d; // 0.000000013340213222681154 deg |
assign cordic_angle[33] = 60'h00000000145f306; // 0.000000006670106611340577 deg |
assign cordic_angle[34] = 60'h000000000a2f983; // 0.000000003335053305670289 deg |
assign cordic_angle[35] = 60'h000000000517cc1; // 0.000000001667526652835144 deg |
assign cordic_angle[36] = 60'h00000000028be60; // 0.000000000833763326417572 deg |
assign cordic_angle[37] = 60'h000000000145f30; // 0.000000000416881663208786 deg |
assign cordic_angle[38] = 60'h0000000000a2f98; // 0.000000000208440831604393 deg |
assign cordic_angle[39] = 60'h0000000000517cc; // 0.000000000104220415802197 deg |
assign cordic_angle[40] = 60'h000000000028be6; // 0.000000000052110207901098 deg |
assign cordic_angle[41] = 60'h0000000000145f3; // 0.000000000026055103950549 deg |
assign cordic_angle[42] = 60'h00000000000a2f9; // 0.000000000013027551975275 deg |
assign cordic_angle[43] = 60'h00000000000517c; // 0.000000000006513775987637 deg |
assign cordic_angle[44] = 60'h0000000000028be; // 0.000000000003256887993819 deg |
assign cordic_angle[45] = 60'h00000000000145f; // 0.000000000001628443996909 deg |
assign cordic_angle[46] = 60'h000000000000a2f; // 0.000000000000814221998455 deg |
assign cordic_angle[47] = 60'h000000000000517; // 0.000000000000407110999227 deg |
assign cordic_angle[48] = 60'h00000000000028b; // 0.000000000000203555499614 deg |
assign cordic_angle[49] = 60'h000000000000145; // 0.000000000000101777749807 deg |
assign cordic_angle[50] = 60'h0000000000000a2; // 0.000000000000050888874903 deg |
assign cordic_angle[51] = 60'h000000000000051; // 0.000000000000025444437452 deg |
assign cordic_angle[52] = 60'h000000000000028; // 0.000000000000012722218726 deg |
assign cordic_angle[53] = 60'h000000000000014; // 0.000000000000006361109363 deg |
//gain: 1.646760258121065412240114 |
//2^54/gain: 10939296367302552.000000000000000000000000 |
//0026dd3b6a10d798 |
|
reg [7:0] cnt; |
wire signed [(WW-1):0] e_xval, e_yval; |
// Declare variables for all of the separate stages |
reg signed [WW-1:0] xv [0:5]; |
reg signed [WW-1:0] yv [0:5]; |
reg [PW:0] ph [0:5]; |
reg signed [WW-1:0] xv5, yv5; |
reg [PW:0] ph5; |
reg [2:0] cr_rot; |
|
assign e_xval = { {xval_i[(IW-1)]}, xval_i, {(WW-IW-1){1'b0}} }; |
assign e_yval = { {yval_i[(IW-1)]}, yval_i, {(WW-IW-1){1'b0}} }; |
|
// Round our result towards even |
wire [WW-1:0] pre_xval, pre_yval; |
|
assign pre_xval = xv[4] + {{(OW){1'b0}},xv[4][(WW-OW)],{(WW-OW-1){!xv[4][WW-OW]}}}; |
assign pre_yval = yv[4] + {{(OW){1'b0}},yv[4][(WW-OW)],{(WW-OW-1){!yv[4][WW-OW]}}}; |
|
always_ff @(posedge clk, posedge rst) |
if (rst) |
cnt <= 'd0; |
else begin |
if (ld) |
cnt <= 'd0; |
else if (!done) |
cnt <= cnt + 2'd2; |
end |
|
assign done = cnt==8'd64; |
|
// cnt equals 10 for the first iteration. |
always_comb |
if (arctan ? ~yv[4][WW-1] : ph[4][PW]) // Negative phase |
begin |
// If the phase is negative, rotate by the |
// CORDIC angle in a clockwise direction. |
xv5 = xv[4] + (yv[4] >>> (cnt - 8'd10)); |
yv5 = yv[4] - (xv[4] >>> (cnt - 8'd10)); |
ph5 = ph[4] + cordic_angle[cnt-8'd10]; |
|
end |
else begin |
// On the other hand, if the phase is |
// positive ... rotate in the |
// counter-clockwise direction |
xv5 = xv[4] - (yv[4] >>> (cnt - 8'd10)); |
yv5 = yv[4] + (xv[4] >>> (cnt - 8'd10)); |
ph5 = ph[4] - cordic_angle[cnt-8'd10]; |
end |
|
always_ff @(posedge clk, posedge rst) |
if (rst) begin |
xval_o <= 'd0; |
yval_o <= 'd0; |
phase_o <= 'd0; |
for (nn = 0; nn < 6; nn = nn + 1) begin |
xv[nn] <= 'd0; |
yv[nn] <= 'd0; |
ph[nn] <= 'd0; |
end |
end |
else begin |
if (ld) begin |
if (arctan) begin |
// First stage, map to within +/- 45 degrees |
case({xval_i[IW-1], yval_i[IW-1]}) |
2'b01: begin // Rotate by -315 degrees |
xv[0] <= e_xval - e_yval; |
yv[0] <= e_xval + e_yval; |
ph[0] <= 60'hE00000000000000; |
end |
2'b10: begin // Rotate by -135 degrees |
xv[0] <= -e_xval + e_yval; |
yv[0] <= -e_xval - e_yval; |
ph[0] <= 60'h300000000000000; |
end |
2'b11: begin // Rotate by -225 degrees |
xv[0] <= -e_xval - e_yval; |
yv[0] <= e_xval - e_yval; |
ph[0] <= 60'h500000000000000; // 19'h50000; |
end |
// 2'b00: |
default: begin // Rotate by -45 degrees |
xv[0] <= e_xval + e_yval; |
yv[0] <= -e_xval + e_yval; |
ph[0] <= 60'h100000000000000; |
end |
endcase |
end |
else begin |
cr_rot <= phase_i[(PW-1):(PW-3)]; |
case(phase_i[(PW-1):(PW-3)]) |
3'b000: |
begin // 0 .. 45, No change 270 .. 360 |
xv[0] <= e_xval; |
yv[0] <= e_yval; |
ph[0] <= phase_i; |
end |
3'b001,3'b010: |
begin // 45 .. 90, 90 .. 135 |
xv[0] <= -e_yval; |
yv[0] <= e_xval; |
ph[0] <= phase_i - 60'h400000000000000; |
end |
3'b011: |
begin // 135 .. 180, 180 .. 225 |
xv[0] <= -e_xval; |
yv[0] <= -e_yval; |
ph[0] <= phase_i - 60'h800000000000000; |
end |
3'b100: |
begin // 180 .. 225 |
xv[0] <= -e_xval; |
yv[0] <= -e_yval; |
ph[0] <= phase_i - 60'h800000000000000; |
end |
3'b101,3'b110: |
begin // 225 .. 270, 270 .. 315 |
xv[0] <= e_yval; |
yv[0] <= -e_xval; |
ph[0] <= phase_i - 60'hC00000000000000; |
end |
3'b111: |
begin // 315 .. 360, No change |
xv[0] <= e_xval; |
yv[0] <= e_yval; |
ph[0] <= phase_i; |
ph[0][PW] <= 1'b1; // Make phase negative |
end |
endcase |
end |
end |
xv[1] <= ({{60{xv[0][WW-1]}},xv[0]} * INV_GAIN) >>> 8'd54; |
yv[1] <= ({{60{yv[0][WW-1]}},yv[0]} * INV_GAIN) >>> 8'd54; |
ph[1] <= ph[0]; |
xv[2] <= xv[1]; |
yv[2] <= yv[1]; |
ph[2] <= ph[1]; |
xv[3] <= xv[2]; |
yv[3] <= yv[2]; |
ph[3] <= ph[2]; |
if (cnt <= 6'd8) begin |
xv[4] <= xv[3]; |
yv[4] <= yv[3]; |
ph[4] <= ph[3]; |
end |
else if (cnt > 6'd8 && cnt < 8'd60) begin |
if (arctan ? ~yv5[WW-1] : ph5[PW]) // Negative phase |
begin |
// If the phase is negative, rotate by the |
// CORDIC angle in a clockwise direction. |
xv[4] <= xv5 + (yv5 >>> (cnt - 8'd9)); |
yv[4] <= yv5 - (xv5 >>> (cnt - 8'd9)); |
ph[4] <= ph5 + cordic_angle[cnt-8'd9]; |
|
end |
else begin |
// On the other hand, if the phase is |
// positive ... rotate in the |
// counter-clockwise direction |
xv[4] <= xv5 - (yv5 >>> (cnt - 8'd9)); |
yv[4] <= yv5 + (xv5 >>> (cnt - 8'd9)); |
ph[4] <= ph5 - cordic_angle[cnt-8'd9]; |
end |
end |
else if (cnt==8'd60) begin |
xv[4] <= xv[4];//({{54{xv[4][WW-1]}},xv[4]} * INV_GAIN) >>> 8'd54; |
yv[4] <= yv[4];//({{54{xv[4][WW-1]}},yv[4]} * INV_GAIN) >>> 8'd54; |
ph[4] <= ph[4]; |
end |
else if (cnt==8'd62) begin |
xval_o <= pre_xval[(WW-1):(WW-OW)]; |
yval_o <= pre_yval[(WW-1):(WW-OW)]; |
phase_o <= ph[4]; |
end |
/* |
else if (cnt==8'd64) begin |
case(cr_rot) |
3'd0,3'd7: |
begin |
xval_o <= xval_o; |
yval_o <= yval_o; |
phase_o <= phase_o; |
phase_o[PW] <= 1'b0; |
end |
3'd1,3'd2: |
begin |
xval_o <= xval_o; |
yval_o <= yval_o; |
phase_o <= phase_o + 60'h400000000000000; |
end |
3'd3: |
begin |
xval_o <= xval_o; |
yval_o <= yval_o; |
phase_o <= phase_o + 60'h800000000000000; |
end |
3'd4: |
begin |
xval_o <= xval_o; |
yval_o <= yval_o; |
phase_o <= phase_o + 60'h800000000000000; |
end |
3'd5,3'd6: |
begin |
xval_o <= xval_o; |
yval_o <= yval_o; |
phase_o <= phase_o + 60'hC00000000000000; |
end |
endcase |
end |
*/ |
end |
|
endmodule |
/rtl/verilog2/fpCvt16To128.sv
0,0 → 1,61
`timescale 1ns / 1ps |
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2023 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// fpCvt16To128.sv |
// - decimal floating convert half to quad |
// |
// |
// BSD 3-Clause License |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions are met: |
// |
// 1. Redistributions of source code must retain the above copyright notice, this |
// list of conditions and the following disclaimer. |
// |
// 2. Redistributions in binary form must reproduce the above copyright notice, |
// this list of conditions and the following disclaimer in the documentation |
// and/or other materials provided with the distribution. |
// |
// 3. Neither the name of the copyright holder nor the names of its |
// contributors may be used to endorse or promote products derived from |
// this software without specific prior written permission. |
// |
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
// |
// ============================================================================ |
|
import fp16Pkg::*; |
import fp128Pkg::*; |
|
module fpCvt16To128(i, o); |
input FP16 i; |
output FP128 o; |
|
wire [15:0] bias128 = 15'h3FFF; |
wire [ 4:0] bias16 = 5'h0F; |
|
always_comb |
o.sign = i.sign; |
always_comb |
if (i.exp==5'h1F) // Keep infinity / nan status |
o.exp = 15'h7FFF; |
else |
o.exp = bias128 - bias16 + i.exp; |
always_comb |
o.sig = {i.sig,102'd0}; |
|
endmodule |
/rtl/verilog2/fpCvt16To64.sv
0,0 → 1,61
`timescale 1ns / 1ps |
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2023 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// fpCvt16To64.sv |
// - decimal floating convert half to double |
// |
// |
// BSD 3-Clause License |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions are met: |
// |
// 1. Redistributions of source code must retain the above copyright notice, this |
// list of conditions and the following disclaimer. |
// |
// 2. Redistributions in binary form must reproduce the above copyright notice, |
// this list of conditions and the following disclaimer in the documentation |
// and/or other materials provided with the distribution. |
// |
// 3. Neither the name of the copyright holder nor the names of its |
// contributors may be used to endorse or promote products derived from |
// this software without specific prior written permission. |
// |
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
// |
// ============================================================================ |
|
import fp16Pkg::*; |
import fp64Pkg::*; |
|
module fpCvt16To64(i, o); |
input FP16 i; |
output FP64 o; |
|
wire [10:0] bias64 = 11'h3FF; |
wire [ 4:0] bias16 = 5'h0F; |
|
always_comb |
o.sign = i.sign; |
always_comb |
if (i.exp==5'h1F) // Keep infinity / nan status |
o.exp = 11'h7FF; |
else |
o.exp = bias64 - bias16 + i.exp; |
always_comb |
o.sig = {i.sig,43'd0}; |
|
endmodule |
/rtl/verilog2/fpCvt32To64.sv
0,0 → 1,61
`timescale 1ns / 1ps |
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// fpCvt32To64.sv |
// - decimal floating convert single to double |
// |
// |
// BSD 3-Clause License |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions are met: |
// |
// 1. Redistributions of source code must retain the above copyright notice, this |
// list of conditions and the following disclaimer. |
// |
// 2. Redistributions in binary form must reproduce the above copyright notice, |
// this list of conditions and the following disclaimer in the documentation |
// and/or other materials provided with the distribution. |
// |
// 3. Neither the name of the copyright holder nor the names of its |
// contributors may be used to endorse or promote products derived from |
// this software without specific prior written permission. |
// |
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
// |
// ============================================================================ |
|
import fp32Pkg::*; |
import fp64Pkg::*; |
|
module fpCvt32To64(i, o); |
input FP32 i; |
output FP64 o; |
|
wire [10:0] bias64 = 11'h3FF; |
wire [ 7:0] bias32 = 8'h7F; |
|
always_comb |
o.sign = i.sign; |
always_comb |
if (i.exp==8'hFF) // Keep infinity / nan status |
o.exp = 11'h7FF; |
else |
o.exp = bias64 - bias32 + i.exp; |
always_comb |
o.sig = {i.sig,29'd0}; |
|
endmodule |
/rtl/verilog2/fpCvt64To128.sv
0,0 → 1,61
`timescale 1ns / 1ps |
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// fpCvt32To96.sv |
// - decimal floating convert double to triple |
// |
// |
// BSD 3-Clause License |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions are met: |
// |
// 1. Redistributions of source code must retain the above copyright notice, this |
// list of conditions and the following disclaimer. |
// |
// 2. Redistributions in binary form must reproduce the above copyright notice, |
// this list of conditions and the following disclaimer in the documentation |
// and/or other materials provided with the distribution. |
// |
// 3. Neither the name of the copyright holder nor the names of its |
// contributors may be used to endorse or promote products derived from |
// this software without specific prior written permission. |
// |
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
// |
// ============================================================================ |
|
import fp64Pkg::*; |
import fp128Pkg::*; |
|
module fpCvt64To128(i, o); |
input FP64 i; |
output FP128 o; |
|
wire [14:0] bias128 = 15'h3FFF; |
wire [10:0] bias64 = 11'h3FF; |
|
always_comb |
o.sign = i.sign; |
always_comb |
if (i.exp==11'h7FF) // Keep infinity / nan status |
o.exp = 15'h7FFF; |
else |
o.exp = bias128 - bias64 + i.exp; |
always_comb |
o.sig = {i.sig,60'd0}; |
|
endmodule |
/rtl/verilog2/fpDecomp128Reg.sv
0,0 → 1,99
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// fpDecomp128Reg.v |
// - decompose floating point value with registered outputs |
// - parameterized width |
// |
// |
// This source file is free software: you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or |
// (at your option) any later version. |
// |
// This source file is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
// GNU General Public License for more details. |
// |
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// |
// ============================================================================ |
|
import fp128Pkg::*; |
|
module fpDecomp128(i, sgn, exp, man, fract, xz, mz, vz, inf, xinf, qnan, snan, nan); |
input FP128 i; |
output sgn; |
output [fp128Pkg::EMSB:0] exp; |
output [fp128Pkg::FMSB:0] man; |
output [fp128Pkg::FMSB+1:0] fract; // mantissa with hidden bit recovered |
output xz; // denormalized - exponent is zero |
output mz; // mantissa is zero |
output vz; // value is zero (both exponent and mantissa are zero) |
output inf; // all ones exponent, zero mantissa |
output xinf; // all ones exponent |
output qnan; // nan |
output snan; // signalling nan |
output nan; |
|
// Decompose input |
assign sgn = i.sign; |
assign exp = i.exp; |
assign man = i.sig; |
assign xz = !(|exp); // denormalized - exponent is zero |
assign mz = !(|man); // mantissa is zero |
assign vz = xz & mz; // value is zero (both exponent and mantissa are zero) |
assign inf = &exp & mz; // all ones exponent, zero mantissa |
assign xinf = &exp; |
assign qnan = &exp & man[fp128Pkg::FMSB]; |
assign snan = &exp & !man[fp128Pkg::FMSB] & !mz; |
assign nan = &exp & !mz; |
assign fract = {!xz,i.sig}; |
|
endmodule |
|
|
module fpDecomp128Reg(clk, ce, i, o, sgn, exp, man, fract, xz, mz, vz, inf, xinf, qnan, snan, nan); |
input clk; |
input ce; |
input FP128 i; |
|
output FP128 o; |
output reg sgn; |
output reg [fp128Pkg::EMSB:0] exp; |
output reg [fp128Pkg::FMSB:0] man; |
output reg [fp128Pkg::FMSB+1:0] fract; // mantissa with hidden bit recovered |
output reg xz; // denormalized - exponent is zero |
output reg mz; // mantissa is zero |
output reg vz; // value is zero (both exponent and mantissa are zero) |
output reg inf; // all ones exponent, zero mantissa |
output reg xinf; // all ones exponent |
output reg qnan; // nan |
output reg snan; // signalling nan |
output reg nan; |
|
// Decompose input |
always_ff @(posedge clk) |
if (ce) begin |
o <= i; |
sgn = i.sign; |
exp = i.exp; |
man = i.sig; |
xz = !(|exp); // denormalized - exponent is zero |
mz = !(|man); // mantissa is zero |
vz = xz & mz; // value is zero (both exponent and mantissa are zero) |
inf = &exp & mz; // all ones exponent, zero mantissa |
xinf = &exp; |
qnan = &exp & man[fp128Pkg::FMSB]; |
snan = &exp & !man[fp128Pkg::FMSB] & !mz; |
nan = &exp & !mz; |
fract = {|exp,i.sig}; |
end |
|
endmodule |
/rtl/verilog2/fpSincos64.sv
0,0 → 1,235
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2023 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// |
// BSD 3-Clause License |
// Redistribution and use in source and binary forms, with or without |
// modification, are permitted provided that the following conditions are met: |
// |
// 1. Redistributions of source code must retain the above copyright notice, this |
// list of conditions and the following disclaimer. |
// |
// 2. Redistributions in binary form must reproduce the above copyright notice, |
// this list of conditions and the following disclaimer in the documentation |
// and/or other materials provided with the distribution. |
// |
// 3. Neither the name of the copyright holder nor the names of its |
// contributors may be used to endorse or promote products derived from |
// this software without specific prior written permission. |
// |
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
// |
// ============================================================================ |
|
import fp64Pkg::*; |
|
module fpSincos64(rst, clk, rm, ld, a, sin, cos); |
input rst; |
input clk; |
input [2:0] rm; |
input ld; |
input FP64 a; |
output FP64 sin; |
output FP64 cos; |
|
FP64 aa; |
FP64X sinx, cosx; |
wire FP64N fpn_sin, fpn_cos; |
reg [59:0] phase_i; |
wire [EMSB:0] exp; |
reg [EMSB:0] exp1,exp2,exp3,exp4; |
wire [FMSB+1:0] fract; |
reg [FMSB+10:0] fract1,fract2,fract3,fract4; |
wire [53:0] xval, yval; |
wire [59:0] phase; |
wire nan; |
wire cdone; |
wire vz; |
reg ld1, ld2, ld3, ld4, ld5; |
|
fpDecomp64Reg u4 |
( |
.clk(clk), |
.ce(1'b1), |
.i(aa), |
.o(), |
.sgn(sgn), |
.exp(exp), |
.man(), |
.fract(fract), |
.xz(), |
.mz(), |
.vz(vz), |
.inf(), |
.xinf(), |
.qnan(), |
.snan(), |
.nan(nan) |
); |
|
wire signed [11:0] expdif = 11'h3ff - exp; |
|
always_ff @(posedge clk) |
if (rst) begin |
fract1 <= 'd0; |
fract2 <= 'd0; |
ld1 <= 'd0; |
ld2 <= 'd0; |
ld3 <= 'd0; |
ld4 <= 'd0; |
ld5 <= 'd0; |
aa <= 'd0; |
end |
else begin |
if (ld) |
aa <= a; |
ld1 <= ld; |
ld2 <= ld1; |
ld3 <= ld2; |
ld4 <= ld3; |
ld5 <= ld4; |
if (vz) begin |
fract1 <= 'd0; |
exp1 <= 'd0; |
end |
else if (expdif[11]) begin // expdif < 0? |
fract1 <= {fract,7'b0} << -expdif; |
exp1 <= exp + expdif; |
end |
else if (expdif > 13'd53) begin |
fract1 <= 'd0; |
exp1 <= exp + 6'd53; |
end |
else if (expdif > 0) begin// negative? |
fract1 <= {fract,7'b0} >> expdif[5:0]; |
exp1 <= exp + expdif; |
end |
else if (expdif=='d0) begin |
fract1 <= {fract,7'b0}; |
exp1 <= exp; |
end |
exp2 <= exp1; |
exp3 <= exp2; |
exp4 <= exp3; |
fract2 <= ({61'd0,fract1} * 61'h517cc1b727220c0) >> 8'd61; |
fract3 <= fract2; |
fract4 <= fract3; |
end |
|
wire [6:0] ylz, xlz; |
cntlz64 uclzy( |
.i({yval[53] ? -yval[52:0] : yval[52:0],11'd0}), |
.o(ylz) |
); |
cntlz64 uclzx ( |
.i({xval[53] ? -xval[52:0] : xval[52:0],11'd0}), |
.o(xlz) |
); |
|
always_ff @(posedge clk) |
if (rst) begin |
sinx <= 'd0; |
cosx <= 'd0; |
end |
else begin |
if (cdone) begin |
if (nan) begin |
sinx.sign <= a.sign; |
sinx.exp <= a.exp; |
sinx.sig <= {a.sig,a.sig}; |
cosx.sign <= a.sign; |
cosx.exp <= a.exp; |
cosx.sig <= {a.sig,a.sig}; |
end |
else begin |
sinx.sign <= yval[53]; |
sinx.exp <= exp4 - 2'd1 - ylz; // 2^1 |
if (yval[53]) |
sinx.sig <= {-yval[51:0],54'd0} << ylz; |
else |
sinx.sig <= {yval[51:0],54'd0} << ylz; |
cosx.sign <= xval[53]; |
cosx.exp <= exp4 - 2'd1 - xlz; |
if (xval[53]) begin |
cosx.sig <= {-xval[51:0],54'd0} << xlz; |
end |
else |
cosx.sig <= {xval[51:0],54'd0} << xlz; |
end |
end |
end |
|
fpCordic u1 |
( |
.rst(rst), |
.clk(clk), |
.arctan(1'b0), |
.ld(ld5), |
.phase_i({fract4[FMSB+8:0],1'b0}), |
.xval_i(54'h10000000000000), |
.yval_i(54'h00000000000000), |
.xval_o(xval), |
.yval_o(yval), |
.phase_o(phase), |
.done(cdone) |
); |
|
fpNormalize64 u2 |
( |
.clk(clk), |
.ce(1'b1), |
.under_i(1'b0), |
.i(sinx), |
.o(fpn_sin) |
); |
|
fpRound64 u3 |
( |
.clk(clk), |
.ce(1'b1), |
.rm(rm), |
.i(fpn_sin), |
.o(sin) |
); |
|
fpNormalize64 u5 |
( |
.clk(clk), |
.ce(1'b1), |
.under_i(1'b0), |
.i(cosx), |
.o(fpn_cos) |
); |
|
fpRound64 u6 |
( |
.clk(clk), |
.ce(1'b1), |
.rm(rm), |
.i(fpn_cos), |
.o(cos) |
); |
|
vtdl #(.WID(1), .DEP(16)) u7 |
( |
.clk(clk), |
.ce(1'b1), |
.a(4'd11), |
.d(cdone), |
.q(done) |
); |
|
endmodule |
/test_bench/fpSincos_tb.sv
0,0 → 1,109
`timescale 1ns / 1ps |
// ============================================================================ |
// __ |
// \\__/ o\ (C) 2023 Robert Finch, Waterloo |
// \ __ / All rights reserved. |
// \/_// robfinch<remove>@finitron.ca |
// || |
// |
// fpSincos_tb.sv |
// - floating point sin/cosine test bench |
// |
// This source file is free software: you can redistribute it and/or modify |
// it under the terms of the GNU Lesser General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or |
// (at your option) any later version. |
// |
// This source file is distributed in the hope that it will be useful, |
// but WITHOUT ANY WARRANTY; without even the implied warranty of |
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
// GNU General Public License for more details. |
// |
// You should have received a copy of the GNU General Public License |
// along with this program. If not, see <http://www.gnu.org/licenses/>. |
// |
// Floating Point Multiplier / Divider |
// |
// This multiplier/divider handles denormalized numbers. |
// The output format is of an internal expanded representation |
// in preparation to be fed into a normalization unit, then |
// rounding. Basically, it's the same as the regular format |
// except the mantissa is doubled in size, the leading two |
// bits of which are assumed to be whole bits. |
// |
// |
// ============================================================================ |
|
import fp64Pkg::*; |
|
module fpSincos_tb(); |
reg rst; |
reg clk; |
reg [15:0] adr; |
reg [63:0] b; |
wire [63:0] o; |
reg [63:0] ad,bd; |
wire [63:0] od; |
reg [3:0] rm; |
wire [63:0] sin, cos; |
real a,aa,ab,ac; |
//wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}}; |
//wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}}; |
|
integer outfile; |
|
initial begin |
rst = 1'b0; |
clk = 1'b0; |
adr = 0; |
a = $urandom(1); |
#20 rst = 1; |
#50 rst = 0; |
#1000000 $fclose(outfile); |
#10 $finish; |
end |
|
always #5 |
clk = ~clk; |
|
reg [7:0] count; |
wire ld = count==4; |
always @(posedge clk) |
if (rst) begin |
adr <= 0; |
count <= 0; |
a <= 0.0; |
end |
else |
begin |
if (adr==0) begin |
outfile = $fopen("f:/cores2023/Float/fpu/test_bench/fpSincos_tvo.txt", "wb"); |
$fwrite(outfile, "rm ------ A ------ ------ SIN ----- ---- SIM sin ---- ------ COS ----- ---- SIM cos ---\n"); |
end |
count <= count + 1; |
if (count > 76) |
count <= 1'd1; |
if (ld) begin |
a <= a + 0.01; |
// a.sign = 1'b0; |
// a.exp = 11'h3fe; |
// a.sig = {$urandom(),20'd0}; |
rm <= 3'd0; |
// a[31:0] <= $urandom(); |
// a[63:32] <= $urandom(); |
// rm <= adr[15:13]; |
//ad <= memd[adr][63: 0]; |
//bd <= memd[adr][127:64]; |
end |
if (count==76) begin |
aa <= a; |
ab <= aa; |
ac <= ab; |
$fwrite(outfile, "%h\t%h\t%h\t%h\t%h\t%h\n", rm, $realtobits(ab), sin, $realtobits($sin(ab)), cos, $realtobits($cos(ab))); |
adr <= adr + 1; |
end |
end |
|
fpSincos64 u6 (rst, clk, 3'd0, ld, $realtobits(a), sin, cos); |
|
endmodule |