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    from Rev 76 to Rev 77
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Rev 76 → Rev 77

/trunk/test_bench/DFPAddsub96_tb.v
0,0 → 1,157
`timescale 1ns / 1ps
// ============================================================================
// __
// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFPAddsub96_tb.v
// - decimal floating point addsub test bench
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
module DFPAddsub96_tb();
reg rst;
reg clk;
reg [15:0] adr;
reg [95:0] a,b;
wire [95:0] o;
reg [95:0] ad,bd;
reg [95:0] od;
reg [3:0] rm;
 
integer n;
reg [95:0] a1, b1;
wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}};
wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}};
 
integer outfile;
 
initial begin
rst = 1'b0;
clk = 1'b0;
adr = 0;
a = $urandom(1);
b = 1;
#20 rst = 1;
#50 rst = 0;
#10000000 $fclose(outfile);
#10 $finish;
end
 
always #5
clk = ~clk;
 
genvar g;
generate begin : gRand
for (g = 0; g < 96; g = g + 4) begin
always @(posedge clk) begin
a1[g+3:g] <= $urandom() % 10;
b1[g+3:g] <= $urandom() % 10;
end
end
end
endgenerate
 
reg [7:0] count;
always @(posedge clk)
if (rst) begin
adr <= 0;
count <= 0;
end
else
begin
if (adr==0) begin
outfile = $fopen("f:/cores2022/Float/dfpu/test_bench/DFPAddsub96_tvo.txt", "wb");
$fwrite(outfile, " rm ------- A ------ ------- B ------ ------ sum ----- -- SIM Sum --\n");
end
count <= count + 1;
if (count > 35)
count <= 1'd1;
if (count==2) begin
a <= a1;
b <= b1;
a[95:92] <= 4'h5;
b[95:92] <= 4'h5;
rm <= adr[14:12];
//ad <= memd[adr][63: 0];
//bd <= memd[adr][127:64];
end
if (adr==1 && count==2) begin
a <= 96'h25ff00000000000000000000; // 1
b <= 96'h25ff00000000000000000000; // 1
end
if (adr==2 && count==2) begin
a <= 96'h260000000000000000000000; // 10
b <= 96'h260000000000000000000000; // 10
end
if (adr==3 && count==2) begin
a <= 96'h260100000000000000000000; // 100
b <= 96'h260100000000000000000000; // 100
end
if (adr==4 && count==2) begin
a <= 96'h260200000000000000000000; // 1000
b <= 96'h260200000000000000000000; // 1000
end
if (adr==5 && count==2) begin
a <= 96'h26064D2E7030000000000000; // 12345678
b <= 96'h260000000000000000000000; // 10
end
if (adr==6 && count==2) begin
a <= 96'h440000000000000000000000;
b <= 96'h440000000000000000000000;
end
if (adr==7 && count==2) begin
a <= 96'h440040000000000000000000;
b <= 96'h440040000000000000000000;
end
if (count==35) begin
if (adr[11]) begin
$fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "-",rm, a, b, o);
end
else begin
$fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "+",rm, a, b, o);
end
adr <= adr + 1;
end
end
 
//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
DFPAddsub96nr u6 (
.clk(clk),
.ce(1'b1),
.op(adr[11]),
.a(a),
.b(b),
.o(o),
.rm(rm)
);
 
endmodule
/trunk/test_bench/DFPMultiply96_tb.v
0,0 → 1,139
`timescale 1ns / 1ps
// ============================================================================
// __
// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFPMultiply96_tb.v
// - decimal floating point multiplier test bench
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Floating Point Multiplier / Divider
//
// This multiplier/divider handles denormalized numbers.
// The output format is of an internal expanded representation
// in preparation to be fed into a normalization unit, then
// rounding. Basically, it's the same as the regular format
// except the mantissa is doubled in size, the leading two
// bits of which are assumed to be whole bits.
//
//
// ============================================================================
 
module DFPMultiply96_tb();
parameter N=24;
reg rst;
reg clk;
reg [15:0] adr;
reg [95:0] a,b;
wire [95:0] o;
reg [3:0] rm;
 
integer n;
reg [95:0] a1, b1;
wire done;
reg ld;
 
integer outfile;
 
initial begin
rst = 1'b0;
clk = 1'b0;
adr = 0;
a = $urandom(1);
#20 rst = 1;
#50 rst = 0;
#2000000 $fclose(outfile);
#10 $finish;
end
 
always #5
clk = ~clk;
 
genvar g;
generate begin : gRand
for (g = 0; g < N*4+16+4; g = g + 4) begin
always @(posedge clk) begin
a1[g+3:g] <= $urandom() % 16;
b1[g+3:g] <= $urandom() % 16;
end
end
end
endgenerate
 
reg [9:0] count;
always @(posedge clk)
if (rst) begin
adr <= 0;
count <= 0;
end
else
begin
ld <= 1'b0;
if (adr==0) begin
outfile = $fopen("f:/cores2022/Float/dfpu/test_bench/DFPMultiply96_tvo.txt", "wb");
$fwrite(outfile, "rm ------ A ------ ------- B ------ - DUT Product - - SIM Product -\n");
end
count <= count + 1;
if (count > 750)
count <= 1'd1;
if (count==2) begin
a <= a1;
b <= b1;
rm <= adr[15:13];
ld <= 1'b1;
//ad <= memd[adr][63: 0];
//bd <= memd[adr][127:64];
end
if (adr==1 && count==2) begin
a <= 96'h25ff00000000000000000000; // 1
b <= 96'h25ff00000000000000000000; // 1
end
if (adr==2 && count==2) begin
a <= 96'h260000000000000000000000; // 10
b <= 96'h260000000000000000000000; // 10
end
if (adr==3 && count==2) begin
a <= 96'h260100000000000000000000; // 100
b <= 96'h260100000000000000000000; // 100
end
if (adr==4 && count==2) begin
a <= 96'h260200000000000000000000; // 1000
b <= 96'h260200000000000000000000; // 1000
end
if (adr==5 && count==2) begin
a <= 96'h26064D2E7030000000000000; // 12345678
b <= 96'h260000000000000000000000; // 10
end
if (adr==6 && count==2) begin
a <= 96'h440000000000000000000000;
b <= 96'h440000000000000000000000;
end
if (adr==7 && count==2) begin
a <= 96'h440040000000000000000000;
b <= 96'h440040000000000000000000;
end
if (count==750) begin
$fwrite(outfile, "%h\t%h\t%h\t%h\n", rm, a, b, o);
adr <= adr + 1;
end
end
 
//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
DFPMultiply96nr u6 (clk, 1'b1, ld, a, b, o, rm, done);//, sign_exe, inf, overflow, underflow);
 
endmodule
/trunk/test_bench/i2df96_tb.sv
0,0 → 1,126
// ============================================================================
// __
// \\__/ o\ (C) 2022 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// iTodf96_tb.sv
// - test convert integer to decimal floating point
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
module i2df96_tb();
 
reg rst;
reg clk;
reg [15:0] adr;
wire [95:0] flt;
reg [7:0] count;
 
reg [95:0] bin;
 
integer outfile;
 
initial begin
rst = 1'b0;
clk = 1'b0;
adr = 0;
bin = $urandom(1);
#20 rst = 1;
#50 rst = 0;
#10000000 $fclose(outfile);
#10 $finish;
end
 
always #5
clk = ~clk;
 
genvar g;
generate begin : gRand
for (g = 0; g < 96; g = g + 4) begin
always @(posedge clk) begin
if (count==2)
bin[g+3:g] <= $urandom() % 16;
end
end
end
endgenerate
 
always @(posedge clk)
if (rst) begin
adr <= 0;
count <= 0;
end
else
begin
if (adr==0) begin
outfile = $fopen("f:/cores2022/float/dfpu/test_bench/i2df128_tvo.txt", "wb");
$fwrite(outfile, "s ------ bin ------ ------ flt ------ \n");
end
count <= count + 1;
if (count > 140)
count <= 1'd1;
if (adr==1) begin
bin <= 96'h01;
end
if (adr==2) begin
bin <= 96'h0A;
end
if (adr==3) begin
bin <= 96'd100;
end
if (adr==4) begin
bin <= 96'd1000;
end
if (adr==5) begin
bin <= 96'd1000000;
end
if (adr==6) begin
bin <= 96'd12345678;
end
if (count==140) begin
$fwrite(outfile, "%c %h\t%h\n", adr[11] ? "s" : "u", bin, flt);
adr <= adr + 1;
end
end
 
i2df96 u6 (
.rst(rst),
.clk(clk),
.ce(1'b1),
.op(adr[11]),
.rm(3'd0),
.ld(count==3),
.i(bin),
.o(flt),
.done()
);
 
endmodule

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