OpenCores
URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /funbase_ip_library/trunk
    from Rev 181 to Rev 182
    ↔ Reverse comparison
  •

Rev 181 → Rev 182

/TUT/ip.hwp.communication/hibi_pe_dma/1.0/vhd/hibi_pe_dma_hw.tcl
1,61 → 1,60
# TCL File Generated by Component Editor 10.0sp1
# Fri Feb 17 18:08:42 EET 2012
# TCL File Generated by Component Editor 12.1
# Tue Mar 26 18:40:28 EET 2013
# DO NOT MODIFY
 
 
# +-----------------------------------
# |
# | hibi_pe_dma "hibi_pe_dma" v1.0
# | null 2012.02.17.18:08:42
# |
# |
# | D:/user/lehton87/svn/daci_ip/trunk/ip.hwp.communication/hibi_pe_dma/1.0/vhd/hibi_pe_dma.vhd
# |
# | ./hpd_tx_control.vhd syn, sim
# | ./hpd_rx_packet.vhd syn, sim
# | ./hpd_rx_stream.vhd syn, sim
# | ./hpd_rx_and_conf.vhd syn, sim
# | ./hibi_pe_dma.vhd syn, sim
# |
# +-----------------------------------
#
# hibi_pe_dma "hibi_pe_dma" v1.0
# null 2013.03.26.18:40:28
#
#
 
# +-----------------------------------
# | request TCL package from ACDS 10.0
# |
package require -exact sopc 10.0
# |
# +-----------------------------------
#
# request TCL package from ACDS 12.1
#
package require -exact qsys 12.1
 
# +-----------------------------------
# | module hibi_pe_dma
# |
 
#
# module hibi_pe_dma
#
set_module_property NAME hibi_pe_dma
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP Other
set_module_property DISPLAY_NAME hibi_pe_dma
set_module_property TOP_LEVEL_HDL_FILE hibi_pe_dma.vhd
set_module_property TOP_LEVEL_HDL_MODULE hibi_pe_dma
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
# |
# +-----------------------------------
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
 
# +-----------------------------------
# | files
# |
add_file hpd_tx_control.vhd {SYNTHESIS SIMULATION}
add_file hpd_rx_packet.vhd {SYNTHESIS SIMULATION}
add_file hpd_rx_stream.vhd {SYNTHESIS SIMULATION}
add_file hpd_rx_and_conf.vhd {SYNTHESIS SIMULATION}
add_file hibi_pe_dma.vhd {SYNTHESIS SIMULATION}
# |
# +-----------------------------------
 
# +-----------------------------------
# | parameters
# |
#
# file sets
#
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL hibi_pe_dma
set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file hpd_tx_control.vhd VHDL PATH hpd_tx_control.vhd
add_fileset_file hpd_rx_packet.vhd VHDL PATH hpd_rx_packet.vhd
add_fileset_file hpd_rx_stream.vhd VHDL PATH hpd_rx_stream.vhd
add_fileset_file hpd_rx_and_conf.vhd VHDL PATH hpd_rx_and_conf.vhd
add_fileset_file hibi_pe_dma.vhd VHDL PATH hibi_pe_dma.vhd
 
add_fileset sim_vhdl SIM_VHDL "" "VHDL Simulation"
set_fileset_property sim_vhdl ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file hpd_tx_control.vhd VHDL PATH hpd_tx_control.vhd
add_fileset_file hpd_rx_packet.vhd VHDL PATH hpd_rx_packet.vhd
add_fileset_file hpd_rx_stream.vhd VHDL PATH hpd_rx_stream.vhd
add_fileset_file hpd_rx_and_conf.vhd VHDL PATH hpd_rx_and_conf.vhd
add_fileset_file hibi_pe_dma.vhd VHDL PATH hibi_pe_dma.vhd
 
 
#
# parameters
#
add_parameter data_width_g INTEGER 32
set_parameter_property data_width_g DEFAULT_VALUE 32
set_parameter_property data_width_g DISPLAY_NAME data_width_g
120,36 → 119,32
set_parameter_property hibi_addr_cmp_hi_g ALLOWED_RANGES -2147483648:2147483647
set_parameter_property hibi_addr_cmp_hi_g AFFECTS_GENERATION false
set_parameter_property hibi_addr_cmp_hi_g HDL_PARAMETER true
# |
# +-----------------------------------
 
# +-----------------------------------
# | display items
# |
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point avalon_slave_0
# |
#
# display items
#
 
 
#
# connection point avalon_slave_0
#
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressAlignment DYNAMIC
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clock_sink
set_interface_property avalon_slave_0 associatedReset clock_sink_reset
set_interface_property avalon_slave_0 bitsPerSymbol 8
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 burstcountUnits WORDS
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 isMemoryDevice false
set_interface_property avalon_slave_0 isNonVolatileStorage false
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 printableDevice false
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0
 
set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_sink
set_interface_property avalon_slave_0 ENABLED true
 
add_interface_port avalon_slave_0 avalon_cfg_addr_in address Input n_chans_bits_g+4
159,14 → 154,18
add_interface_port avalon_slave_0 avalon_cfg_waitrequest_out waitrequest Output 1
add_interface_port avalon_slave_0 avalon_cfg_writedata_in writedata Input addr_width_g
add_interface_port avalon_slave_0 avalon_cfg_readdata_out readdata Output addr_width_g
# |
# +-----------------------------------
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
 
# +-----------------------------------
# | connection point conduit_end
# |
 
#
# connection point conduit_end
#
add_interface conduit_end conduit end
 
set_interface_property conduit_end associatedClock ""
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
 
add_interface_port conduit_end hibi_data_in export Input data_width_g
179,59 → 178,61
add_interface_port conduit_end hibi_full_in export Input 1
add_interface_port conduit_end hibi_comm_out export Output 5
add_interface_port conduit_end hibi_we_out export Output 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point clock_sink
# |
 
#
# connection point clock_sink
#
add_interface clock_sink clock end
 
set_interface_property clock_sink clockRate 0
set_interface_property clock_sink ENABLED true
 
add_interface_port clock_sink clk clk Input 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point clock_sink_reset
# |
 
#
# connection point clock_sink_reset
#
add_interface clock_sink_reset reset end
set_interface_property clock_sink_reset associatedClock clock_sink
set_interface_property clock_sink_reset synchronousEdges DEASSERT
 
set_interface_property clock_sink_reset ASSOCIATED_CLOCK clock_sink
set_interface_property clock_sink_reset ENABLED true
 
add_interface_port clock_sink_reset rst_n reset_n Input 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point interrupt_sender
# |
 
#
# connection point interrupt_sender
#
add_interface interrupt_sender interrupt end
set_interface_property interrupt_sender associatedAddressablePoint avalon_slave_0
set_interface_property interrupt_sender associatedClock clock_sink
set_interface_property interrupt_sender associatedReset clock_sink_reset
 
set_interface_property interrupt_sender ASSOCIATED_CLOCK clock_sink
set_interface_property interrupt_sender ENABLED true
 
add_interface_port interrupt_sender rx_irq_out irq Output 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point avalon_master
# |
 
#
# connection point avalon_master
#
add_interface avalon_master avalon start
set_interface_property avalon_master addressUnits SYMBOLS
set_interface_property avalon_master associatedClock clock_sink
set_interface_property avalon_master associatedReset clock_sink_reset
set_interface_property avalon_master bitsPerSymbol 8
set_interface_property avalon_master burstOnBurstBoundariesOnly false
set_interface_property avalon_master burstcountUnits WORDS
set_interface_property avalon_master doStreamReads false
set_interface_property avalon_master doStreamWrites false
set_interface_property avalon_master holdTime 0
set_interface_property avalon_master linewrapBursts false
 
set_interface_property avalon_master ASSOCIATED_CLOCK ""
set_interface_property avalon_master maximumPendingReadTransactions 0
set_interface_property avalon_master readLatency 0
set_interface_property avalon_master readWaitTime 1
set_interface_property avalon_master setupTime 0
set_interface_property avalon_master timingUnits Cycles
set_interface_property avalon_master writeWaitTime 0
set_interface_property avalon_master ENABLED true
 
add_interface_port avalon_master avalon_addr_out_rx address Output addr_width_g
239,19 → 240,28
add_interface_port avalon_master avalon_be_out_rx byteenable Output data_width_g/8
add_interface_port avalon_master avalon_writedata_out_rx writedata Output data_width_g
add_interface_port avalon_master avalon_waitrequest_in_rx waitrequest Input 1
# |
# +-----------------------------------
 
# +-----------------------------------
# | connection point avalon_master_1
# |
 
#
# connection point avalon_master_1
#
add_interface avalon_master_1 avalon start
set_interface_property avalon_master_1 addressUnits SYMBOLS
set_interface_property avalon_master_1 associatedClock clock_sink
set_interface_property avalon_master_1 associatedReset clock_sink_reset
set_interface_property avalon_master_1 bitsPerSymbol 8
set_interface_property avalon_master_1 burstOnBurstBoundariesOnly false
set_interface_property avalon_master_1 burstcountUnits WORDS
set_interface_property avalon_master_1 doStreamReads false
set_interface_property avalon_master_1 doStreamWrites false
set_interface_property avalon_master_1 holdTime 0
set_interface_property avalon_master_1 linewrapBursts false
 
set_interface_property avalon_master_1 ASSOCIATED_CLOCK ""
set_interface_property avalon_master_1 maximumPendingReadTransactions 0
set_interface_property avalon_master_1 readLatency 0
set_interface_property avalon_master_1 readWaitTime 1
set_interface_property avalon_master_1 setupTime 0
set_interface_property avalon_master_1 timingUnits Cycles
set_interface_property avalon_master_1 writeWaitTime 0
set_interface_property avalon_master_1 ENABLED true
 
add_interface_port avalon_master_1 avalon_readdatavalid_in_tx readdatavalid Input 1
259,5 → 269,4
add_interface_port avalon_master_1 avalon_readdata_in_tx readdata Input data_width_g
add_interface_port avalon_master_1 avalon_re_out_tx read Output 1
add_interface_port avalon_master_1 avalon_addr_out_tx address Output addr_width_g
# |
# +-----------------------------------
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.