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URL https://opencores.org/ocsvn/galois_lfsr/galois_lfsr/trunk

Subversion Repositories galois_lfsr

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  • This comparison shows the changes necessary to convert path 
    /galois_lfsr/trunk
    from Rev 6 to Rev 7
    ↔ Reverse comparison
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Rev 6 → Rev 7

/rtl/user.vhdl
36,7 → 36,11
from http://www.opencores.org/lgpl.shtml.
*/
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
--use work.types.all;
/* Enable for synthesis; comment out for simulation.
For this design, we just need boolean_vector. This is already included in Questa/ModelSim,
but Quartus doesn't yet support this.
*/
use work.types.all;
 
entity user is
generic(
50,7 → 54,7
);
port(
/* Comment-out for simulation. */
--clk,reset:in std_ulogic;
clk,reset:in std_ulogic;
msg:in unsigned(tapVector'high downto 0):=9x"57";
crc32:out unsigned(31 downto 0):=(others=>'0')
);
/rtl/galois-lfsr.vhdl
40,7 → 40,11
from http://www.opencores.org/lgpl.shtml.
*/
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
--use work.types.all;
/* Enable for synthesis; comment out for simulation.
For this design, we just need boolean_vector. This is already included in Questa/ModelSim,
but Quartus doesn't yet support this.
*/
use work.types.all;
 
entity lfsr is generic(
/*
75,11 → 79,10
/* Receives a vector of taps; generates LFSR structure with correct XOR positionings. */
tapGenr: for i in 0 to taps'high-1 generate
i_d(i+1)<=x(i) when taps(i) else i_q(i);
x(i)<=i_q(i) xor i_q(taps'high); -- when nReset else '0';
x(i)<=i_q(i) xor i_q(taps'high);
end generate;
process(nReset,load,seed,clk) is begin
--if nReset='0' or load then i_q<=seed;
if nReset='0' then i_q<=(others=>'0');
elsif load then i_q<=seed;
elsif rising_edge(clk) then
/rtl/packages/pkg-types.vhdl
0,0 → 1,48
/*
Tauhop Solutions common types.
Author(s):
- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
Copyright (C) 2012-2013 Authors and OPENCORES.ORG
This source file may be used and distributed without
restriction provided that this copyright statement is not
removed from the file and that any derivative work contains
the original copyright notice and the associated disclaimer.
This source file is free software; you can redistribute it
and/or modify it under the terms of the GNU Lesser General
Public License as published by the Free Software Foundation;
either version 2.1 of the License, or (at your option) any
later version.
This source is distributed in the hope that it will be
useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE. See the GNU Lesser General Public License for more
details.
You should have received a copy of the GNU Lesser General
Public License along with this source; if not, download it
from http://www.opencores.org/lgpl.shtml.
*/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
 
package types is
type byte is array(7 downto 0) of std_logic;
type byte_vector is array(natural range <>) of byte;
/* VHDL-2008 datatypes.
Comment out for simulation. Questa/ModelSim already supports this.
*/
type boolean_vector is array(natural range <>) of boolean;
type integer_vector is array(natural range <>) of integer;
/* [end]: VHDL-2008 datatypes. */
end package types;
 
package body types is
end package body types;

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