URL
https://opencores.org/ocsvn/galois_lfsr/galois_lfsr/trunk
Subversion Repositories galois_lfsr
Compare Revisions
- This comparison shows the changes necessary to convert path
/galois_lfsr/trunk
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/testbench/questa/waves.do
6,14 → 6,12
add wave -position end sim:/user/parallelLoad |
add wave -position end sim:/user/loadEn |
add wave -position end sim:/user/computeClk |
#add wave -position end -hexadecimal sim:/user/rgmiiMac_in |
#add wave -position end -expand -hexadecimal sim:/user/rgmiiMac_out |
add wave -position end sim:/user/d |
add wave -position end sim:/user/crc32 |
add wave -position end sim:/user/i_lfsr/i_d |
add wave -position end sim:/user/i_lfsr/i_q |
add wave -position end sim:/user/i_lfsr/x |
add wave -position end sim:/user/msg |
add wave -position end -hexadecimal sim:/user/crc32 |
add wave -position end -hexadecimal sim:/user/i_lfsr/i_d |
add wave -position end -hexadecimal sim:/user/i_lfsr/i_q |
add wave -position end -hexadecimal sim:/user/i_lfsr/x |
add wave -position end -hexadecimal sim:/user/msg |
add wave -position end sim:/user/i_loaded |
add wave -position end sim:/user/i_computed |
|
/rtl/user.vhdl
40,7 → 40,7
For this design, we just need boolean_vector. This is already included in Questa/ModelSim, |
but Quartus doesn't yet support this. |
*/ |
use work.types.all; |
--use work.types.all; |
|
entity user is |
generic( |
54,7 → 54,7
); |
port( |
/* Comment-out for simulation. */ |
clk,reset:in std_ulogic; |
-- clk,reset:in std_ulogic; |
msg:in unsigned(tapVector'high downto 0):=9x"57"; |
crc32:out unsigned(31 downto 0):=(others=>'0') |
); |
/rtl/quartus-synthesis/user.vhdl
0,0 → 1,141
/* |
This file is part of the Galois Linear Feedback Shift Register |
(galois_lfsr) project: |
http://www.opencores.org/project,galois_lfsr |
|
Description |
Synthesisable use case for Galois LFSR. |
This example is a CRC generator that uses a Galois LFSR. |
|
ToDo: |
|
Author(s): |
- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com |
|
Copyright (C) 2012-2013 Authors and OPENCORES.ORG |
|
This source file may be used and distributed without |
restriction provided that this copyright statement is not |
removed from the file and that any derivative work contains |
the original copyright notice and the associated disclaimer. |
|
This source file is free software; you can redistribute it |
and/or modify it under the terms of the GNU Lesser General |
Public License as published by the Free Software Foundation; |
either version 2.1 of the License, or (at your option) any |
later version. |
|
This source is distributed in the hope that it will be |
useful, but WITHOUT ANY WARRANTY; without even the implied |
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
PURPOSE. See the GNU Lesser General Public License for more |
details. |
|
You should have received a copy of the GNU Lesser General |
Public License along with this source; if not, download it |
from http://www.opencores.org/lgpl.shtml. |
*/ |
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all; |
/* Enable for synthesis; comment out for simulation. |
For this design, we just need boolean_vector. This is already included in Questa/ModelSim, |
but Quartus doesn't yet support this. |
*/ |
use work.types.all; |
|
entity user is |
generic( |
parallelLoad:boolean:=false; |
tapVector:boolean_vector:=( |
/* Example polynomial from Wikipedia: |
http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks |
*/ |
0|1|2|8=>true, 7 downto 3=>false |
) |
); |
port( |
/* Comment-out for simulation. */ |
clk,reset:in std_ulogic; |
msg:in unsigned(tapVector'high downto 0):=9x"57"; |
crc32:out unsigned(31 downto 0):=(others=>'0') |
); |
end entity user; |
|
architecture rtl of user is |
signal n,c:natural; |
|
/* Tester signals. */ |
signal d:std_ulogic; |
/* synthesis translate_off */ |
signal clk,reset:std_ulogic:='0'; |
/* synthesis translate_on */ |
|
signal loadEn,computeClk:std_ulogic; -- clock gating. |
signal loaded,i_loaded:boolean; |
signal computed,i_computed:boolean; |
|
begin |
/* Simulation Tester. */ |
/* synthesis translate_off */ |
clk<=not clk after 10 ps; |
|
process is begin |
reset<='0'; wait for 1 ps; |
reset<='1'; wait for 500 ps; |
reset<='0'; |
wait; |
end process; |
/* synthesis translate_on */ |
|
loadEn<=clk when reset='0' and not i_computed else '0'; |
computeClk<=clk when reset='0' and i_loaded and not i_computed else '0'; |
|
/* Galois LFSR instance. */ |
i_lfsr: entity work.lfsr(rtl) |
generic map(taps=>tapVector) |
/*generic map(taps => ( |
0|1|2|8=>true, |
7 downto 3=>false |
))*/ |
port map(nReset=>not reset, clk=>loadEn, |
load=>parallelLoad, |
seed=>msg, |
d=>d, |
q=>crc32(msg'range) |
); |
|
/* Load message into LFSR. */ |
process(reset,loadEn) is begin |
if reset then loaded<=false; n<=msg'length-1; d<='0'; |
elsif rising_edge(loadEn) then |
d<='0'; |
|
/* for parallel mode, LFSR automatically loads the seed in parallel. */ |
if parallelLoad then d<='0'; loaded<=true; |
else |
if not loaded then d<=msg(n); end if; |
|
if n>0 then n<=n-1; |
else loaded<=true; |
end if; |
end if; |
end if; |
end process; |
|
/* Shift zeroes into LFSR after message has been loaded completely. */ |
process(reset,loaded,computeClk) is begin |
if reset='1' or not loaded then computed<=false; c<=msg'length-1; |
elsif rising_edge(computeClk) then |
if c>0 then c<=c-1; |
else computed<=true; |
end if; |
end if; |
end process; |
|
/* Register pipelines. */ |
process(clk) is begin |
if falling_edge(clk) then |
i_loaded<=loaded; |
i_computed<=computed; |
end if; |
end process; |
end architecture rtl; |
rtl/quartus-synthesis/user.vhdl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/quartus-synthesis/galois-lfsr.vhdl
===================================================================
--- rtl/quartus-synthesis/galois-lfsr.vhdl (nonexistent)
+++ rtl/quartus-synthesis/galois-lfsr.vhdl (revision 8)
@@ -0,0 +1,96 @@
+/*
+ This file is part of the Galois-type linear-feedback shift register
+ (galois_lfsr) project:
+ http://www.opencores.org/project,galois_lfsr
+
+ Description
+ Synthesisable use case for Galois LFSR.
+ This example is a CRC generator that uses a Galois LFSR.
+ Example applications include:
+ * serial or parallel PRBS generation.
+ * CRC computation.
+ * digital scramblers/descramblers.
+
+ ToDo:
+
+ Author(s):
+ - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
+
+ Copyright (C) 2012-2013 Authors and OPENCORES.ORG
+
+ This source file may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ This source file is free software; you can redistribute it
+ and/or modify it under the terms of the GNU Lesser General
+ Public License as published by the Free Software Foundation;
+ either version 2.1 of the License, or (at your option) any
+ later version.
+
+ This source is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ PURPOSE. See the GNU Lesser General Public License for more
+ details.
+
+ You should have received a copy of the GNU Lesser General
+ Public License along with this source; if not, download it
+ from http://www.opencores.org/lgpl.shtml.
+*/
+library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
+/* Enable for synthesis; comment out for simulation.
+ For this design, we just need boolean_vector. This is already included in Questa/ModelSim,
+ but Quartus doesn't yet support this.
+*/
+use work.types.all;
+
+entity lfsr is generic(
+ /*
+ * Tap vector: a TRUE means that position is tapped, otherwise that position is untapped.
+ */
+ taps:boolean_vector
+ );
+
+ port(nReset,clk:in std_ulogic:='0';
+ load:in boolean;
+ seed:in unsigned(taps'high downto 0);
+
+ d:in std_ulogic;
+ q:out unsigned(taps'high downto 0)
+ );
+end entity lfsr;
+
+architecture rtl of lfsr is
+ signal i_d,i_q:unsigned(taps'high downto 0);
+ signal x:unsigned(taps'high-1 downto 0);
+
+begin
+-- /* [begin]: Simulation testbench stimuli. Do not remove.
+-- TODO migrate to separate testbench when more testcases are developed.
+-- */
+-- /* synthesis translate_off */
+-- clk<=not clk after 1 ns;
+-- /* synthesis translate_on */
+-- /* [end]: simulation stimuli. */
+
+
+ /* Receives a vector of taps; generates LFSR structure with correct XOR positionings. */
+ tapGenr: for i in 0 to taps'high-1 generate
+ i_d(i+1)<=x(i) when taps(i) else i_q(i);
+ x(i)<=i_q(i) xor i_q(taps'high);
+ end generate;
+
+ process(nReset,load,seed,clk) is begin
+ if nReset='0' then i_q<=(others=>'0');
+ elsif load then i_q<=seed;
+ elsif rising_edge(clk) then
+ i_q<=i_d;
+ end if;
+ end process;
+
+ i_d(0)<=d;
+ q<=i_d;
+
+end architecture rtl;
rtl/quartus-synthesis/galois-lfsr.vhdl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/galois-lfsr.vhdl
===================================================================
--- rtl/galois-lfsr.vhdl (revision 7)
+++ rtl/galois-lfsr.vhdl (revision 8)
@@ -1,5 +1,5 @@
/*
- This file is part of the Galois Linear Feedback Shift Register
+ This file is part of the Galois-type linear-feedback shift register
(galois_lfsr) project:
http://www.opencores.org/project,galois_lfsr
@@ -44,7 +44,7 @@
For this design, we just need boolean_vector. This is already included in Questa/ModelSim,
but Quartus doesn't yet support this.
*/
-use work.types.all;
+--use work.types.all;
entity lfsr is generic(
/*
/workspace/quartus/galois.qpf
0,0 → 1,30
# -------------------------------------------------------------------------- # |
# |
# Copyright (C) 1991-2012 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
# |
# -------------------------------------------------------------------------- # |
# |
# Quartus II 32-bit |
# Version 12.1 Build 177 11/07/2012 SJ Full Version |
# Date created = 12:05:08 March 04, 2014 |
# |
# -------------------------------------------------------------------------- # |
|
QUARTUS_VERSION = "12.1" |
DATE = "12:05:08 March 04, 2014" |
|
# Revisions |
|
PROJECT_REVISION = "galois" |
workspace/quartus/galois.qpf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: workspace/quartus/galois.qsf
===================================================================
--- workspace/quartus/galois.qsf (nonexistent)
+++ workspace/quartus/galois.qsf (revision 8)
@@ -0,0 +1,58 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 12.1 Build 177 11/07/2012 SJ Full Version
+# Date created = 23:35:01 July 30, 2013
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# ethernet_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV GX"
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name TOP_LEVEL_ENTITY user
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:01 JULY 30, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION 12.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 169
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VHDL_FILE "../../rtl/packages/pkg-types.vhdl"
+set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/galois-lfsr.vhdl"
+set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/user.vhdl"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
workspace/quartus/galois.qsf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property