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/gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_prototype.ise Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple.ise Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_fsm.vhd
0,0 → 1,539
-- GECKO3COM IP Core
--
-- Copyright (C) 2009 by
-- ___ ___ _ _
-- ( _ \ ( __)( ) ( )
-- | (_) )| ( | |_| | Bern University of Applied Sciences
-- | _ < | _) | _ | School of Engineering and
-- | (_) )| | | | | | Information Technology
-- (____/ (_) (_) (_)
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- URL to the project description:
-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
--------------------------------------------------------------------------------
--
-- Author: Christoph Zimmermann
-- Date of creation: 3 february 2010
-- Description:
-- This is the finite-state-mashine for the GECKO3com simple IP core.
--
-- This core provides a simple FIFO and register interface to the
-- USB data transfer capabilities of the GECKO3COM/GECKO3main system.
--
-- Look at GECKO3COM_loopback.vhd for an example how to use it.
--
-- Target Devices: general
-- Tool versions: 11.1
--
--------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
library work;
use work.GECKO3COM_defines.all;
 
 
entity GECKO3COM_simple_fsm is
 
port (
i_nReset : in std_logic;
i_sysclk : in std_logic;
o_receive_fifo_wr_en : out std_logic;
i_receive_fifo_full : in std_logic;
o_receive_fifo_reset : out std_logic;
o_receive_transfersize_en : out std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
o_receive_counter_load : out std_logic;
o_receive_counter_en : out std_logic;
i_receive_counter_zero : in std_logic;
i_dev_dep_msg_out : in std_logic;
i_request_dev_dep_msg_in : in std_logic;
o_btag_reg_en : out std_logic;
o_nbtag_reg_en : out std_logic;
i_btag_correct : in std_logic;
i_eom_bit_detected : in std_logic;
i_send_transfersize_en : in std_logic;
o_send_fifo_rd_en : out std_logic;
i_send_fifo_empty : in std_logic;
o_send_fifo_reset : out std_logic;
o_send_counter_load : out std_logic;
o_send_counter_en : out std_logic;
i_send_counter_zero : in std_logic;
o_send_mux_sel : out std_logic_vector(2 downto 0);
o_send_finished : out std_logic;
o_receive_newdata_set : out std_logic;
o_receive_end_of_message_set : out std_logic;
o_send_data_request_set : out std_logic;
i_gpif_rx : in std_logic;
i_gpif_rx_empty : in std_logic;
o_gpif_rx_rd_en : out std_logic;
i_gpif_tx : in std_logic;
i_gpif_tx_full : in std_logic;
o_gpif_tx_wr_en : out std_logic;
i_gpif_abort : in std_logic;
o_gpif_eom : out std_logic);
 
end GECKO3COM_simple_fsm;
 
 
architecture fsm of GECKO3COM_simple_fsm is
 
-- XST specific synthesize attributes
attribute safe_implementation : string;
attribute safe_recovery_state : string;
 
type state_type is (st1_idle, st2_abort, st3_read_msg_id, st4_read_nbtag,
st5_check_btag, st6_read_transfer_size_low,
st7_read_transfer_size_high, st8_check_attributes,
st9_signal_data_request, st10_signal_receive_new_data,
st11_receive_data, st12_receive_wait,
st13_wait_for_receive_end, st14_read_align_bytes,
st15_start_response, st16_send_msg_id,
st17_send_nbtag, st18_send_transfer_size_low,
st19_send_transfer_size_high, st20_send_attributes,
st21_load_counter, st22_send_data, st23_send_wait,
st24_wait_for_send_end);
signal state, next_state : state_type;
 
-- XST specific synthesize attributes
attribute safe_recovery_state of state : signal is "st1_idle";
attribute safe_implementation of state : signal is "yes";
 
--Declare internal signals for all outputs of the state-machine
signal s_receive_fifo_wr_en : std_logic;
signal s_receive_fifo_reset : std_logic;
signal s_receive_transfersize_en : std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
signal s_receive_counter_load : std_logic;
signal s_receive_counter_en : std_logic;
signal s_btag_reg_en : std_logic;
signal s_nbtag_reg_en : std_logic;
signal s_send_fifo_rd_en : std_logic;
signal s_send_fifo_reset : std_logic;
signal s_send_counter_load : std_logic;
signal s_send_counter_en : std_logic;
signal s_send_counter_zero : std_logic;
signal s_send_mux_sel : std_logic_vector(2 downto 0);
signal s_send_finished : std_logic;
signal s_receive_newdata_set : std_logic;
signal s_receive_end_of_message_set : std_logic;
signal s_send_data_request_set : std_logic;
signal s_gpif_eom : std_logic;
signal s_gpif_rx_rd_en : std_logic;
signal s_gpif_tx_wr_en : std_logic;
 
begin -- fsm
SYNC_PROC : process (i_sysclk)
begin
if (i_sysclk'event and i_sysclk = '1') then
if (i_nReset = '0') then
state <= st1_idle;
 
o_receive_fifo_wr_en <= '0';
o_receive_fifo_reset <= '1';
o_receive_transfersize_en <= (others => '0');
o_receive_counter_load <= '0';
o_receive_counter_en <= '0';
o_btag_reg_en <= '0';
o_nbtag_reg_en <= '0';
o_send_fifo_rd_en <= '0';
o_send_fifo_reset <= '1';
o_send_counter_load <= '0';
o_send_counter_en <= '0';
o_send_mux_sel <= (others => '0');
o_send_finished <= '0';
o_receive_newdata_set <= '0';
o_receive_end_of_message_set <= '0';
o_send_data_request_set <= '0';
o_gpif_eom <= '0';
o_gpif_rx_rd_en <= '0';
o_gpif_tx_wr_en <= '0';
else
state <= next_state;
 
o_receive_fifo_wr_en <= s_receive_fifo_wr_en;
o_receive_fifo_reset <= s_receive_fifo_reset;
o_receive_transfersize_en <= s_receive_transfersize_en;
o_receive_counter_load <= s_receive_counter_load;
o_receive_counter_en <= s_receive_counter_en;
o_btag_reg_en <= s_btag_reg_en;
o_nbtag_reg_en <= s_nbtag_reg_en;
o_send_fifo_rd_en <= s_send_fifo_rd_en;
o_send_fifo_reset <= s_send_fifo_reset;
o_send_counter_load <= s_send_counter_load;
o_send_counter_en <= s_send_counter_en;
o_send_mux_sel <= s_send_mux_sel;
o_send_finished <= s_send_finished;
o_receive_newdata_set <= s_receive_newdata_set;
o_receive_end_of_message_set <= s_receive_end_of_message_set;
o_send_data_request_set <= s_send_data_request_set;
o_gpif_eom <= s_gpif_eom;
o_gpif_rx_rd_en <= s_gpif_rx_rd_en;
o_gpif_tx_wr_en <= s_gpif_tx_wr_en;
end if;
end if;
end process;
 
--MEALY State-Machine - Outputs based on state and inputs
OUTPUT_DECODE : process (state, i_receive_fifo_full,
i_receive_counter_zero, i_dev_dep_msg_out,
i_request_dev_dep_msg_in, i_btag_correct,
i_eom_bit_detected, i_send_transfersize_en,
i_send_fifo_empty, i_send_counter_zero,
i_gpif_rx, i_gpif_rx_empty, i_gpif_tx,
i_gpif_tx_full, i_gpif_abort)
begin
 
s_receive_fifo_wr_en <= '0';
s_receive_fifo_reset <= '0';
s_receive_transfersize_en <= (others => '0');
s_receive_counter_load <= '0';
s_receive_counter_en <= '0';
s_btag_reg_en <= '0';
s_nbtag_reg_en <= '0';
s_send_fifo_rd_en <= '0';
s_send_fifo_reset <= '0';
s_send_counter_load <= '0';
s_send_counter_en <= '0';
s_send_mux_sel <= (others => '0');
s_receive_newdata_set <= '0';
s_receive_end_of_message_set <= '0';
s_send_data_request_set <= '0';
s_gpif_eom <= '0';
s_gpif_rx_rd_en <= '0';
s_gpif_tx_wr_en <= '0';
 
if state = st11_receive_data then
s_receive_fifo_wr_en <= '1';
end if;
 
if state = st2_abort then
s_receive_fifo_reset <= '1';
end if;
 
if state = st6_read_transfer_size_low then
s_receive_transfersize_en <= "01";
elsif state = st7_read_transfer_size_high then
s_receive_transfersize_en <= "10";
end if;
 
if state = st10_signal_receive_new_data then
s_receive_counter_load <= '1';
end if;
 
if (state = st10_signal_receive_new_data and
i_gpif_rx_empty = '0' and
i_receive_fifo_full = '0')
or (state = st11_receive_data)
or (state = st12_receive_wait and
i_gpif_rx_empty = '0' and
i_receive_fifo_full = '1')
then
s_receive_counter_en <= '1';
end if;
 
if state = st3_read_msg_id then
s_btag_reg_en <= '1';
end if;
if state = st4_read_nbtag then
s_nbtag_reg_en <= '1';
end if;
 
if (state = st21_load_counter and
i_gpif_tx_full = '0' and
i_send_fifo_empty = '0')
or state = st22_send_data
or (state = st23_send_wait and
i_gpif_tx_full = '0' and
i_send_fifo_empty = '0')
then
s_send_fifo_rd_en <= '1';
end if;
 
if state = st2_abort then
s_send_fifo_reset <= '1';
end if;
 
if state = st21_load_counter then
s_send_counter_load <= '1';
end if;
 
if (state = st21_load_counter and i_gpif_tx_full = '0' and
i_send_fifo_empty = '0') or
state = st22_send_data or
(state = st23_send_wait and i_gpif_tx_full = '0' and
i_send_fifo_empty = '0')
then
s_send_counter_en <= '1';
end if;
if state = st16_send_msg_id then
s_send_mux_sel <= "000";
elsif state = st17_send_nbtag then
s_send_mux_sel <= "001";
elsif state =st18_send_transfer_size_low then
s_send_mux_sel <= "010";
elsif state = st19_send_transfer_size_high then
s_send_mux_sel <= "011";
elsif state = st20_send_attributes then
s_send_mux_sel <= "100";
elsif state = st21_load_counter then
s_send_mux_sel <= "101";
end if;
 
if state = st24_wait_for_send_end and i_gpif_tx = '0' then
s_send_finished <= '0';
end if;
if state = st10_signal_receive_new_data then
s_receive_newdata_set <= '1';
end if;
 
if state = st8_check_attributes and i_eom_bit_detected = '1' then
s_receive_end_of_message_set <= '1';
end if;
if state = st9_signal_data_request then
s_send_data_request_set <= '1';
end if;
 
if state = st22_send_data and i_send_counter_zero = '1' then
s_gpif_eom <= '1';
end if;
if (i_gpif_rx_empty = '0' and
(state = st1_idle or
state = st3_read_msg_id or
state = st4_read_nbtag or
state = st5_check_btag or
state = st6_read_transfer_size_low or
state = st7_read_transfer_size_high or
state = st8_check_attributes))
or ((state = st10_signal_receive_new_data or state = st12_receive_wait)
and i_gpif_rx_empty = '0' and i_receive_fifo_full = '0')
or state = st11_receive_data
or (state = st14_read_align_bytes and i_gpif_rx_empty = '0')
then
s_gpif_rx_rd_en <= '1';
end if;
 
if (i_gpif_tx_full = '0' and
(state = st16_send_msg_id or
state = st17_send_nbtag or
state = st18_send_transfer_size_low or
state = st19_send_transfer_size_high or
state = st20_send_attributes or
state = st21_load_counter))
or state = st22_send_data
then
s_gpif_tx_wr_en <= '1';
end if;
end process;
 
NEXT_STATE_DECODE : process (state, i_receive_fifo_full,
i_receive_counter_zero, i_dev_dep_msg_out,
i_request_dev_dep_msg_in, i_btag_correct,
i_eom_bit_detected, i_send_transfersize_en,
i_send_fifo_empty, i_send_counter_zero,
i_gpif_rx, i_gpif_rx_empty, i_gpif_tx,
i_gpif_tx_full, i_gpif_abort)
begin
--declare default state for next_state to avoid latches
next_state <= state; --default is to stay in current state
 
case (state) is
when st1_idle =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_rx_empty = '0' then
next_state <= st3_read_msg_id;
end if;
when st2_abort =>
next_state <= st1_idle;
when st3_read_msg_id =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_rx_empty = '0' then
next_state <= st4_read_nbtag;
end if;
when st4_read_nbtag =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_rx_empty = '0' then
next_state <= st5_check_btag;
end if;
 
when st5_check_btag =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_btag_correct = '0' then
next_state <= st1_idle;
elsif i_gpif_rx_empty = '0' then
next_state <= st6_read_transfer_size_low;
end if;
 
when st6_read_transfer_size_low =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_rx_empty = '0' then
next_state <= st7_read_transfer_size_high;
end if;
 
when st7_read_transfer_size_high =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_rx_empty = '0' then
next_state <= st8_check_attributes;
end if;
 
when st8_check_attributes =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_rx_empty = '0' and i_request_dev_dep_msg_in = '1' then
next_state <= st9_signal_data_request;
elsif i_gpif_rx_empty = '0' and i_dev_dep_msg_out = '1' then
next_state <= st10_signal_receive_new_data;
end if;
 
when st9_signal_data_request =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_send_transfersize_en = '1' then
next_state <= st15_start_response;
end if;
 
when st10_signal_receive_new_data =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_rx_empty = '0' and i_receive_fifo_full = '0' then
next_state <= st11_receive_data;
end if;
 
when st11_receive_data =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_receive_counter_zero = '1' then
next_state <= st13_wait_for_receive_end;
elsif i_gpif_rx_empty = '1' or i_receive_fifo_full = '1' then
next_state <= st12_receive_wait;
end if;
 
when st12_receive_wait =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_rx_empty = '0' and i_receive_fifo_full = '0' then
next_state <= st11_receive_data;
end if;
 
when st13_wait_for_receive_end =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_rx = '0' then
next_state <= st14_read_align_bytes;
end if;
 
when st14_read_align_bytes =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_rx_empty = '1' then
next_state <= st1_idle;
end if;
 
when st15_start_response =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_tx_full = '0' then
next_state <= st16_send_msg_id;
end if;
 
when st16_send_msg_id =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_tx_full = '0' then
next_state <= st17_send_nbtag;
end if;
 
when st17_send_nbtag =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_tx_full = '0' then
next_state <= st18_send_transfer_size_low;
end if;
 
when st18_send_transfer_size_low =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_tx_full = '0' then
next_state <= st19_send_transfer_size_high;
end if;
 
when st19_send_transfer_size_high =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_tx_full = '0' then
next_state <= st20_send_attributes;
end if;
 
when st20_send_attributes =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_tx_full = '0' then
next_state <= st21_load_counter;
end if;
 
when st21_load_counter =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_tx_full = '0' and i_send_fifo_empty = '0' then
next_state <= st22_send_data;
end if;
 
when st22_send_data =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_send_counter_zero = '1' then
next_state <= st24_wait_for_send_end;
elsif i_gpif_tx_full = '1' or i_send_fifo_empty = '1' then
next_state <= st23_send_wait;
end if;
 
when st23_send_wait =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_tx_full = '0' and i_send_fifo_empty = '0' then
next_state <= st22_send_data;
end if;
 
when st24_wait_for_send_end =>
if i_gpif_abort = '1' then
next_state <= st2_abort;
elsif i_gpif_tx = '0' then
next_state <= st1_idle;
end if;
when others =>
next_state <= st1_idle;
end case;
end process;
 
end fsm;
/gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_datapath.vhd
0,0 → 1,365
-- GECKO3COM IP Core
--
-- Copyright (C) 2009 by
-- ___ ___ _ _
-- ( _ \ ( __)( ) ( )
-- | (_) )| ( | |_| | Bern University of Applied Sciences
-- | _ < | _) | _ | School of Engineering and
-- | (_) )| | | | | | Information Technology
-- (____/ (_) (_) (_)
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- URL to the project description:
-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
--------------------------------------------------------------------------------
--
-- Author: Christoph Zimmermann
-- Date of creation: 16:52:52 01/28/2010
-- Description:
-- This is the top module for the GECKO3com simple IP core.
-- Not the one for Xilinx EDK (with PLB bus), for processor less designs.
--
-- This core provides a simple FIFO and register interface to the
-- USB data transfer capabilities of the GECKO3COM/GECKO3main system.
--
-- Look at GECKO3COM_loopback.vhd for an example how to use it.
--
-- Target Devices: general
-- Tool versions: 11.1
-- Dependencies: Xilinx FPGA's Spartan3 and up or Virtex4 and up.
--
--------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
library work;
use work.GECKO3COM_defines.all;
 
 
entity GECKO3COM_simple_datapath is
 
generic (
BUSWIDTH : integer := 16);
 
port (
i_nReset : in std_logic;
i_sysclk : in std_logic;
i_rx_data : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
o_tx_data : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
 
i_receive_fifo_rd_en : in std_logic;
i_receive_fifo_wr_en : in std_logic;
o_receive_fifo_empty : out std_logic;
o_receive_fifo_full : out std_logic;
o_receive_fifo_data : out std_logic_vector(BUSWIDTH-1 downto 0);
i_receive_fifo_reset : in std_logic;
o_receive_transfersize : out std_logic_vector(31 downto 0);
i_receive_transfersize_en : in std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
i_receive_counter_load : in std_logic;
i_receive_counter_en : in std_logic;
o_receive_counter_zero : out std_logic;
o_dev_dep_msg_out : out std_logic;
o_request_dev_dep_msg_in : out std_logic;
i_btag_reg_en : in std_logic;
i_nbtag_reg_en : in std_logic;
o_btag_correct : out std_logic;
o_eom_bit_detected : out std_logic;
 
i_send_fifo_rd_en : in std_logic;
i_send_fifo_wr_en : in std_logic;
o_send_fifo_empty : out std_logic;
o_send_fifo_full : out std_logic;
i_send_fifo_data : in std_logic_vector(BUSWIDTH-1 downto 0);
i_send_fifo_reset : in std_logic;
i_send_transfersize : in std_logic_vector(31 downto 0);
i_send_transfersize_en : in std_logic;
i_send_counter_load : in std_logic;
i_send_counter_en : in std_logic;
o_send_counter_zero : out std_logic;
i_send_mux_sel : in std_logic_vector(2 downto 0);
 
i_receive_newdata_set : in std_logic;
o_receive_newdata : out std_logic;
i_receive_end_of_message_set : in std_logic;
o_receive_end_of_message : out std_logic;
i_send_data_request_set : in std_logic;
o_send_data_request : out std_logic);
 
end GECKO3COM_simple_datapath;
 
architecture behaviour of GECKO3COM_simple_datapath is
 
-----------------------------------------------------------------------------
-- COMPONENTS
-----------------------------------------------------------------------------
 
component receive_fifo
generic (
BUSWIDTH : integer);
port (
i_din : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
i_clk : in std_logic;
i_rd_en : in std_logic;
i_rst : in std_logic;
i_wr_en : in std_logic;
o_dout : out std_logic_vector(BUSWIDTH-1 downto 0);
o_empty : out std_logic;
o_full : out std_logic);
end component;
 
component send_fifo
generic (
BUSWIDTH : integer);
port (
i_din : in std_logic_vector(BUSWIDTH-1 downto 0);
i_clk : in std_logic;
i_rd_en : in std_logic;
i_rst : in std_logic;
i_wr_en : in std_logic;
o_dout : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
o_empty : out std_logic;
o_full : out std_logic);
end component;
 
 
-----------------------------------------------------------------------------
-- interconection signals
-----------------------------------------------------------------------------
 
signal s_receive_transfersize : std_logic_vector(31 downto 0);
signal s_send_transfersize_reg: std_logic_vector(31 downto 0);
 
signal s_receive_transfersize_count: std_logic_vector(31 downto 0);
signal s_send_transfersize_count: std_logic_vector(31 downto 0);
 
signal s_receive_fifo_empty : std_logic;
 
signal s_send_fifo_data : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
signal s_btag, s_nbtag : std_logic_vector(7 downto 0);
 
begin -- behaviour
 
receive_fifo_1 : receive_fifo
generic map (
BUSWIDTH => BUSWIDTH)
port map (
i_din => i_rx_data,
i_clk => i_sysclk,
i_rd_en => i_receive_fifo_rd_en,
i_rst => i_nReset,
i_wr_en => i_receive_fifo_wr_en,
o_dout => o_receive_fifo_data,
o_empty => s_receive_fifo_empty,
o_full => o_receive_fifo_full);
 
send_fifo_1 : send_fifo
generic map (
BUSWIDTH => BUSWIDTH)
port map (
i_din => i_send_fifo_data,
i_clk => i_sysclk,
i_rd_en => i_send_fifo_rd_en,
i_rst => i_nReset,
i_wr_en => i_send_fifo_wr_en,
o_dout => s_send_fifo_data,
o_empty => o_send_fifo_empty,
o_full => o_send_fifo_full);
 
 
o_receive_fifo_empty <= s_receive_fifo_empty;
 
-- purpose: process to fill the 32 bit receive_transfersize register with 8
-- or 16 bit wide input data.
-- type : sequential
-- inputs : i_sysclk, i_nReset, i_rx_data, i_receive_transfersize_en
receive_transfersize: process (i_sysclk, i_nReset)
begin -- process registers
if i_nReset = '0' then -- asynchronous reset (active low)
s_receive_transfersize <= (others => '0');
elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
if i_receive_transfersize_en(0) = '1' then
s_receive_transfersize(15 downto 0) <= i_rx_data;
end if;
if i_receive_transfersize_en(1) = '1' then
s_receive_transfersize(31 downto 16) <= i_rx_data;
end if;
end if;
end process receive_transfersize;
 
o_receive_transfersize <= s_receive_transfersize;
 
 
-- purpose: 32 bit send_transfersize register
-- type : sequential
-- inputs : i_sysclk, i_nReset, i_send_transfersize, i_receive_transfersize_en
send_transfersize: process (i_sysclk, i_nReset)
begin -- process registers
if i_nReset = '0' then -- asynchronous reset (active low)
s_send_transfersize_reg <= (others => '0');
elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
if i_send_transfersize_en = '1' then
s_send_transfersize_reg <= i_send_transfersize;
end if;
end if;
end process send_transfersize;
 
-- purpose: down counter for the receive transfer size
-- type : sequential
-- inputs : i_sysclk, i_nReset, s_reveive_transfersize,
-- i_receive_transfersize_en
-- outputs: s_receive_transfersize_count
receive_counter : process (i_sysclk, i_nReset)
begin -- process receive_counter
if i_nReset = '0' then -- asynchronous reset (active low)
s_receive_transfersize_count <= (others => '0');
elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
if i_receive_counter_load = '1' then
s_receive_transfersize_count <= s_receive_transfersize;
end if;
if i_receive_counter_en = '1' then
s_receive_transfersize_count <= s_receive_transfersize_count - 1;
end if;
end if;
end process receive_counter;
 
o_receive_counter_zero <=
'1' when s_receive_transfersize_count = x"0000" else
'0';
 
 
-- purpose: down counter for the send transfer size
-- type : sequential
-- inputs : i_sysclk, i_nReset, s_send_transfersize_reg,
-- i_send_transfersize_en
-- outputs: s_send_transfersize_count
send_counter : process (i_sysclk, i_nReset)
begin -- process receive_counter
if i_nReset = '0' then -- asynchronous reset (active low)
s_send_transfersize_count <= (others => '0');
elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
if i_send_counter_load = '1' then
s_receive_transfersize_count <= s_send_transfersize_reg;
end if;
if i_send_counter_en = '1' then
s_send_transfersize_count <= s_send_transfersize_count - 1;
end if;
end if;
end process send_counter;
 
o_send_counter_zero <=
'1' when s_send_transfersize_count = x"0000" else
'0';
 
 
-- purpose: registers to store the btag and inverse btag
-- type : sequential
-- inputs : i_sysclk, i_nReset, i_btag_reg_en, i_nbtag_reg_en
-- i_rx_data
-- outputs: s_btag, s_nbtag
btag_register : process (i_sysclk, i_nReset)
begin -- process receive_counter
if i_nReset = '0' then -- asynchronous reset (active low)
s_btag <= (others => '0');
s_nbtag <= (others => '0');
elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
if i_btag_reg_en = '1' then
s_btag <= i_rx_data(15 downto 8);
end if;
if i_nbtag_reg_en = '1' then
s_nbtag <= i_rx_data(7 downto 0);
end if;
end if;
end process btag_register;
o_btag_correct <=
'1' when s_btag = not s_nbtag else
'0';
 
o_dev_dep_msg_out <=
'1' when i_rx_data(7 downto 0) = x"01" else
'0';
 
o_request_dev_dep_msg_in <=
'1' when i_rx_data(7 downto 0) = x"02" else
'0';
 
o_eom_bit_detected <=
'1' when i_rx_data(15 downto 8) = b"00000001" else
'0';
 
 
-- purpose: mulitiplexer to construct the tmc header structure
-- type : combinational
-- inputs : i_send_mux_sel, s_btag, s_nbtag, s_send_fifo_data,
-- s_send_transfersize_reg
-- outputs: o_tx_data
tx_data_mux: process (i_send_mux_sel, s_btag, s_nbtag, s_send_fifo_data,
s_send_transfersize_reg)
begin -- process tx_data_mux
case i_send_mux_sel is
when "000" => o_tx_data <= x"02" & s_btag; -- MsgID and stored bTag
when "001" => o_tx_data <= s_nbtag & x"00"; -- inverted bTag and Reserved
when "010" => o_tx_data <= s_send_transfersize_reg(15 downto 0);
when "011" => o_tx_data <= s_send_transfersize_reg(31 downto 16);
when "100" => o_tx_data <= x"0001"; -- TransferAttributes: EOM = 1
when "101" => o_tx_data <= x"0000"; -- Header byte 10 and 11, Reserved
when "110" => o_tx_data <= s_send_fifo_data; -- message data
when others => o_tx_data <= s_send_fifo_data;
end case;
end process tx_data_mux;
 
-- purpose: set and reset behavour for the status flags
-- type : sequential
-- inputs : i_sysclk, i_nReset, i_receive_newdata_set,
-- i_receive_end_of_message_set, s_send_data_request_set,
-- i_receive_fifo_rd_en, s_receive_fifo_empty, i_send_fifo_wr_en
-- outputs: o_receive_newdata, o_receive_end_of_message, o_send_data_request
gecko3com_simple_flags: process (i_sysclk, i_nReset)
begin -- process gecko3com_simple_flags
if i_nReset = '0' then -- asynchronous reset (active low)
o_receive_newdata <= '0';
o_receive_end_of_message <= '0';
o_send_data_request <= '0';
elsif i_sysclk'event and i_sysclk = '1' then -- rising clock edge
if i_receive_newdata_set = '1' then
o_receive_newdata <= '1';
end if;
if i_receive_fifo_rd_en = '1' then
o_receive_newdata <= '0';
end if;
 
if i_receive_end_of_message_set = '1' then
o_receive_end_of_message <= '1';
end if;
if s_receive_fifo_empty = '1' then
o_receive_end_of_message <= '0';
end if;
 
if i_send_data_request_set = '1' then
o_send_data_request <= '1';
end if;
if i_send_fifo_wr_en = '1' then
o_send_data_request <= '0';
end if;
end if;
end process gecko3com_simple_flags;
 
end behaviour;
/gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_prototype.xise
22,10 → 22,7
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator_fifo_dualclock.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator/coregenerator_fifo_dualclock.xco" xil_pn:type="FILE_COREGEN"/>
<file xil_pn:name="fifo_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
58,9 → 55,41
<file xil_pn:name="gecko3com_test_chipscope.cdc" xil_pn:type="FILE_CDC">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator_fifo_dualclock.ise" xil_pn:type="FILE_COREGENISE">
<file xil_pn:name="GECKO3COM_simple.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator/coregenerator_fifo_receive.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator/coregenerator_fifo_send.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="fifo_receive.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="fifo_send.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="GECKO3COM_simple_datapath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="GECKO3COM_simple_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator/coregenerator_fifo_dualclock.ise" xil_pn:type="FILE_COREGENISE"/>
<file xil_pn:name="coregenerator/coregenerator_fifo_receive.ise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator/coregenerator_fifo_send.ise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
</files>
 
<properties>
72,6 → 101,7
<property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
<property xil_pn:name="Editor" xil_pn:value="Custom"/>
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|gpif_com_test|loopback"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/gpif_com_test"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="Soft"/>
/gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM.ipf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/gecko3/trunk/GECKO3COM/gecko3com-ip/core/gpif_com.vhd
84,7 → 84,7
signal s_ABORT_FSM, s_ABORT_TMP : std_logic;
signal s_RX_FSM, s_RX_TMP : std_logic;
signal s_TX_FSM, s_TX_TMP : std_logic;
signal s_EOM, s_EOM_TMP : std_logic; -- End of message
signal s_EOM, s_EOM_TMP, s_EOM_FF : std_logic; -- End of message
signal s_X2U_FULL_IFCLK, s_X2U_FULL_TMP : std_logic;
-- USB to Xilinx (U2X)
203,7 → 203,7
i_IFCLK => i_IFCLK,
i_WRU => i_WRU,
i_RDYU => i_RDYU,
i_EOM => s_EOM,
i_EOM => s_EOM_FF,
i_U2X_FULL => s_U2X_FULL,
i_U2X_AM_FULL => s_U2X_AM_FULL,
i_X2U_FULL_IFCLK => s_X2U_FULL_IFCLK,
253,7 → 253,7
end if;
end process double_buf_sig;
 
-- Double buffer the ABORT, RX and TX signal to avoid metastability
-- Double buffer the s_EOM and s_X2U_FULL_IFCLK signal to avoid metastability
double_buf_ifclk : process (i_IFCLK, i_nReset)
begin
if i_nReset = '0' then
267,15 → 267,32
end if;
end process double_buf_ifclk;
 
-- purpose: EOM bit flip-flop
-- type : sequential
-- inputs : i_IFCLK, i_nReset, s_EOM, s_X2U_EMPTY
-- outputs: s_EOM_FF
EOM_FF: process (i_IFCLK, i_nReset)
begin -- process EOM_FF
if i_nReset = '0' then -- asynchronous reset (active low)
s_EOM_FF <= '0';
elsif i_IFCLK'event and i_IFCLK = '1' then -- rising clock edge
if s_EOM = '1' then
s_EOM_FF <= '1';
end if;
if s_X2U_EMPTY = '1' then
s_EOM_FF <= '0';
end if;
end if;
end process EOM_FF;
-----------------------------------------------------------------------------
-- Data bus access
-----------------------------------------------------------------------------
 
-----------------------------------------------------------------------------
-- Data bus access
-----------------------------------------------------------------------------
 
-- purpose: to handle the access on the bidirectional bus
-- type : combinational
-- inputs : s_bus_trans_dir
-- outputs:
-- purpose: to handle the access on the bidirectional bus
-- type : combinational
-- inputs : s_bus_trans_dir
-- outputs:
bus_access : process (s_dbus_trans_dir, s_dbus_out)
begin -- process bus_access
if s_dbus_trans_dir = '1' then
/gecko3/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple.vhd
0,0 → 1,355
-- GECKO3COM IP Core
--
-- Copyright (C) 2009 by
-- ___ ___ _ _
-- ( _ \ ( __)( ) ( )
-- | (_) )| ( | |_| | Bern University of Applied Sciences
-- | _ < | _) | _ | School of Engineering and
-- | (_) )| | | | | | Information Technology
-- (____/ (_) (_) (_)
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- URL to the project description:
-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
--------------------------------------------------------------------------------
--
-- Author: Christoph Zimmermann
-- Date of creation: 16:52:52 01/28/2010
-- Description:
-- This is the top module for the GECKO3com simple IP core.
-- Not the one for Xilinx EDK (with PLB bus), for processor less designs.
--
-- This core provides a simple FIFO and register interface to the
-- USB data transfer capabilities of the GECKO3COM/GECKO3main system.
--
-- Look at GECKO3COM_loopback.vhd for an example how to use it.
--
-- Target Devices: Xilinx FPGA's Spartan3 and up or Virtex4 and up.
-- Tool versions: 11.1
--
--------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
library work;
use work.GECKO3COM_defines.all;
 
 
entity GECKO3COM_simple is
generic (
BUSWIDTH : integer := 16); -- vector size of the FIFO databusses
port (
i_nReset : in std_logic;
i_sysclk : in std_logic; -- FPGA System CLK
 
i_receive_fifo_rd_en : in std_logic;
o_receive_fifo_empty : out std_logic;
o_receive_fifo_data : out std_logic_vector(BUSWIDTH-1 downto 0);
o_receive_transfersize : out std_logic_vector(31 downto 0);
o_receive_end_of_message : out std_logic;
o_receive_newdata : out std_logic;
 
i_send_fifo_wr_en : in std_logic;
o_send_fifo_full : out std_logic;
i_send_fifo_data : in std_logic_vector(BUSWIDTH-1 downto 0);
i_send_transfersize : in std_logic_vector(31 downto 0);
i_send_transfersize_en : in std_logic;
o_send_data_request : out std_logic;
o_send_finished : out std_logic;
 
o_rx : out std_logic; -- receiving data signalisation
o_tx : out std_logic; -- transmitting data signalisation
 
-- Interface signals to the EZ-USB FX2
i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock)
i_WRU : in std_logic; -- write from GPIF
i_RDYU : in std_logic; -- GPIF is ready
o_WRX : out std_logic; -- To write to GPIF
o_RDYX : out std_logic; -- IP Core is ready
b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0) -- bidirect data bus
);
end GECKO3COM_simple;
 
 
architecture Behavioral of GECKO3COM_simple is
 
-----------------------------------------------------------------------------
-- COMPONENTS
-----------------------------------------------------------------------------
 
component gpif_com
port (
i_nReset : in std_logic;
i_SYSCLK : in std_logic;
o_ABORT : out std_logic;
o_RX : out std_logic;
o_TX : out std_logic;
i_RD_EN : in std_logic;
o_EMPTY : out std_logic;
o_RX_DATA : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
i_EOM : in std_logic;
i_WR_EN : in std_logic;
o_FULL : out std_logic;
i_TX_DATA : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
i_IFCLK : in std_logic;
i_WRU : in std_logic;
i_RDYU : in std_logic;
o_WRX : out std_logic;
o_RDYX : out std_logic;
b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0));
end component;
 
component GECKO3COM_simple_datapath
generic (
BUSWIDTH : integer);
port (
i_nReset : in std_logic;
i_sysclk : in std_logic;
i_rx_data : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
o_tx_data : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
i_receive_fifo_rd_en : in std_logic;
i_receive_fifo_wr_en : in std_logic;
o_receive_fifo_empty : out std_logic;
o_receive_fifo_full : out std_logic;
o_receive_fifo_data : out std_logic_vector(BUSWIDTH-1 downto 0);
i_receive_fifo_reset : in std_logic;
o_receive_transfersize : out std_logic_vector(31 downto 0);
i_receive_transfersize_en : in std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
i_receive_counter_load : in std_logic;
i_receive_counter_en : in std_logic;
o_receive_counter_zero : out std_logic;
o_dev_dep_msg_out : out std_logic;
o_request_dev_dep_msg_in : out std_logic;
i_btag_reg_en : in std_logic;
i_nbtag_reg_en : in std_logic;
o_btag_correct : out std_logic;
o_eom_bit_detected : out std_logic;
i_send_fifo_rd_en : in std_logic;
i_send_fifo_wr_en : in std_logic;
o_send_fifo_empty : out std_logic;
o_send_fifo_full : out std_logic;
i_send_fifo_data : in std_logic_vector(BUSWIDTH-1 downto 0);
i_send_fifo_reset : in std_logic;
i_send_transfersize : in std_logic_vector(31 downto 0);
i_send_transfersize_en : in std_logic;
i_send_counter_load : in std_logic;
i_send_counter_en : in std_logic;
o_send_counter_zero : out std_logic;
i_send_mux_sel : in std_logic_vector(2 downto 0);
o_send_finished : out std_logic;
i_receive_newdata_set : in std_logic;
o_receive_newdata : out std_logic;
i_receive_end_of_message_set : in std_logic;
o_receive_end_of_message : out std_logic;
i_send_data_request_set : in std_logic;
o_send_data_request : out std_logic);
end component;
 
component GECKO3COM_simple_fsm
port (
i_nReset : in std_logic;
i_sysclk : in std_logic;
o_receive_fifo_wr_en : out std_logic;
i_receive_fifo_full : in std_logic;
o_receive_fifo_reset : out std_logic;
o_receive_transfersize_en : out std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
o_receive_counter_load : out std_logic;
o_receive_counter_en : out std_logic;
i_receive_counter_zero : in std_logic;
i_dev_dep_msg_out : in std_logic;
i_request_dev_dep_msg_in : in std_logic;
o_btag_reg_en : out std_logic;
o_nbtag_reg_en : out std_logic;
i_btag_correct : in std_logic;
i_eom_bit_detected : in std_logic;
i_send_transfersize_en : in std_logic;
o_send_fifo_rd_en : out std_logic;
i_send_fifo_empty : in std_logic;
o_send_fifo_reset : out std_logic;
o_send_counter_load : out std_logic;
o_send_counter_en : out std_logic;
i_send_counter_zero : in std_logic;
o_send_mux_sel : out std_logic_vector(2 downto 0);
o_receive_newdata_set : out std_logic;
o_receive_end_of_message_set : out std_logic;
o_send_data_request_set : out std_logic;
i_gpif_rx : in std_logic;
i_gpif_rx_empty : in std_logic;
o_gpif_rx_rd_en : out std_logic;
i_gpif_tx : in std_logic;
i_gpif_tx_full : in std_logic;
o_gpif_tx_wr_en : out std_logic;
i_gpif_abort : in std_logic;
o_gpif_eom : out std_logic);
end component;
 
-----------------------------------------------------------------------------
-- interconection signals
-----------------------------------------------------------------------------
 
-- gpif_com internal signals
signal s_gpif_abort : std_logic;
signal s_gpif_rx_rd_en : std_logic;
signal s_gpif_rx_empty : std_logic;
signal s_gpif_rx_data : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
signal s_gpif_rx : std_logic;
signal s_gpif_eom : std_logic;
signal s_gpif_tx_wr_en : std_logic;
signal s_gpif_tx_full : std_logic;
signal s_gpif_tx_data : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
signal s_gpif_tx : std_logic;
 
-- GECKO3COM_simple_datapath internal signals
signal s_receive_fifo_wr_en : std_logic;
signal s_receive_fifo_empty : std_logic;
signal s_receive_fifo_full : std_logic;
signal s_receive_fifo_reset : std_logic;
signal s_receive_transfersize_en : std_logic_vector((32/SIZE_DBUS_GPIF)-1 downto 0);
signal s_receive_counter_load : std_logic;
signal s_receive_counter_en : std_logic;
signal s_receive_counter_zero : std_logic;
signal s_dev_dep_msg_out : std_logic;
signal s_request_dev_dep_msg_in : std_logic;
signal s_btag_reg_en : std_logic;
signal s_nbtag_reg_en : std_logic;
signal s_btag_correct : std_logic;
signal s_eom_bit_detected : std_logic;
signal s_send_fifo_rd_en : std_logic;
signal s_send_fifo_empty : std_logic;
signal s_send_fifo_reset : std_logic;
signal s_send_counter_load : std_logic;
signal s_send_counter_en : std_logic;
signal s_send_counter_zero : std_logic;
signal s_send_mux_sel : std_logic_vector(2 downto 0);
 
signal s_receive_newdata_set : std_logic;
signal s_receive_end_of_message_set : std_logic;
signal s_send_data_request_set : std_logic;
begin -- behaviour
 
GPIF_INTERFACE: gpif_com
port map (
i_nReset => i_nReset,
i_SYSCLK => i_sysclk,
o_ABORT => s_gpif_abort,
o_RX => s_gpif_rx,
o_TX => s_gpif_tx,
i_RD_EN => s_gpif_rx_rd_en,
o_EMPTY => s_gpif_rx_empty,
o_RX_DATA => s_gpif_rx_data,
i_EOM => s_gpif_eom,
i_WR_EN => s_gpif_tx_wr_en,
o_FULL => s_gpif_tx_full,
i_TX_DATA => s_gpif_tx_data,
i_IFCLK => i_IFCLK,
i_WRU => i_WRU,
i_RDYU => i_RDYU,
o_WRX => o_WRX,
o_RDYX => o_RDYX,
b_gpif_bus => b_gpif_bus);
 
o_rx <= s_gpif_rx;
o_tx <= s_gpif_tx;
 
GECKO3COM_simple_datapath_1 : GECKO3COM_simple_datapath
generic map (
BUSWIDTH => BUSWIDTH)
port map (
i_nReset => i_nReset,
i_sysclk => i_sysclk,
i_rx_data => s_gpif_rx_data,
o_tx_data => s_gpif_tx_data,
i_receive_fifo_rd_en => i_receive_fifo_rd_en,
i_receive_fifo_wr_en => s_receive_fifo_wr_en,
o_receive_fifo_empty => s_receive_fifo_empty,
o_receive_fifo_full => s_receive_fifo_full,
o_receive_fifo_data => o_receive_fifo_data,
i_receive_fifo_reset => s_receive_fifo_reset,
o_receive_transfersize => o_receive_transfersize,
i_receive_transfersize_en => s_receive_transfersize_en,
i_receive_counter_load => s_receive_counter_load,
i_receive_counter_en => s_receive_counter_en,
o_receive_counter_zero => s_receive_counter_zero,
o_dev_dep_msg_out => s_dev_dep_msg_out,
o_request_dev_dep_msg_in => s_request_dev_dep_msg_in,
i_btag_reg_en => s_btag_reg_en,
i_nbtag_reg_en => s_nbtag_reg_en,
o_btag_correct => s_btag_correct,
o_eom_bit_detected => s_eom_bit_detected,
i_send_fifo_rd_en => s_send_fifo_rd_en,
i_send_fifo_wr_en => i_send_fifo_wr_en,
o_send_fifo_empty => s_send_fifo_empty,
o_send_fifo_full => o_send_fifo_full,
i_send_fifo_data => i_send_fifo_data,
i_send_fifo_reset => s_send_fifo_reset,
i_send_transfersize => i_send_transfersize,
i_send_transfersize_en => i_send_transfersize_en,
i_send_counter_load => s_send_counter_load,
i_send_counter_en => s_send_counter_en,
o_send_counter_zero => s_send_counter_zero,
i_send_mux_sel => s_send_mux_sel,
i_receive_newdata_set => s_receive_newdata_set,
o_receive_newdata => o_receive_newdata,
i_receive_end_of_message_set => s_receive_end_of_message_set,
o_receive_end_of_message => o_receive_end_of_message,
i_send_data_request_set => s_send_data_request_set,
o_send_data_request => o_send_data_request);
 
o_receive_fifo_empty <= s_receive_fifo_empty;
 
GECKO3COM_simple_fsm_1: GECKO3COM_simple_fsm
port map (
i_nReset => i_nReset,
i_sysclk => i_sysclk,
o_receive_fifo_wr_en => s_receive_fifo_wr_en,
i_receive_fifo_full => s_receive_fifo_full,
o_receive_fifo_reset => s_receive_fifo_reset,
o_receive_transfersize_en => s_receive_transfersize_en,
o_receive_counter_load => s_receive_counter_load,
o_receive_counter_en => s_receive_counter_en,
i_receive_counter_zero => s_receive_counter_zero,
i_dev_dep_msg_out => s_dev_dep_msg_out,
i_request_dev_dep_msg_in => s_request_dev_dep_msg_in,
o_btag_reg_en => s_btag_reg_en,
o_nbtag_reg_en => s_nbtag_reg_en,
i_btag_correct => s_btag_correct,
i_eom_bit_detected => s_eom_bit_detected,
i_send_transfersize_en => i_send_transfersize_en,
o_send_fifo_rd_en => s_send_fifo_rd_en,
i_send_fifo_empty => s_send_fifo_empty,
o_send_fifo_reset => s_send_fifo_reset,
o_send_counter_load => s_send_counter_load,
o_send_counter_en => s_send_counter_en,
i_send_counter_zero => s_send_counter_zero,
o_send_mux_sel => s_send_mux_sel,
o_receive_newdata_set => s_receive_newdata_set,
o_receive_end_of_message_set => s_receive_end_of_message_set,
o_send_data_request_set => s_send_data_request_set,
i_gpif_rx => s_gpif_rx,
i_gpif_rx_empty => s_gpif_rx_empty,
o_gpif_rx_rd_en => s_gpif_rx_rd_en,
i_gpif_tx => s_gpif_tx,
i_gpif_tx_full => s_gpif_tx_full,
o_gpif_tx_wr_en => s_gpif_tx_wr_en,
i_gpif_abort => s_gpif_abort,
o_gpif_eom => s_gpif_eom);
end Behavioral;
 
/gecko3/trunk/GECKO3COM/gecko3com-ip/core/fifo_receive.vhd
0,0 → 1,108
-- GECKO3COM IP Core
--
-- Copyright (C) 2009 by
-- ___ ___ _ _
-- ( _ \ ( __)( ) ( )
-- | (_) )| ( | |_| | Bern University of Applied Sciences
-- | _ < | _) | _ | School of Engineering and
-- | (_) )| | | | | | Information Technology
-- (____/ (_) (_) (_)
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- URL to the project description:
-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
----------------------------------------------------------------------------------
--
-- Author: Christoph Zimmermann
-- Date of creation: 17. December 2009
-- Description:
-- This is a wrapper for a FIFO that was generated with the Xilinx Coregenerator
-- to hide the vendor specific stuff and match our naming conventions.
--
-- Target Devices: Xilinx FPGA's due to use of Coregenerator IP cores
-- Tool versions: 11.1
-- Dependencies:
--
----------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library UNISIM;
use UNISIM.vcomponents.all;
 
library UNIMACRO;
use UNIMACRO.vcomponents.all;
 
library work;
use work.GECKO3COM_defines.all;
 
entity receive_fifo is
generic (
BUSWIDTH : integer := 16); -- vector size of the FIFO databusses
port (
i_din : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
i_clk : in std_logic;
i_rd_en : in std_logic;
i_rst : in std_logic;
i_wr_en : in std_logic;
o_dout : out std_logic_vector(BUSWIDTH-1 downto 0);
o_empty : out std_logic;
o_full : out std_logic);
end receive_fifo;
 
architecture wrapper of receive_fifo is
 
-----------------------------------------------------------------------------
-- COMPONENTS
-----------------------------------------------------------------------------
 
component coregenerator_fifo_receive
port (
din : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
rd_clk : in std_logic;
rd_en : in std_logic;
rst : in std_logic;
wr_clk : in std_logic;
wr_en : in std_logic;
dout : out std_logic_vector(BUSWIDTH-1 downto 0);
empty : out std_logic;
full : out std_logic);
end component;
 
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of coregenerator_fifo_receive : component is true;
attribute box_type of coregenerator_fifo_receive : component is "black_box";
begin
 
-----------------------------------------------------------------------------
-- Port map
-----------------------------------------------------------------------------
 
FIFO : coregenerator_fifo_receive
port map (
din => i_din,
rd_clk => i_clk,
rd_en => i_rd_en,
rst => i_rst,
wr_clk => i_clk ,
wr_en => i_wr_en,
dout => o_dout,
empty => o_empty,
full => o_full
);
 
end wrapper;
/gecko3/trunk/GECKO3COM/gecko3com-ip/core/fifo_send.vhd
0,0 → 1,108
-- GECKO3COM IP Core
--
-- Copyright (C) 2009 by
-- ___ ___ _ _
-- ( _ \ ( __)( ) ( )
-- | (_) )| ( | |_| | Bern University of Applied Sciences
-- | _ < | _) | _ | School of Engineering and
-- | (_) )| | | | | | Information Technology
-- (____/ (_) (_) (_)
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- URL to the project description:
-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
----------------------------------------------------------------------------------
--
-- Author: Christoph Zimmermann
-- Date of creation: 17. December 2009
-- Description:
-- This is a wrapper for a FIFO that was generated with the Xilinx Coregenerator
-- to hide the vendor specific stuff and match our naming conventions.
--
-- Target Devices: Xilinx FPGA's due to use of Coregenerator IP cores
-- Tool versions: 11.1
-- Dependencies:
--
----------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library UNISIM;
use UNISIM.vcomponents.all;
 
library UNIMACRO;
use UNIMACRO.vcomponents.all;
 
library work;
use work.GECKO3COM_defines.all;
 
entity send_fifo is
generic (
BUSWIDTH : integer := 16); -- vector size of the FIFO databusses
port (
i_din : in std_logic_vector(BUSWIDTH-1 downto 0);
i_clk : in std_logic;
i_rd_en : in std_logic;
i_rst : in std_logic;
i_wr_en : in std_logic;
o_dout : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
o_empty : out std_logic;
o_full : out std_logic);
end send_fifo;
 
architecture wrapper of send_fifo is
 
-----------------------------------------------------------------------------
-- COMPONENTS
-----------------------------------------------------------------------------
 
component coregenerator_fifo_send
port (
din : in std_logic_vector(BUSWIDTH-1 downto 0);
rd_clk : in std_logic;
rd_en : in std_logic;
rst : in std_logic;
wr_clk : in std_logic;
wr_en : in std_logic;
dout : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
empty : out std_logic;
full : out std_logic);
end component;
 
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of coregenerator_fifo_send : component is true;
attribute box_type of coregenerator_fifo_send : component is "black_box";
begin
 
-----------------------------------------------------------------------------
-- Port map
-----------------------------------------------------------------------------
 
FIFO : coregenerator_fifo_send
port map (
din => i_din,
rd_clk => i_clk,
rd_en => i_rd_en,
rst => i_rst,
wr_clk => i_clk ,
wr_en => i_wr_en,
dout => o_dout,
empty => o_empty,
full => o_full
);
 
end wrapper;

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