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Subversion Repositories generic_booth_multipler

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  • This comparison shows the changes necessary to convert path 
    /generic_booth_multipler
    from Rev 5 to Rev 6
    ↔ Reverse comparison
  •

Rev 5 → Rev 6

/trunk/rtl/modules/00.Adder.vhd
2,11 → 2,14
use IEEE.STD_LOGIC_1164.ALL;
 
entity Adder is
generic(
size : integer:= 4
);
port(
A : in std_logic_vector;
B : in std_logic_vector;
Cin : in std_logic;
S : out std_logic_vector;
A : in std_logic_vector(size-1 downto 0);
B : in std_logic_vector(size-1 downto 0);
Cin : in std_logic;
S : out std_logic_vector(size-1 downto 0);
Cout : out std_logic);
end Adder;
 
/trunk/rtl/modules/00.Alu.vhd
3,34 → 3,58
use IEEE.STD_LOGIC_1164.ALL;
 
entity Alu is
generic(
size : integer:= 4
);
port(
A : in std_logic_vector;
B : in std_logic_vector;
A : in std_logic_vector(size-1 downto 0);
B : in std_logic_vector(size-1 downto 0);
op : in std_logic;
S : out std_logic_vector);
S : out std_logic_vector(size-1 downto 0));
end Alu;
 
architecture Behavioral of Alu is
component Adder is
generic(
size : integer:= 4
);
port(
A : in std_logic_vector;
B : in std_logic_vector;
A : in std_logic_vector(size-1 downto 0);
B : in std_logic_vector(size-1 downto 0);
Cin : in std_logic;
S : out std_logic_vector;
S : out std_logic_vector(size-1 downto 0);
Cout : out std_logic);
end component;
component XorCrearor is
generic(
size : integer:= 4
);
port(
input1 : in std_logic;
input2 : in std_logic_vector;
input2 : in std_logic_vector(size-1 downto 0);
result : out std_logic_vector);
end component;
signal xored: std_logic_vector(A'range);
begin
XO :XorCrearor port map(op,B,xored);
ADD:ADDER port map(A,xored,op,S,open);
XO :XorCrearor
generic map (
size => size
)
port map(
input1 => op,
input2 =>B,
result => xored);
ADD: ADDER
generic map (
size => size
)
port map(
A=> A,
B=> xored,
cin=> op,
S=> S,
cout=> open);
 
 
end Behavioral;
 
/trunk/rtl/modules/00.Ander.vhd
3,10 → 3,13
use IEEE.STD_LOGIC_1164.ALL;
 
entity Ander is
generic(
size : integer:= 4
);
port(
input1 : in std_logic;
input2 : in std_logic_vector;
result : out std_logic_vector);
input2 : in std_logic_vector(size-1 downto 0);
result : out std_logic_vector(size-1 downto 0));
end Ander;
 
architecture Behavioral of Ander is
/trunk/rtl/modules/00.COUNTER.vhd
3,10 → 3,13
use ieee.std_logic_unsigned.all;
 
entity counter is
generic(
size : integer:= 4
);
port(
clock : in std_logic;
reset : in std_logic;
value : out std_logic_vector);
value : out std_logic_vector(size-1 downto 0));
end counter;
 
architecture behavioral of counter is
/trunk/rtl/modules/00.LeftShiftReg.vhd
3,18 → 3,21
use IEEE.STD_LOGIC_1164.ALL;
 
entity LeftShiftReg is
generic(
size : integer:= 4
);
port(
clock :in std_logic;
enable :in std_logic;
shift :in std_logic;
din :in std_logic_vector;
dout :out std_logic_vector);
din :in std_logic_vector(size-1 downto 0);
dout :out std_logic_vector(size-1 downto 0));
end LeftShiftReg;
architecture Behavioral of LeftShiftReg is
signal data : std_logic_vector(din'range);
begin
process(clock,enable,shift)
process(clock, enable, shift)
begin
if(clock'event and clock = '1')then
if(enable = '1')then
/trunk/rtl/modules/00.Regeister.vhd
3,12 → 3,15
use IEEE.STD_LOGIC_1164.ALL;
 
entity Regeister is
generic (
size: integer := 4
);
port(
clock :in std_logic;
clock :in std_logic;
enable :in std_logic;
reset :in std_logic;
din :in std_logic_vector;
dout :out std_logic_vector);
reset :in std_logic;
din :in std_logic_vector(size-1 downto 0);
dout :out std_logic_vector(size-1 downto 0));
end Regeister;
 
architecture Behavioral of Regeister is
/trunk/rtl/modules/00.RightShiftReg.vhd
2,11 → 2,14
use IEEE.STD_LOGIC_1164.ALL;
 
entity RightShiftReg is
generic(
size : integer := 4
);
port(
clock :in std_logic;
enable :in std_logic;
shift :in std_logic;
din :in std_logic_vector;
din :in std_logic_vector(size-1 downto 0);
dout :out std_logic_vector(1 downto 0));
end RightShiftReg;
 
13,7 → 16,7
architecture Behavioral of RightShiftReg is
signal data : std_logic_vector(din'length-1 downto 0);
begin
process(clock,enable,shift)
process(clock, enable, shift)
begin
if(clock'event and clock = '1')then
if(enable = '1')then
/trunk/rtl/modules/00.XorCrearor.vhd
3,10 → 3,13
use IEEE.STD_LOGIC_1164.ALL;
 
entity XorCrearor is
generic (
size: integer := 4
);
port(
input1 : in std_logic;
input2 : in std_logic_vector;
result : out std_logic_vector);
input2 : in std_logic_vector(size-1 downto 0);
result : out std_logic_vector(size-1 downto 0));
end XorCrearor;
 
architecture Behavioral of XorCrearor is
/trunk/rtl/modules/01.BoothDatapath.vhd
2,43 → 2,55
use IEEE.STD_LOGIC_1164.ALL;
 
entity BoothDatapath is
generic(
size: integer := 4
);
port(
clock :in std_logic;
reset :in std_logic;
load :in std_logic;
shift :in std_logic;
X : in std_logic_vector;
Y : in std_logic_vector;
P : out std_logic_vector);
X : in std_logic_vector(size-1 downto 0);
Y : in std_logic_vector(size-1 downto 0);
P : out std_logic_vector(2*size-1 downto 0));
end BoothDatapath;
 
architecture Behavioral of BoothDatapath is
 
component Regeister is
generic (
size: integer := 4
);
port(
clock :in std_logic;
clock :in std_logic;
enable :in std_logic;
reset :in std_logic;
din :in std_logic_vector;
dout :out std_logic_vector);
reset :in std_logic;
din :in std_logic_vector(size-1 downto 0);
dout :out std_logic_vector(size-1 downto 0));
end component;
 
component LeftShiftReg is
port(
clock :in std_logic;
enable :in std_logic;
shift :in std_logic;
din :in std_logic_vector;
dout :out std_logic_vector);
generic(
size : integer:= 4
);
port(
clock :in std_logic;
enable :in std_logic;
shift :in std_logic;
din :in std_logic_vector(size-1 downto 0);
dout :out std_logic_vector(size-1 downto 0));
end component;
component RightShiftReg is
port(
clock : in std_logic;
enable : in std_logic;
shift : in std_logic;
din : in std_logic_vector;
dout : out std_logic_vector(1 downto 0));
generic(
size : integer := 4
);
port(
clock :in std_logic;
enable :in std_logic;
shift :in std_logic;
din :in std_logic_vector(size-1 downto 0);
dout :out std_logic_vector(1 downto 0));
end component;
component BoothEncoder is
port(
50,17 → 62,23
end component;
 
component Alu is
generic(
size : integer:= 4
);
port(
A : in std_logic_vector;
B : in std_logic_vector;
A : in std_logic_vector(size-1 downto 0);
B : in std_logic_vector(size-1 downto 0);
op : in std_logic;
S : out std_logic_vector);
S : out std_logic_vector(size-1 downto 0));
end component;
component Ander is
generic(
size : integer:= 4
);
port(
input1 : in std_logic;
input2 : in std_logic_vector;
result : out std_logic_vector);
input2 : in std_logic_vector(size-1 downto 0);
result : out std_logic_vector(size-1 downto 0));
end component;
signal sign_extended_x,andout,alu_out,p_out,X_reg_dout: std_logic_vector(2*X'length -1 downto 0);
signal lessTwoBits : std_logic_vector(1 downto 0);
78,6 → 96,7
product => product);
Y_REG : RightShiftReg
generic map(size => size+1)
port map(
clock => clock,
enable => load,
86,6 → 105,7
dout => lessTwoBits);
X_REG : LeftShiftReg
generic map(size => 2*size)
port map(
clock => clock,
enable => load,
94,6 → 114,7
dout => X_reg_dout);
ANDing : Ander
generic map(size => 2*size)
port map(
input1 => product,
input2 => X_reg_dout,
100,6 → 121,7
result => AndOut);
Add_Sub : ALU
generic map(size => 2*size)
port map(
A => P_out,
B => AndOut,
107,6 → 129,7
S => ALU_Out);
P_REG : Regeister
generic map(size => 2*size)
port map(
clock => clock,
enable => shift,
/trunk/rtl/modules/02.BoothMultiplier.vhd
17,6 → 17,9
architecture Behavioral of BoothMultiplier is
 
component counter is
generic(
size: integer := 4
);
port( clock : in std_logic;
reset : in std_logic;
value : out std_logic_vector);
23,7 → 26,10
end component counter;
component BoothDatapath is
port(
generic(
size: integer := 4
);
port(
clock :in std_logic;
reset :in std_logic;
load :in std_logic;
58,6 → 64,7
begin
datapath: BoothDatapath
generic map(2**COUNTER_SIZE)
port map(
clock => clock,
reset => reg_clear,
68,6 → 75,7
P => Result);
counter_unit: counter
generic map(size => COUNTER_SIZE)
port map(
clock => clock,
reset => cnt_clear,
75,7 → 83,7
counter_interrupt <= '1' when (counter_value = ONES) else '0';
controller: BoothController
controller: BoothController
port map(
clock => clock,
reset => clear,

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