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/trunk/rtl/verilog/gpio_top.v
45,9 → 45,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/10/31 02:26:51 lampret
// Fixed wb_err_o.
//
// Revision 1.1 2001/09/18 18:49:07 lampret
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
//
187,28 → 184,7
wire rgpio_ctrl_sel; // RGPIO_CTRL select
wire latch_clk; // Latch clock
wire full_decoding; // Full address decoding qualification
wire [gw-1:0] in_muxed; // Muxed inputs
wire wb_ack; // WB Acknowledge
wire wb_err; // WB Error
wire wb_inta; // WB Interrupt
reg [dw-1:0] wb_dat; // WB Data out
`ifdef GPIO_REGISTERED_WB_OUTPUTS
reg wb_ack_o; // WB Acknowledge
reg wb_err_o; // WB Error
reg wb_inta_o; // WB Interrupt
reg [dw-1:0] wb_dat_o; // WB Data out
`endif
wire [gw-1:0] out_pad; // GPIO Outputs
`ifdef GPIO_REGISTERED_IO_OUTPUTS
reg [gw-1:0] out_pad_o; // GPIO Outputs
`endif
wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock
wire pext_clk; // External clock for posedge flops
reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs
`ifdef GPIO_NO_NEGEDGE_FLOPS
`else
reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs
`endif
reg [dw-1:0] wb_dat_o; // Data out
 
//
// All WISHBONE transfer terminations are successful except when:
216,54 → 192,27
// any of the GPIO registers
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
//
 
//
// WB Acknowledge
//
assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;
 
//
// Optional registration of WB Ack
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_ack_o <= #1 1'b0;
else
wb_ack_o <= #1 wb_ack;
`else
assign wb_ack_o = wb_ack;
`endif
 
//
// WB Error
//
assign wb_ack_o = wb_cyc_i & wb_stb_i & !wb_err_o;
`ifdef GPIO_FULL_DECODE
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
assign wb_err_o = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
`else
assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;
assign wb_err_o = wb_cyc_i & wb_stb_i & !full_decoding;
`endif
`else
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
assign wb_err_o = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
`else
assign wb_err = 1'b0;
assign wb_err_o = 1'b0;
`endif
`endif
 
//
// Optional registration of WB error
// Latch clock is selected by RGPIO_CTRL[ECLK]. When it is set,
// external clock is used.
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_err_o <= #1 1'b0;
else
wb_err_o <= #1 wb_err;
`else
assign wb_err_o = wb_err;
`endif
assign latch_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ?
ext_clk_pad_i ^ rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] : wb_clk_i;
 
//
// Full address decoder
311,11 → 260,11
else if (rgpio_out_sel && wb_we_i)
rgpio_out <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
assign rgpio_out = `GPIO_DEF_RPGIO_OUT; // RGPIO_OUT = 0x0
`endif
 
//
// Write to RGPIO_OE. Bits in RGPIO_OE are stored inverted.
// Write to RGPIO_OE
//
`ifdef GPIO_RGPIO_OE
always @(posedge wb_clk_i or posedge wb_rst_i)
322,7 → 271,7
if (wb_rst_i)
rgpio_oe <= #1 {gw{1'b0}};
else if (rgpio_oe_sel && wb_we_i)
rgpio_oe <= #1 ~wb_dat_i[gw-1:0];
rgpio_oe <= #1 wb_dat_i[gw-1:0];
`else
assign rgpio_oe = `GPIO_DEF_RPGIO_OE; // RGPIO_OE = 0x0
`endif
370,148 → 319,64
// Latch into RGPIO_IN
//
`ifdef GPIO_RGPIO_IN
always @(posedge wb_clk_i or posedge wb_rst_i)
always @(posedge latch_clk or posedge wb_rst_i)
if (wb_rst_i)
rgpio_in <= #1 {gw{1'b0}};
else
rgpio_in <= #1 in_muxed;
rgpio_in <= #1 in_pad_i;
`else
assign rgpio_in = in_muxed;
assign rgpio_in = in_pad_i;
`endif
 
//
// Mux inputs directly from input pads with inputs sampled by external clock
// Read GPIO registers
//
assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : in_pad_i;
 
//
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed.
// If negedge flops are allowed, pext_clk only clocks posedge flops.
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~ext_clk_pad_i : ext_clk_pad_i;
`else
assign pext_clk = ext_clk_pad_i;
`endif
 
//
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops.
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
assign extc_in = pextc_sampled;
`else
assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled;
`endif
 
//
// Latch using posedge external clock
//
always @(posedge pext_clk or posedge wb_rst_i)
if (wb_rst_i)
pextc_sampled <= #1 {gw{1'b0}};
else
pextc_sampled <= #1 in_pad_i;
 
//
// Latch using negedge external clock
//
`ifdef GPIO_NO_NEGEDGE_FLOPS
`else
always @(negedge ext_clk_pad_i or posedge wb_rst_i)
if (wb_rst_i)
nextc_sampled <= #1 {gw{1'b0}};
else
nextc_sampled <= #1 in_pad_i;
`endif
 
//
// Mux all registers when doing a read of GPIO registers
//
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
rgpio_ptrig or rgpio_aux or rgpio_ctrl)
case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
`ifdef GPIO_READREGS
`GPIO_RGPIO_OUT: begin
wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_out};
wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_out};
end
`GPIO_RGPIO_OE: begin
wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, ~rgpio_oe};
wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_oe};
end
`GPIO_RGPIO_INTE: begin
wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_inte};
wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_inte};
end
`GPIO_RGPIO_PTRIG: begin
wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_ptrig};
wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_ptrig};
end
`GPIO_RGPIO_AUX: begin
wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_aux};
wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_aux};
end
`GPIO_RGPIO_CTRL: begin
wb_dat[3:0] <= rgpio_ctrl;
wb_dat[dw-1:4] <= {dw-4{1'b0}};
wb_dat_o[3:0] <= rgpio_ctrl;
wb_dat_o[dw-1:4] <= {dw-4{1'b0}};
end
`endif
default: begin
wb_dat[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_in};
wb_dat_o[dw-1:0] <= {{dw-gw{1'b0}}, rgpio_in};
end
endcase
 
//
// WB data output
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= #1 {dw{1'b0}};
else
wb_dat_o <= #1 wb_dat;
`else
assign wb_dat_o = wb_dat;
`endif
 
//
// Generate interrupt request
//
assign wb_inta = ((in_pad_i ^ ~rgpio_ptrig) & rgpio_inte) ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
assign wb_inta_o = ((in_pad_i ^ ~rgpio_ptrig) & rgpio_inte) ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
 
//
// Optional registration of WB interrupt
// Generate output enables from inverted RGPIO_OE bits
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_inta_o <= #1 wb_inta;
else
wb_inta_o <= #1 wb_inta;
`else
assign wb_inta_o = wb_inta;
`endif
assign oen_padoen_o = ~rgpio_oe;
 
//
// Output enables are RGPIO_OE bits
// Generate outputs
//
assign oen_padoen_o = rgpio_oe;
assign out_pad_o = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
 
//
// Generate GPIO outputs
//
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
 
//
// Optional registration of GPIO outputs
//
`ifdef GPIO_REGISTERED_IO_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
out_pad_o <= #1 {gw{1'b0}};
else
out_pad_o <= #1 out_pad;
`else
assign out_pad_o = out_pad;
`endif
 
`else
 
//
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
// is cleared and WISHBONE transfers complete with errors
/trunk/rtl/verilog/gpio_defines.v
44,9 → 44,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/09/18 18:49:07 lampret
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
//
// Revision 1.1 2001/08/21 21:39:28 lampret
// Changed directory structure, port names and drfines.
//
82,37 → 79,6
//
`define GPIO_IMPLEMENTED
 
//
// Define to register all WISHBONE outputs.
//
// Register outputs if you are using GPIO core as a block and synthesizing
// and place&routing it separately from the rest of the system.
//
// If you do not need registered outputs, you can save some area by not defining
// this macro. By default it is defined.
//
`define GPIO_REGISTERED_WB_OUTPUTS
 
//
// Define to register all GPIO pad outputs.
//
// Register outputs if you are using GPIO core as a block and synthesizing
// and place&routing it separately from the rest of the system.
//
// If you do not need registered outputs, you can save some area by not defining
// this macro. By default it is defined.
//
`define GPIO_REGISTERED_IO_OUTPUTS
 
//
// Define to avoid using negative edge clock flip-flops for external clock
// (caused by RGPIO_CTRL[NEC] bit. Instead an inverted external clock with
// positive edge clock flip-flops will be used.
//
// By default it is defined.
//
`define GPIO_NO_NEGEDGE_FLOPS
 
//
// Undefine if you don't need to read GPIO registers except for RGPIO_IN register.
// When it is undefined all reads of GPIO registers return RGPIO_IN register. This
148,7 → 114,7
//
// WISHBONE address bits used for full decoding of GPIO registers.
//
`define GPIO_ADDRHH 6
`define GPIO_ADDRHH 15
`define GPIO_ADDRHL 5
`define GPIO_ADDRLH 1
`define GPIO_ADDRLL 0

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