OpenCores
URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

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Rev 18 → Rev 17

/trunk/bench/verilog/tb_tasks.v
44,9 → 44,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/09/18 16:37:55 lampret
// Changed VCD output location.
//
// Revision 1.2 2001/09/18 15:43:27 lampret
// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.
//
369,14 → 366,9
//
task test_eclk;
integer l1, l2, l3;
integer r1, r2, r3;
integer r1, r2;
begin
 
// Set external clock to low state
tb_top.gpio_mon.set_gpioeclk(0);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
//
// Phase 1
//
391,8 → 383,7
setctrl(0);
 
// Wait for time to advance
@(posedge tb_top.clk);
@(posedge tb_top.clk);
#1000;
 
// Read GPIO_RGPIO_IN
getin(l1);
403,7 → 394,7
// GPIO uses external clock to latch gpio_in
//
 
// Set GPIO to use external clock, NEC bit cleared
// Set GPIO to use external clock
setctrl(1 << `GPIO_RGPIO_CTRL_ECLK);
 
// Put something else on gpio_in pins
410,41 → 401,27
random_gpio(r2);
tb_top.gpio_mon.set_gpioin(r2);
 
// Make an external posedge clock pulse
tb_top.gpio_mon.set_gpioeclk(0);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
tb_top.gpio_mon.set_gpioeclk(1);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
// Wait for time to advance
#1000;
 
// Read RGPIO_IN
// Read GPIO_RGPIO_IN (should be the same as l1)
getin(l2);
 
//
// Phase 3
//
// Change GPIO inputs and WB clock but not external clock.
// RGPIO_IN should not change.
//
// Make an external clock
tb_top.gpio_mon.set_gpioeclk(0);
#10;
tb_top.gpio_mon.set_gpioeclk(1);
#10;
 
// Put something else on gpio_in pins
random_gpio(r3);
tb_top.gpio_mon.set_gpioin(r3);
 
// Wait for WB clock
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Read RGPIO_IN
// Read RGPIO_IN (should be different than l2)
getin(l3);
 
//
// Phase 4
// Phase 3
//
// Compare phases
//
if (l1 == r1 && l2 == r2 && l2 == l3)
if (l1 == l2 && l2 == r1 && l3 == r2)
$write(".");
else
local_errs = local_errs + 1;
456,7 → 433,7
//
task test_nec;
integer l1, l2;
integer r1, r2;
integer r2;
begin
//
// Phase 1
464,50 → 441,35
// Compare RGPIO_IN before and after negative edge
//
 
// Set external clock to low state
tb_top.gpio_mon.set_gpioeclk(0);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
// Clear GPIO_RGPIO_IN
tb_top.gpio_mon.set_gpioin('d0);
 
// Set GPIO to use WB clock
setctrl(0);
 
// Advance time
#1000;
 
// Set GPIO to use external clock and set RGPIO_CTRL[NEC]
setctrl(1 << `GPIO_RGPIO_CTRL_ECLK | 1 << `GPIO_RGPIO_CTRL_NEC);
 
// Put random on gpio inputs
random_gpio(r1);
tb_top.gpio_mon.set_gpioin(r1);
 
// Advance time by making an external negedge clock pulse
tb_top.gpio_mon.set_gpioeclk(1);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
tb_top.gpio_mon.set_gpioeclk(0);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Put something on gpio_in pins
random_gpio(r2);
tb_top.gpio_mon.set_gpioin(r2);
 
// Make an external posedge clock pulse
tb_top.gpio_mon.set_gpioeclk(0);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
tb_top.gpio_mon.set_gpioeclk(1);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
// Wait for time to advance
#1000;
 
// Read RGPIO_IN (should be the same as r1)
// Read RGPIO_IN
getin(l1);
 
// Make an external negedge clock pulse
// Make an external clock
tb_top.gpio_mon.set_gpioeclk(1);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
#10;
tb_top.gpio_mon.set_gpioeclk(0);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
#10;
 
// Read RGPIO_IN (should be the same as r2)
// Read RGPIO_IN (should be different than l1)
getin(l2);
 
//
515,8 → 477,7
//
// Compare phases
//
// $display("l1 %h l2 %h r1 %h r2 %h", l1, l2, r1, r2);
if (l1 == r1 && l2 == r2)
if (!l1 && l2 == r2)
$write(".");
else
local_errs = local_errs + 1;
548,8 → 509,7
tb_top.gpio_mon.set_gpioin(l1);
 
// Advance time
@(posedge tb_top.clk);
@(posedge tb_top.clk);
#1000;
 
// Read GPIO_RGPIO_IN
getin(l2);
583,8 → 543,7
setout(l1);
 
// Advance time
@(posedge tb_top.clk);
@(posedge tb_top.clk);
#1000;
 
// Read gpio_out
tb_top.gpio_mon.get_gpioout(l2);
618,8 → 577,7
setoe(l1);
 
// Advance time
@(posedge tb_top.clk);
@(posedge tb_top.clk);
#1000;
 
// Read gpio_oen
tb_top.gpio_mon.get_gpiooen(l2);
661,8 → 619,7
setout(l3);
 
// Advance time
@(posedge tb_top.clk);
@(posedge tb_top.clk);
#1000;
 
// Read gpio_out
tb_top.gpio_mon.get_gpioout(l4);
695,7 → 652,7
integer r1;
begin
 
$write(" Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");
$write(" Testing control bis RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");
 
//
// Phase 1
723,8 → 680,7
setinte(r1);
 
// Advance time
@(posedge tb_top.clk);
@(posedge tb_top.clk);
#100;
 
// Sample interrupt request. Should be zero.
l1 = tb_top.gpio_top.wb_inta_o;
733,8 → 689,7
tb_top.gpio_mon.set_gpioin(0);
 
// Advance time
@(posedge tb_top.clk);
@(posedge tb_top.clk);
#100;
 
// Sample interrupt request. Should be one.
l2 = tb_top.gpio_top.wb_inta_o;
743,8 → 698,7
setctrl(0);
 
// Advance time
@(posedge tb_top.clk);
@(posedge tb_top.clk);
#100;
 
// Sample interrupt request. Should be zero.
l3 = tb_top.gpio_top.wb_inta_o;
806,8 → 760,7
setinte(r1);
 
// Advance time
@(posedge tb_top.clk);
@(posedge tb_top.clk);
#100;
 
// Sample interrupt request. Should be zero.
l1 = tb_top.gpio_top.wb_inta_o;
816,8 → 769,7
tb_top.gpio_mon.set_gpioin('hffffffff);
 
// Advance time
@(posedge tb_top.clk);
@(posedge tb_top.clk);
#100;
 
// Sample interrupt request. Should be one.
l2 = tb_top.gpio_top.wb_inta_o;
826,8 → 778,7
setctrl(0);
 
// Advance time
@(posedge tb_top.clk);
@(posedge tb_top.clk);
#100;
 
// Sample interrupt request. Should be zero.
l3 = tb_top.gpio_top.wb_inta_o;
/trunk/bench/verilog/tb_defines.v
45,9 → 45,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/08/21 22:01:50 lampret
// More intensive verification.
//
// Revision 1.1 2001/08/21 21:39:27 lampret
// Changed directory structure, port names and drfines.
//
71,6 → 68,6
// means more loops of each subtest (e.g. for some subtests
// 5 means 50 loops, for others 100 etc). Good numbers are from 1
// (very fast and very little verification) to 200 (slow but thorough).
// Default is 200.
// Default is 20.
//
`define GPIO_VERIF_INTENSITY 200

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