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URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

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Rev 21 → Rev 20

/trunk/rtl/verilog/gpio_top.v
45,9 → 45,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2001/12/12 20:35:53 lampret
// Fixing style.
//
// Revision 1.4 2001/12/12 07:12:58 lampret
// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)
//
185,15 → 182,6
`endif
 
//
// GPIO Interrupt Status Register (or no register)
//
`ifdef GPIO_RGPIO_INTS
reg [gw-1:0] rgpio_ints; // RGPIO_INTS register
`else
wire [gw-1:0] rgpio_ints; // No register
`endif
 
//
// Internal wires & regs
//
wire rgpio_out_sel; // RGPIO_OUT select
202,7 → 190,6
wire rgpio_ptrig_sel;// RGPIO_PTRIG select
wire rgpio_aux_sel; // RGPIO_AUX select
wire rgpio_ctrl_sel; // RGPIO_CTRL select
wire rgpio_ints_sel; // RGPIO_INTS select
wire latch_clk; // Latch clock
wire full_decoding; // Full address decoding qualification
wire [gw-1:0] in_muxed; // Muxed inputs
302,7 → 289,6
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
 
//
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
314,7 → 300,7
else if (rgpio_ctrl_sel && wb_we_i)
rgpio_ctrl <= #1 wb_dat_i[3:0];
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;
rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INT] | wb_inta_o;
`else
assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1
`endif
469,9 → 455,6
wb_dat[dw-1:4] = {dw-4{1'b0}};
end
`endif
`GPIO_RGPIO_INTS: begin
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ints};
end
default: begin
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_in};
end
491,24 → 474,9
`endif
 
//
// RGPIO_INTS
//
`ifdef GPIO_RGPIO_INTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
rgpio_ints <= #1 {gw{1'b0}};
else if (rgpio_ints_sel && wb_we_i)
rgpio_ints <= #1 wb_dat_i[gw-1:0];
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
rgpio_ints <= #1 rgpio_ints | (in_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
`else
assign rgpio_ints = (in_pad_i ^ ~rgpio_ptrig) & rgpio_inte;
`endif
 
//
// Generate interrupt request
//
assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
assign wb_inta = ((in_pad_i ^ ~rgpio_ptrig) & rgpio_inte) ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
 
//
// Optional registration of WB interrupt
/trunk/rtl/verilog/gpio_defines.v
44,9 → 44,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/11/15 02:24:37 lampret
// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
//
// Revision 1.1 2001/09/18 18:49:07 lampret
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
//
181,7 → 178,6
`define GPIO_RGPIO_PTRIG 3'h4 // Address 0x10
`define GPIO_RGPIO_AUX 3'h5 // Address 0x14
`define GPIO_RGPIO_CTRL 3'h6 // Address 0x18
`define GPIO_RGPIO_INTS 3'h7 // Address 0x1c
 
//
// Default values for unimplemented GPIO registers
203,4 → 199,4
`define GPIO_RGPIO_CTRL_ECLK 0
`define GPIO_RGPIO_CTRL_NEC 1
`define GPIO_RGPIO_CTRL_INTE 2
`define GPIO_RGPIO_CTRL_INTS 3
`define GPIO_RGPIO_CTRL_INT 3
/trunk/bench/verilog/tb_tasks.v
44,9 → 44,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/11/15 02:26:32 lampret
// Updated timing and fixed some typing errors.
//
// Revision 1.3 2001/09/18 16:37:55 lampret
// Changed VCD output location.
//
160,18 → 157,6
endtask
 
//
// Set RGPIO_INTS register
//
task setints;
input [31:0] val;
 
begin
#100 tb_top.wb_master.wr(`GPIO_RGPIO_INTS<<sh_addr, val, 4'b1111);
end
 
endtask
 
//
// Display RGPIO_IN register
//
task showin;
264,19 → 249,6
endtask
 
//
// Display RGPIO_INTS register
//
task showints;
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp);
$write(" RGPIO_INTS:%h", tmp);
end
 
endtask
 
//
// Compare parameter with RGPIO_IN register
//
task comp_in;
381,18 → 353,6
endtask
 
//
// Get RGPIO_INTS register
//
task getints;
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp);
end
 
endtask
 
//
// Calculate a random and make it narrow to fit on GPIO I/O pins
//
task random_gpio;
730,7 → 690,7
// Test interrupts
//
task test_ints;
integer l1, l2, l3, l4;
integer l1, l2, l3;
integer i, rnd, err;
integer r1;
begin
755,9 → 715,6
 
// Low level triggering
setptrig(0);
// Clear RGPIO_INTS
setints(0);
 
// Enable interrupts in RGPIO_CTRL
setctrl(1 << `GPIO_RGPIO_CTRL_INTE);
778,7 → 735,6
// Advance time
@(posedge tb_top.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Sample interrupt request. Should be one.
l2 = tb_top.gpio_top.wb_inta_o;
793,14 → 749,9
// Sample interrupt request. Should be zero.
l3 = tb_top.gpio_top.wb_inta_o;
 
// Get RGPIO_INTS. Should be nonzero.
getints(l4);
 
// Check for errors
if (l1 || !l2 || l3 || (l4 != r1)) begin
$display("l1 %h l2 %h l3 %h l4 %h", l1, l2, l3, l4);
if (l1 || !l2 || l3)
err = err +1;
end
end
// Enable spurious interrupt monitor
845,9 → 796,6
// Set gpio_in pins
tb_top.gpio_mon.set_gpioin('h00000000);
 
// Clear old interrupts
setints(0);
 
// High level triggering
setptrig('hffffffff);
 
870,7 → 818,6
// Advance time
@(posedge tb_top.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Sample interrupt request. Should be one.
l2 = tb_top.gpio_top.wb_inta_o;
877,7 → 824,6
 
// Clear interrupt request
setctrl(0);
setints(0);
 
// Advance time
@(posedge tb_top.clk);
921,7 → 867,7
//
integer i;
initial begin
`ifdef GPIO_DUMP_VCD
`ifdef DUMP_VCD
$dumpfile("../out/tb_top.vcd");
$dumpvars(0);
`endif
/trunk/doc/gpio_spec.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/src/gpio_spec.doc Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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