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URL https://opencores.org/ocsvn/gpio/gpio/trunk

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Rev 26 → Rev 25

/trunk/rtl/verilog/gpio_top.v
45,9 → 45,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10 2002/03/13 20:47:57 lampret
// Ports changed per Ran Aviram suggestions.
//
// Revision 1.9 2002/03/09 03:43:27 lampret
// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)
//
465,19 → 462,19
case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
`ifdef GPIO_READREGS
`GPIO_RGPIO_OUT: begin
wb_dat[dw-1:0] = rgpio_out;
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_out};
end
`GPIO_RGPIO_OE: begin
wb_dat[dw-1:0] = ~rgpio_oe;
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, ~rgpio_oe};
end
`GPIO_RGPIO_INTE: begin
wb_dat[dw-1:0] = rgpio_inte;
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_inte};
end
`GPIO_RGPIO_PTRIG: begin
wb_dat[dw-1:0] = rgpio_ptrig;
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ptrig};
end
`GPIO_RGPIO_AUX: begin
wb_dat[dw-1:0] = rgpio_aux;
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_aux};
end
`GPIO_RGPIO_CTRL: begin
wb_dat[3:0] = rgpio_ctrl;
485,10 → 482,10
end
`endif
`GPIO_RGPIO_INTS: begin
wb_dat[dw-1:0] = rgpio_ints;
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_ints};
end
default: begin
wb_dat[dw-1:0] = rgpio_in;
wb_dat[dw-1:0] = {{dw-gw{1'b0}}, rgpio_in};
end
endcase
 
/trunk/bench/verilog/tb_top.v
44,9 → 44,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/09/18 15:43:28 lampret
// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.
//
// Revision 1.1 2001/08/21 21:39:27 lampret
// Changed directory structure, port names and drfines.
//
139,10 → 136,10
.aux_i(gpio_aux),
 
// External GPIO Interface
.ext_pad_i(gpio_in),
.clk_pad_i(gpio_eclk),
.ext_pad_o(gpio_out),
.ext_padoen_o(gpio_oen)
.in_pad_i(gpio_in),
.ext_clk_pad_i(gpio_eclk),
.out_pad_o(gpio_out),
.oen_padoen_o(gpio_oen)
);
 
//

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