OpenCores
URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 3 to Rev 2
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  •

Rev 3 → Rev 2

/trunk/bench/gpio_mon.v
44,10 → 44,7
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/06/05 07:45:22 lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
`include "timescale.vh"
 
97,7 → 94,7
// Set gpio_eclk
//
task set_gpioeclk;
input [31:0] val;
input val;
begin
gpio_eclk = val[0];
end
/trunk/bench/tb_top.v
44,19 → 44,15
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/06/05 07:45:22 lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
`include "timescale.vh"
`include "defines.vh"
 
module tb_top;
 
parameter aw = 32;
parameter dw = 32;
parameter gw = `GPIO_IOS;
parameter gw = 32;
 
//
// Interconnect wires
/trunk/bench/tb_defines.vh
45,23 → 45,7
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/06/05 07:45:22 lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
//
// Define if you want VCD dump
//
//`define DEBUG
`define DUMP_VCD
 
//
// Intensity of verification
//
// Higher number means more intensive verification. Higher number
// means more loops of each subtest (e.g. for some subtests
// 5 means 50 loops, for others 100 etc). Good numbers are from 1
// (very fast and very little verification) to 200 (slow but thorough).
// Default is 20.
//
`define VERIF_INTENSITY 20
/trunk/bench/tb_tasks.v
44,10 → 44,7
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2001/06/05 07:45:22 lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
`include "timescale.vh"
`include "defines.vh"
58,10 → 55,7
integer nr_failed;
integer ints_disabled;
integer ints_working;
integer local_errs;
 
parameter sh_addr = `GPIO_ADDRLH+1;
 
//
// Count/report failed tests
//
79,7 → 73,7
input [31:0] val;
 
begin
#100 tb_top.wb_master.wr(`RGPIO_OUT<<sh_addr, val, 4'b1111);
#100 tb_top.wb_master.wr(`RGPIO_OUT<<2, val, 4'b1111);
end
 
endtask
91,7 → 85,7
input [31:0] val;
 
begin
#100 tb_top.wb_master.wr(`RGPIO_OE<<sh_addr, val, 4'b1111);
#100 tb_top.wb_master.wr(`RGPIO_OE<<2, val, 4'b1111);
end
 
endtask
103,7 → 97,7
input [31:0] val;
 
begin
#100 tb_top.wb_master.wr(`RGPIO_INTE<<sh_addr, val, 4'b1111);
#100 tb_top.wb_master.wr(`RGPIO_INTE<<2, val, 4'b1111);
end
 
endtask
115,7 → 109,7
input [31:0] val;
 
begin
#100 tb_top.wb_master.wr(`RGPIO_PTRIG<<sh_addr, val, 4'b1111);
#100 tb_top.wb_master.wr(`RGPIO_PTRIG<<2, val, 4'b1111);
end
 
endtask
127,7 → 121,7
input [31:0] val;
 
begin
#100 tb_top.wb_master.wr(`RGPIO_AUX<<sh_addr, val, 4'b1111);
#100 tb_top.wb_master.wr(`RGPIO_AUX<<2, val, 4'b1111);
end
 
endtask
139,7 → 133,7
input [31:0] val;
 
begin
#100 tb_top.wb_master.wr(`RGPIO_CTRL<<sh_addr, val, 4'b1111);
#100 tb_top.wb_master.wr(`RGPIO_CTRL<<2, val, 4'b1111);
end
 
endtask
151,7 → 145,7
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`RGPIO_IN<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_IN<<2, tmp);
$write(" RGPIO_IN: %h", tmp);
end
 
164,7 → 158,7
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`RGPIO_OUT<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_OUT<<2, tmp);
$write(" RGPIO_OUT: %h", tmp);
end
 
178,7 → 172,7
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`RGPIO_OE<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_OE<<2, tmp);
$write(" RGPIO_OE:%h", tmp);
end
 
191,7 → 185,7
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`RGPIO_INTE<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_INTE<<2, tmp);
$write(" RGPIO_INTE:%h", tmp);
end
 
204,7 → 198,7
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`RGPIO_PTRIG<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_PTRIG<<2, tmp);
$write(" RGPIO_PTRIG:%h", tmp);
end
 
217,7 → 211,7
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`RGPIO_AUX<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_AUX<<2, tmp);
$write(" RGPIO_AUX:%h", tmp);
end
 
230,7 → 224,7
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`RGPIO_CTRL<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_CTRL<<2, tmp);
$write(" RGPIO_CTRL: %h", tmp);
end
 
246,7 → 240,7
reg [31:0] tmp;
reg ret;
begin
#100 tb_top.wb_master.rd(`RGPIO_IN<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_IN<<2, tmp);
 
if (tmp == val)
ret = 1;
263,7 → 257,7
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`RGPIO_IN<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_IN<<2, tmp);
end
 
endtask
275,7 → 269,7
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`RGPIO_OUT<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_OUT<<2, tmp);
end
 
endtask
287,7 → 281,7
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`RGPIO_OE<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_OE<<2, tmp);
end
 
endtask
299,7 → 293,7
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`RGPIO_INTE<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_INTE<<2, tmp);
end
 
endtask
311,7 → 305,7
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`RGPIO_PTRIG<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_PTRIG<<2, tmp);
end
 
endtask
323,7 → 317,7
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`RGPIO_AUX<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_AUX<<2, tmp);
end
 
endtask
335,30 → 329,18
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`RGPIO_CTRL<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`RGPIO_CTRL<<2, tmp);
end
 
endtask
 
//
// Calculate a random and make it narrow to fit on GPIO I/O pins
//
task random_gpio;
output [31:0] tmp;
 
begin
tmp = $random & ((1<<`GPIO_IOS)-1);
end
 
endtask
 
//
// Test operation of control bit RGPIO_CTRL[ECLK]
//
task test_eclk;
integer l1, l2, l3;
integer r1, r2;
begin
$write(" Testing control bit RGPIO_CTRL[ECLK] ...");
 
//
// Phase 1
367,8 → 349,7
//
 
// Put something on gpio_in pins
random_gpio(r1);
tb_top.gpio_mon.set_gpioin(r1);
tb_top.gpio_mon.set_gpioin('d12345678);
 
// Reset GPIO_CTRL
setctrl(0);
389,8 → 370,7
setctrl(1 << `RGPIO_CTRL_ECLK);
 
// Put something else on gpio_in pins
random_gpio(r2);
tb_top.gpio_mon.set_gpioin(r2);
tb_top.gpio_mon.set_gpioin('d55667788);
 
// Wait for time to advance
#1000;
412,10 → 392,10
//
// Compare phases
//
if (l1 == l2 && l2 == r1 && l3 == r2)
$write(".");
if (l1 == l2 && l2 == 'd12345678 && l3 == 'd55667788)
$display(" OK");
else
local_errs = local_errs + 1;
failed;
end
endtask
 
424,8 → 404,9
//
task test_nec;
integer l1, l2;
integer r2;
begin
$write(" Testing control bit RGPIO_CTRL[NEC] ...");
 
//
// Phase 1
//
445,8 → 426,7
setctrl(1 << `RGPIO_CTRL_ECLK | 1 << `RGPIO_CTRL_NEC);
 
// Put something on gpio_in pins
random_gpio(r2);
tb_top.gpio_mon.set_gpioin(r2);
tb_top.gpio_mon.set_gpioin('d11112222);
 
// Wait for time to advance
#1000;
468,10 → 448,10
//
// Compare phases
//
if (!l1 && l2 == r2)
$write(".");
if (!l1 && l2 == 'd11112222)
$display(" OK");
else
local_errs = local_errs + 1;
failed;
end
endtask
 
494,9 → 474,9
setctrl(0);
 
err = 0;
for (i = 0; i < 10 * `VERIF_INTENSITY; i = i +1) begin
for (i = 0; i < 10; i = i +1) begin
// Put something on gpio_in pins
random_gpio(l1);
l1 = $random;
tb_top.gpio_mon.set_gpioin(l1);
 
// Advance time
528,7 → 508,7
//
 
err = 0;
for (i = 0; i < 10 * `VERIF_INTENSITY; i = i +1) begin
for (i = 0; i < 10; i = i +1) begin
// Put something in RGPIO_OUT pins
l1 = $random;
setout(l1);
562,7 → 542,7
//
 
err = 0;
for (i = 0; i < 10 * `VERIF_INTENSITY; i = i +1) begin
for (i = 0; i < 10; i = i +1) begin
// Put something in RGPIO_OE pins
l1 = $random;
setoe(l1);
596,7 → 576,7
//
 
err = 0;
for (i = 0; i < 10 * `VERIF_INTENSITY; i = i +1) begin
for (i = 0; i < 100; i = i +1) begin
// Put something on gpio_aux pins
l1 = $random;
tb_top.gpio_mon.set_gpioaux(l1);
640,9 → 620,7
task test_ints;
integer l1, l2, l3;
integer i, rnd, err;
integer r1;
begin
 
$write(" Testing control bis RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");
 
//
655,11 → 633,13
ints_disabled = 0;
 
err = 0;
for( i = 0; i < 10 * `VERIF_INTENSITY; i = i + 1) begin
for( i = 0; i < 10; i = i + 1) begin
 
// Get some random bits
rnd = $random;
 
// Set gpio_in pins
r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
tb_top.gpio_mon.set_gpioin(r1);
tb_top.gpio_mon.set_gpioin('hffffffff);
 
// Low level triggering
setptrig(0);
668,7 → 648,7
setctrl(1 << `RGPIO_CTRL_INTE);
 
// Enable interrupts in RGPIO_INTE
setinte(r1);
setinte(rnd);
 
// Advance time
#100;
719,7 → 699,6
task test_ptrig;
integer l1, l2, l3;
integer i, rnd, err;
integer r1;
begin
$write(" Testing ptrig features ...");
 
733,10 → 712,10
ints_disabled = 0;
 
err = 0;
for( i = 0; i < 10 * `VERIF_INTENSITY; i = i + 1) begin
for( i = 0; i < 10; i = i + 1) begin
 
// Set bits to one
r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
// Get some random bits
rnd = $random;
 
// Set gpio_in pins
tb_top.gpio_mon.set_gpioin('h00000000);
748,7 → 727,7
setctrl(1 << `RGPIO_CTRL_INTE);
 
// Enable interrupts in RGPIO_INTE
setinte(r1);
setinte(rnd);
 
// Advance time
#100;
807,7 → 786,6
//
// Start of testbench test tasks
//
integer i;
initial begin
`ifdef DUMP_VCD
$dumpfile("../sim/tb_top.vcd");
826,36 → 804,14
$display;
$display("I. Testing correct operation of RGPIO_CTRL control bits");
$display;
 
 
$write(" Testing control bit RGPIO_CTRL[ECLK] ...");
local_errs = 0;
for (i = 0; i < 10 * `VERIF_INTENSITY; i = i + 1)
test_eclk;
if (local_errs == 0)
$display(" OK");
else
failed;
 
 
$write(" Testing control bit RGPIO_CTRL[NEC] ...");
local_errs = 0;
for (i = 0; i < 10 * `VERIF_INTENSITY; i = i + 1)
test_nec;
if (local_errs == 0)
$display(" OK");
else
failed;
 
test_eclk;
test_nec;
test_ints;
 
$display;
$display("II. Testing modes of operation ...");
$display;
 
test_simple;
test_ptrig;
 
$display;
$display("###");
$display("### FAILED TESTS: %d ###", nr_failed);

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