URL
https://opencores.org/ocsvn/gpio/gpio/trunk
Subversion Repositories gpio
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- from Rev 42 to Rev 41
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Rev 42 → Rev 41
/tags/rel_7/doc/src/gpio_spec.doc
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tags/rel_7/doc/src/gpio_spec.doc
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Index: tags/rel_7/doc/gpio_spec.pdf
===================================================================
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Index: tags/rel_7/doc/gpio_spec.pdf
===================================================================
--- tags/rel_7/doc/gpio_spec.pdf (revision 42)
+++ tags/rel_7/doc/gpio_spec.pdf (nonexistent)
tags/rel_7/doc/gpio_spec.pdf
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Index: tags/rel_7/sim/rtl_sim/run/run_sim.scr
===================================================================
--- tags/rel_7/sim/rtl_sim/run/run_sim.scr (revision 42)
+++ tags/rel_7/sim/rtl_sim/run/run_sim.scr (nonexistent)
@@ -1,102 +0,0 @@
-#!/bin/csh -f
-
-if ( $# < 1 ) then
- echo "First argument must be a top level module name!"
- exit
-else
- set SIM_TOP = $1
-endif
-
-set current_par = 1
-set output_waveform = 0
-while ( $current_par < $# )
- @ current_par = $current_par + 1
- case wave:
- @ output_waveform = 1
- breaksw
- default:
- echo 'Unknown option "'$argv[$current_par]'"!'
- exit
- breaksw
- endsw
-end
-
-echo "-CDSLIB ../bin/cds.lib" > ncvlog.args
-echo "-HDLVAR ../bin/hdl.var" >> ncvlog.args
-echo "-MESSAGES" >> ncvlog.args
-echo "-INCDIR ../../../bench/verilog" >> ncvlog.args
-echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args
-echo "-NOCOPYRIGHT" >> ncvlog.args
-echo "-LOGFILE ../log/ncvlog.log" >> ncvlog.args
-
-foreach filename ( `cat ../bin/rtl_file_list` )
- echo "../../../rtl/verilog/"$filename >> ncvlog.args
-end
-
-foreach filename ( `cat ../bin/sim_file_list` )
- echo "../../../bench/verilog/"$filename >> ncvlog.args
-end
-
-ncvlog -f ncvlog.args
-
-echo "-MESSAGES" > ncelab.args
-echo "-NOCOPYRIGHT" >> ncelab.args
-echo "-CDSLIB ../bin/cds.lib" >> ncelab.args
-echo "-HDLVAR ../bin/hdl.var" >> ncelab.args
-echo "-LOGFILE ../log/ncelab.log" >> ncelab.args
-echo "-SNAPSHOT worklib.bench:rtl" >> ncelab.args
-echo "-NO_TCHK_MSG" >> ncelab.args
-echo "-ACCESS +RWC" >> ncelab.args
-echo "worklib.tb_tasks" >> ncelab.args
-echo worklib.$SIM_TOP >> ncelab.args
-
-ncelab -f ncelab.args
-
-echo "-MESSAGES" > ncsim.args
-echo "-NOCOPYRIGHT" >> ncsim.args
-echo "-CDSLIB ../bin/cds.lib" >> ncsim.args
-echo "-HDLVAR ../bin/hdl.var" >> ncsim.args
-echo "-INPUT ncsim.tcl" >> ncsim.args
-echo "-LOGFILE ../log/ncsim.log" >> ncsim.args
-echo "worklib.bench:rtl" >> ncsim.args
-
-if ( $output_waveform ) then
- echo "database -open waves -shm -into ../out/waves.shm" > ./ncsim.tcl
- echo "probe -create -database waves $SIM_TOP -shm -all -depth all" >> ./ncsim.tcl
- echo "run" >> ./ncsim.tcl
-else
- echo "run" > ./ncsim.tcl
-endif
-
-echo "quit" >> ncsim.tcl
-
-ncsim -LICQUEUE -f ./ncsim.args
-
-set exit_line_nb = `sed -n '/exit/=' < ../log/ncsim.log`
-
-#echo "$exit_line_nb"
-
-set dead_line_nb = 0
-
-if ( $exit_line_nb ) then
-
- @ dead_line_nb = $exit_line_nb - 1
- set exit_line=`sed -n $exit_line_nb's/exit/&/gp' < ../log/ncsim.log`
- set dead_line=`sed -n $dead_line_nb's/report/&/gp' < ../log/ncsim.log`
-
- echo "$dead_line"
- echo "$exit_line"
-
- echo "TEST: gpio"
- if ( "$dead_line" == "report (deaddead)" ) then
- if ( "$exit_line" == "exit (00000000)" ) then
- echo "STATUS: passed" #|tee -a ../log/run_sim.log 2>&1
- else
- echo "STATUS: failed" #|tee -a ../log/run_sim.log 2>&1
- endif
- else
- echo "STATUS: failed"
- endif
-
-endif
-
tags/rel_7/sim/rtl_sim/run/run_sim.scr
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\ No newline at end of property
Index: tags/rel_7/sim/rtl_sim/bin/cds.lib
===================================================================
--- tags/rel_7/sim/rtl_sim/bin/cds.lib (revision 42)
+++ tags/rel_7/sim/rtl_sim/bin/cds.lib (nonexistent)
@@ -1,6 +0,0 @@
-#
-# cds.lib: Defines the locations of compiled libraries.
-# Created by ncprep on Tue Nov 11 00:24:06 2003
-#
-
-define worklib ./INCA_libs/worklib
Index: tags/rel_7/sim/rtl_sim/bin/hdl.var
===================================================================
--- tags/rel_7/sim/rtl_sim/bin/hdl.var (revision 42)
+++ tags/rel_7/sim/rtl_sim/bin/hdl.var (nonexistent)
@@ -1,9 +0,0 @@
-#
-# hdl.var: Defines variables used by the INCA tools.
-# Created by ncprep on Tue Nov 11 00:24:06 2003
-#
-
-softinclude $CDS_INST_DIR/tools/inca/files/hdl.var
-
-define LIB_MAP ( $LIB_MAP, + => worklib )
-define VIEW_MAP ( $VIEW_MAP, .v => v)
Index: tags/rel_7/sim/rtl_sim/bin/sim.sh
===================================================================
--- tags/rel_7/sim/rtl_sim/bin/sim.sh (revision 42)
+++ tags/rel_7/sim/rtl_sim/bin/sim.sh (nonexistent)
@@ -1,125 +0,0 @@
-#!/bin/bash
-
-#
-# This script runs RTL and gate-level simulation using different simultion tools.
-# Right now Cadence Verilog-XL and NCSim are supported.
-#
-# Author: Damjan Lampret
-#
-
-#
-# User definitions
-#
-
-# Set simulation tool you are using (xl, ncsim, ncver)
-SIMTOOL=ncsim
-
-# Set test bench top module(s)
-TB_TOP="tb_tasks"
-
-# Set include directories
-INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/"
-
-# Set test bench files
-BENCH_FILES="../../../bench/verilog/*.v"
-
-# Set RTL source files
-RTL_FILES="../../../rtl/verilog/*.v"
-
-# Set gate-level netlist files
-GATE_FILES="../syn/out/final_gpio.v"
-
-# Set libraries (standard cell etc.)
-LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v"
-
-# Set parameters for simulation tool
-if [ $SIMTOOL == xl ]; then
- PARAM="+turbo+3 -q"
- for i in $INCLUDE_DIRS; do
- INCDIR=$INCDIR" +incdir+$i"
- done
-elif [ $SIMTOOL == ncver ]; then
- NCVER_PARAM=""
- for i in $INCLUDE_DIRS; do
- INCDIR=$INCDIR" +incdir+$i"
- done
-elif [ $SIMTOOL == ncsim ]; then
- NCPREP_PARAM="-UPDATE +overwrite"
- NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT"
- for i in $INCLUDE_DIRS; do
- INCDIR=$INCDIR" +incdir+$i"
- done
-else
- echo "$SIMTOOL is unsupported simulation tool."
- exit 0
-fi
-
-#
-# Don't change anything below unless you know what you are doing
-#
-
-# Run simulation in sim directory
-#cd ../sim
-
-# Run actual simulation
-
-# Cadence Verilog-XL
-if [ $SIMTOOL == xl ]; then
-
- # RTL simulation
- if [ "$1" == rtl ]; then
- verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES
-
- # Gate-level simulation
- elif [ "$1" == gate ]; then
- verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
-
- # Wrong parameter or no parameter
- else
- echo "Usage: $0 [rtl|gate]"
- exit 0
- fi
-
-# Cadence Ncverilog
-elif [ $SIMTOOL == ncver ]; then
-
- # RTL simulation
- if [ "$1" == rtl ]; then
- ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES
- cp ncverilog.log ../log
-
- # Gate-level simulation
- elif [ "$1" == gate ]; then
- ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
- cp ncverilog.log ../log
-
- # Wrong parameter or no parameter
- else
- echo "Usage: $0 [rtl|gate]"
- exit 0
- fi
-
-# Cadence Ncsim
-elif [ $SIMTOOL == ncsim ]; then
-
- # RTL simulation
- if [ "$1" == rtl ]; then
- ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES
- ./RUN_NC
-
- # Gate-level simulation
- elif [ "$1" == gate ]; then
- ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
- ./RUN_NC
-
- # Wrong parameter or no parameter
- else
- echo "Usage: $0 [rtl|gate]"
- exit 0
- fi
-
-# Unsupported simulation tool
-else
- echo "$SIMTOOL is unsupported simulation tool."
- exit 0;
-fi
tags/rel_7/sim/rtl_sim/bin/sim.sh
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Index: tags/rel_7/sim/rtl_sim/bin/sim_file_list
===================================================================
--- tags/rel_7/sim/rtl_sim/bin/sim_file_list (revision 42)
+++ tags/rel_7/sim/rtl_sim/bin/sim_file_list (nonexistent)
@@ -1,7 +0,0 @@
-clkrst.v
-gpio_mon.v
-wb_master.v
-tb_tasks.v
-tb_top.v
-
-
tags/rel_7/sim/rtl_sim/bin/sim_file_list
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## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_7/sim/rtl_sim/bin/INCA_libs/worklib/inca.linux.138.pak
===================================================================
--- tags/rel_7/sim/rtl_sim/bin/INCA_libs/worklib/inca.linux.138.pak (revision 42)
+++ tags/rel_7/sim/rtl_sim/bin/INCA_libs/worklib/inca.linux.138.pak (nonexistent)
@@ -1,3216 +0,0 @@
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