URL
https://opencores.org/ocsvn/gpio/gpio/trunk
Subversion Repositories gpio
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 46 to Rev 45
- ↔ Reverse comparison
Rev 46 → Rev 45
/tags/rel_9/sim/rtl_sim/run/run_sim
File deleted
tags/rel_9/sim/rtl_sim/run/run_sim
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_9/sim/rtl_sim/bin/rtl_file_list
===================================================================
--- tags/rel_9/sim/rtl_sim/bin/rtl_file_list (revision 46)
+++ tags/rel_9/sim/rtl_sim/bin/rtl_file_list (nonexistent)
@@ -1 +0,0 @@
-gpio_top.v
tags/rel_9/sim/rtl_sim/bin/rtl_file_list
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_9/sim/rtl_sim/bin/cds.lib
===================================================================
--- tags/rel_9/sim/rtl_sim/bin/cds.lib (revision 46)
+++ tags/rel_9/sim/rtl_sim/bin/cds.lib (nonexistent)
@@ -1,6 +0,0 @@
-#
-# cds.lib: Defines the locations of compiled libraries.
-# Created by ncprep on Tue Nov 11 00:24:06 2003
-#
-
-define worklib ./INCA_libs/worklib
Index: tags/rel_9/sim/rtl_sim/bin/hdl.var
===================================================================
--- tags/rel_9/sim/rtl_sim/bin/hdl.var (revision 46)
+++ tags/rel_9/sim/rtl_sim/bin/hdl.var (nonexistent)
@@ -1,9 +0,0 @@
-#
-# hdl.var: Defines variables used by the INCA tools.
-# Created by ncprep on Tue Nov 11 00:24:06 2003
-#
-
-softinclude $CDS_INST_DIR/tools/inca/files/hdl.var
-
-define LIB_MAP ( $LIB_MAP, + => worklib )
-define VIEW_MAP ( $VIEW_MAP, .v => v)
Index: tags/rel_9/sim/rtl_sim/bin/sim.sh
===================================================================
--- tags/rel_9/sim/rtl_sim/bin/sim.sh (revision 46)
+++ tags/rel_9/sim/rtl_sim/bin/sim.sh (nonexistent)
@@ -1,125 +0,0 @@
-#!/bin/bash
-
-#
-# This script runs RTL and gate-level simulation using different simultion tools.
-# Right now Cadence Verilog-XL and NCSim are supported.
-#
-# Author: Damjan Lampret
-#
-
-#
-# User definitions
-#
-
-# Set simulation tool you are using (xl, ncsim, ncver)
-SIMTOOL=ncsim
-
-# Set test bench top module(s)
-TB_TOP="tb_tasks"
-
-# Set include directories
-INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/"
-
-# Set test bench files
-BENCH_FILES="../../../bench/verilog/*.v"
-
-# Set RTL source files
-RTL_FILES="../../../rtl/verilog/*.v"
-
-# Set gate-level netlist files
-GATE_FILES="../syn/out/final_gpio.v"
-
-# Set libraries (standard cell etc.)
-LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v"
-
-# Set parameters for simulation tool
-if [ $SIMTOOL == xl ]; then
- PARAM="+turbo+3 -q"
- for i in $INCLUDE_DIRS; do
- INCDIR=$INCDIR" +incdir+$i"
- done
-elif [ $SIMTOOL == ncver ]; then
- NCVER_PARAM=""
- for i in $INCLUDE_DIRS; do
- INCDIR=$INCDIR" +incdir+$i"
- done
-elif [ $SIMTOOL == ncsim ]; then
- NCPREP_PARAM="-UPDATE +overwrite"
- NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT"
- for i in $INCLUDE_DIRS; do
- INCDIR=$INCDIR" +incdir+$i"
- done
-else
- echo "$SIMTOOL is unsupported simulation tool."
- exit 0
-fi
-
-#
-# Don't change anything below unless you know what you are doing
-#
-
-# Run simulation in sim directory
-#cd ../sim
-
-# Run actual simulation
-
-# Cadence Verilog-XL
-if [ $SIMTOOL == xl ]; then
-
- # RTL simulation
- if [ "$1" == rtl ]; then
- verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES
-
- # Gate-level simulation
- elif [ "$1" == gate ]; then
- verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
-
- # Wrong parameter or no parameter
- else
- echo "Usage: $0 [rtl|gate]"
- exit 0
- fi
-
-# Cadence Ncverilog
-elif [ $SIMTOOL == ncver ]; then
-
- # RTL simulation
- if [ "$1" == rtl ]; then
- ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES
- cp ncverilog.log ../log
-
- # Gate-level simulation
- elif [ "$1" == gate ]; then
- ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
- cp ncverilog.log ../log
-
- # Wrong parameter or no parameter
- else
- echo "Usage: $0 [rtl|gate]"
- exit 0
- fi
-
-# Cadence Ncsim
-elif [ $SIMTOOL == ncsim ]; then
-
- # RTL simulation
- if [ "$1" == rtl ]; then
- ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES
- ./RUN_NC
-
- # Gate-level simulation
- elif [ "$1" == gate ]; then
- ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
- ./RUN_NC
-
- # Wrong parameter or no parameter
- else
- echo "Usage: $0 [rtl|gate]"
- exit 0
- fi
-
-# Unsupported simulation tool
-else
- echo "$SIMTOOL is unsupported simulation tool."
- exit 0;
-fi
tags/rel_9/sim/rtl_sim/bin/sim.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_9/sim/rtl_sim/bin/sim_file_list
===================================================================
--- tags/rel_9/sim/rtl_sim/bin/sim_file_list (revision 46)
+++ tags/rel_9/sim/rtl_sim/bin/sim_file_list (nonexistent)
@@ -1,7 +0,0 @@
-clkrst.v
-gpio_mon.v
-wb_master.v
-tb_tasks.v
-tb_top.v
-
-
tags/rel_9/sim/rtl_sim/bin/sim_file_list
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tags/rel_9/sim/rtl_sim/bin/INCA_libs/worklib/inca.linux.138.pak
===================================================================
--- tags/rel_9/sim/rtl_sim/bin/INCA_libs/worklib/inca.linux.138.pak (revision 46)
+++ tags/rel_9/sim/rtl_sim/bin/INCA_libs/worklib/inca.linux.138.pak (nonexistent)
@@ -1,3216 +0,0 @@
-çíïé”ÓµëòìôÌÈÀçéíõûý„æ‚Û€ÙÜÞÕÙ›ÚÞÖÌ•Ž†‘¶²¶Éÿ ê¥ÃjDk X° =J%W