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Rev 47 → Rev 46

/trunk/bench/verilog/gpio_testbench.v File deleted
/trunk/bench/verilog/tb_top.v
0,0 → 1,167
//////////////////////////////////////////////////////////////////////
//// ////
//// GPIO Testbench Top ////
//// ////
//// This file is part of the GPIO project ////
//// http://www.opencores.org/cores/gpio/ ////
//// ////
//// Description ////
//// Top level of testbench. It instantiates all blocks. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2003/11/10 23:23:57 gorand
// tests passed.
//
// Revision 1.3 2002/03/13 20:56:16 lampret
// Removed zero padding as per Avi Shamli suggestion.
//
// Revision 1.2 2001/09/18 15:43:28 lampret
// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v.
//
// Revision 1.1 2001/08/21 21:39:27 lampret
// Changed directory structure, port names and drfines.
//
// Revision 1.2 2001/07/14 20:37:24 lampret
// Test bench improvements.
//
// Revision 1.1 2001/06/05 07:45:22 lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
 
`include "timescale.v"
`include "gpio_defines.v"
 
module tb_top();
 
parameter aw = `GPIO_ADDRHH+1 ;
parameter dw = 32;
parameter gw = `GPIO_IOS;
 
//
// Interconnect wires
//
wire clk; // Clock
wire rst; // Reset
wire cyc; // Cycle valid
wire [aw-1:0] adr; // Address bus
wire [dw-1:0] dat_m; // Data bus from PTC to WBM
wire [3:0] sel; // Data selects
wire we; // Write enable
wire stb; // Strobe
wire [dw-1:0] dat_ptc;// Data bus from WBM to PTC
wire ack; // Successful cycle termination
wire err; // Failed cycle termination
wire [gw-1:0] gpio_aux; // GPIO auxiliary signals
wire [gw-1:0] gpio_in; // GPIO inputs
wire gpio_eclk; // GPIO external clock
wire [gw-1:0] gpio_out; // GPIO outputs
wire [gw-1:0] gpio_oen; // GPIO output enables
wire [ 3 : 0 ] tag_o ;
 
//
// Instantiation of Clock/Reset Generator
//
clkrst clkrst(
// Clock
.clk_o(clk),
// Reset
.rst_o(rst)
);
 
//
// Instantiation of Master WISHBONE BFM
//
wb_master wb_master(
// WISHBONE Interface
.CLK_I(clk),
.RST_I(rst),
.CYC_O(cyc),
.ADR_O(adr),
.DAT_O(dat_ptc),
.SEL_O(sel),
.WE_O(we),
.STB_O(stb),
.DAT_I(dat_m),
.ACK_I(ack),
.ERR_I(err),
.RTY_I(1'b0),
.TAG_I(4'b0),
.TAG_O ( tag_o )
);
 
//
// Instantiation of PTC core
//
gpio_top gpio_top(
// WISHBONE Interface
.wb_clk_i(clk),
.wb_rst_i(rst),
.wb_cyc_i(cyc),
.wb_adr_i(adr),
.wb_dat_i(dat_ptc),
.wb_sel_i(sel),
.wb_we_i(we),
.wb_stb_i(stb),
.wb_dat_o(dat_m),
.wb_ack_o(ack),
.wb_err_o(err),
.wb_inta_o(),
 
// Auxiliary inputs interface
.aux_i(gpio_aux),
 
// External GPIO Interface
.ext_pad_i(gpio_in),
.clk_pad_i(gpio_eclk),
.ext_pad_o(gpio_out),
.ext_padoen_o(gpio_oen)
);
 
//
// GPIO Monitor
//
gpio_mon gpio_mon(
.gpio_aux(gpio_aux),
.gpio_in(gpio_in),
.gpio_eclk(gpio_eclk),
.gpio_out(gpio_out),
.gpio_oen(gpio_oen)
);
 
endmodule
/trunk/bench/verilog/tb_tasks.v
44,9 → 44,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2003/11/19 14:22:43 gorand
// small changes, to satisfy VATS..
//
// Revision 1.7 2003/11/10 23:23:57 gorand
// tests passed.
//
108,12 → 105,12
reg [ 31:0 ] addr ;
begin
addr = `GPIO_RGPIO_OUT <<sh_addr ;
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111);
#100 tb_top.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111);
/* $display ( " addr : %h %h", addr, val ) ;
$display ( " out_pad : %h ", gpio_testbench.gpio_top.out_pad ) ;
$display ( " rgpio_aux : %h ", gpio_testbench.gpio_top.rgpio_aux) ;
$display ( " aux_i : %h ", gpio_testbench.gpio_top.aux_i ) ;
$display ( " rgpio_out : %h ", gpio_testbench.gpio_top.rgpio_out ) ;
$display ( " out_pad : %h ", tb_top.gpio_top.out_pad ) ;
$display ( " rgpio_aux : %h ", tb_top.gpio_top.rgpio_aux) ;
$display ( " aux_i : %h ", tb_top.gpio_top.aux_i ) ;
$display ( " rgpio_out : %h ", tb_top.gpio_top.rgpio_out ) ;
*/
end
 
126,7 → 123,7
input [31:0] val;
 
begin
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_OE<<sh_addr, val, 4'b1111);
#100 tb_top.wb_master.wr(`GPIO_RGPIO_OE<<sh_addr, val, 4'b1111);
end
 
endtask
138,7 → 135,7
input [31:0] val;
 
begin
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_INTE<<sh_addr, val, 4'b1111);
#100 tb_top.wb_master.wr(`GPIO_RGPIO_INTE<<sh_addr, val, 4'b1111);
end
 
endtask
150,7 → 147,7
input [31:0] val;
 
begin
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_PTRIG<<sh_addr, val, 4'b1111);
#100 tb_top.wb_master.wr(`GPIO_RGPIO_PTRIG<<sh_addr, val, 4'b1111);
end
 
endtask
162,7 → 159,7
input [31:0] val;
 
begin
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111);
#100 tb_top.wb_master.wr(`GPIO_RGPIO_AUX<<sh_addr, val, 4'b1111);
end
 
endtask
174,7 → 171,7
input [31:0] val;
 
begin
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_CTRL<<sh_addr, val, 4'b1111);
#100 tb_top.wb_master.wr(`GPIO_RGPIO_CTRL<<sh_addr, val, 4'b1111);
end
 
endtask
186,7 → 183,7
input [31:0] val;
 
begin
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_INTS<<sh_addr, val, 4'b1111);
#100 tb_top.wb_master.wr(`GPIO_RGPIO_INTS<<sh_addr, val, 4'b1111);
end
 
endtask
198,7 → 195,7
 
reg [31:0] tmp;
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
$write(" RGPIO_IN: %h", tmp);
end
 
211,7 → 208,7
 
reg [31:0] tmp;
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
$write(" RGPIO_OUT: %h", tmp);
end
 
225,7 → 222,7
 
reg [31:0] tmp;
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
$write(" RGPIO_OE:%h", tmp);
end
 
238,7 → 235,7
 
reg [31:0] tmp;
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
$write(" RGPIO_INTE:%h", tmp);
end
 
251,7 → 248,7
 
reg [31:0] tmp;
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
$write(" RGPIO_PTRIG:%h", tmp);
end
 
264,7 → 261,7
 
reg [31:0] tmp;
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
$write(" RGPIO_AUX:%h", tmp);
end
 
277,7 → 274,7
 
reg [31:0] tmp;
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
$write(" RGPIO_CTRL: %h", tmp);
end
 
290,7 → 287,7
 
reg [31:0] tmp;
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp);
$write(" RGPIO_INTS:%h", tmp);
end
 
306,7 → 303,7
reg [31:0] tmp;
reg ret;
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
 
if (tmp == val)
ret = 1;
323,7 → 320,7
output [31:0] tmp;
 
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_IN<<sh_addr, tmp);
end
 
endtask
335,7 → 332,7
output [31:0] tmp;
 
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_OUT<<sh_addr, tmp);
end
 
endtask
347,7 → 344,7
output [31:0] tmp;
 
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_OE<<sh_addr, tmp);
end
 
endtask
359,7 → 356,7
output [31:0] tmp;
 
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTE<<sh_addr, tmp);
end
 
endtask
371,7 → 368,7
output [31:0] tmp;
 
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_PTRIG<<sh_addr, tmp);
end
 
endtask
383,7 → 380,7
output [31:0] tmp;
 
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_AUX<<sh_addr, tmp);
end
 
endtask
395,7 → 392,7
output [31:0] tmp;
 
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_CTRL<<sh_addr, tmp);
end
 
endtask
407,7 → 404,7
output [31:0] tmp;
 
begin
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp);
#100 tb_top.wb_master.rd(`GPIO_RGPIO_INTS<<sh_addr, tmp);
end
 
endtask
433,9 → 430,9
begin
 
// Set external clock to low state
gpio_testbench.gpio_mon.set_gpioeclk(0);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
tb_top.gpio_mon.set_gpioeclk(0);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
//
// Phase 1
445,14 → 442,14
 
// Put something on gpio_in pins
random_gpio(r1);
gpio_testbench.gpio_mon.set_gpioin(r1);
tb_top.gpio_mon.set_gpioin(r1);
 
// Reset GPIO_CTRL
setctrl(0);
 
// Wait for time to advance
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Read GPIO_RGPIO_IN
getin(l1);
468,15 → 465,15
 
// Put something else on gpio_in pins
random_gpio(r2);
gpio_testbench.gpio_mon.set_gpioin(r2);
tb_top.gpio_mon.set_gpioin(r2);
 
// Make an external posedge clock pulse
gpio_testbench.gpio_mon.set_gpioeclk(0);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
gpio_testbench.gpio_mon.set_gpioeclk(1);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
tb_top.gpio_mon.set_gpioeclk(0);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
tb_top.gpio_mon.set_gpioeclk(1);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Read RGPIO_IN
getin(l2);
490,11 → 487,11
 
// Put something else on gpio_in pins
random_gpio(r3);
gpio_testbench.gpio_mon.set_gpioin(r3);
tb_top.gpio_mon.set_gpioin(r3);
 
// Wait for WB clock
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Read RGPIO_IN
getin(l3);
525,9 → 522,9
//
 
// Set external clock to low state
gpio_testbench.gpio_mon.set_gpioeclk(0);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
tb_top.gpio_mon.set_gpioeclk(0);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Set GPIO to use external clock and set RGPIO_CTRL[NEC]
setctrl(1 << `GPIO_RGPIO_CTRL_ECLK | 1 << `GPIO_RGPIO_CTRL_NEC);
534,38 → 531,38
 
// Put random on gpio inputs
random_gpio(r1);
gpio_testbench.gpio_mon.set_gpioin(r1);
tb_top.gpio_mon.set_gpioin(r1);
 
// Advance time by making an external negedge clock pulse
gpio_testbench.gpio_mon.set_gpioeclk(1);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
gpio_testbench.gpio_mon.set_gpioeclk(0);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
tb_top.gpio_mon.set_gpioeclk(1);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
tb_top.gpio_mon.set_gpioeclk(0);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Put something on gpio_in pins
random_gpio(r2);
gpio_testbench.gpio_mon.set_gpioin(r2);
tb_top.gpio_mon.set_gpioin(r2);
 
// Make an external posedge clock pulse
gpio_testbench.gpio_mon.set_gpioeclk(0);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
gpio_testbench.gpio_mon.set_gpioeclk(1);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
tb_top.gpio_mon.set_gpioeclk(0);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
tb_top.gpio_mon.set_gpioeclk(1);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Read RGPIO_IN (should be the same as r1)
getin(l1);
 
// Make an external negedge clock pulse
gpio_testbench.gpio_mon.set_gpioeclk(1);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
gpio_testbench.gpio_mon.set_gpioeclk(0);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
tb_top.gpio_mon.set_gpioeclk(1);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
tb_top.gpio_mon.set_gpioeclk(0);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Read RGPIO_IN (should be the same as r2)
getin(l2);
605,11 → 602,11
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
// Put something on gpio_in pins
random_gpio(l1);
gpio_testbench.gpio_mon.set_gpioin(l1);
tb_top.gpio_mon.set_gpioin(l1);
 
// Advance time
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Read GPIO_RGPIO_IN
getin(l2);
643,11 → 640,11
setout(l1);
 
// Advance time
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Read gpio_out
gpio_testbench.gpio_mon.get_gpioout(l2);
tb_top.gpio_mon.get_gpioout(l2);
 
// Compare gpio_out and RGPIO_OUT. Should be equal.
if (l1 != l2)
678,11 → 675,11
setoe(l1);
 
// Advance time
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Read gpio_oen
gpio_testbench.gpio_mon.get_gpiooen(l2);
tb_top.gpio_mon.get_gpiooen(l2);
 
// Compare gpio_oen and RGPIO_OE. Should be exactly opposite.
if (l1 != ~l2)
710,7 → 707,7
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin
// Put something on gpio_aux pins
l1 = $random;
gpio_testbench.gpio_mon.set_gpioaux(l1);
tb_top.gpio_mon.set_gpioaux(l1);
 
// Put something in RGPIO_AUX pins
l2 = $random;
721,11 → 718,11
setout(l3);
 
// Advance time
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Read gpio_out
gpio_testbench.gpio_mon.get_gpioout(l4);
tb_top.gpio_mon.get_gpioout(l4);
 
// Compare gpio_out, RGPIO_OUT, RGPIO_AUX and gpio_aux.
// RGPIO_AUX specifies which gpio_aux bits and RGPIO_OUT
771,7 → 768,7
 
// Set gpio_in pins
r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
gpio_testbench.gpio_mon.set_gpioin(r1);
tb_top.gpio_mon.set_gpioin(r1);
 
// Low level triggering
setptrig(0);
786,32 → 783,32
setinte(r1);
 
// Advance time
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Sample interrupt request. Should be zero.
l1 = gpio_testbench.gpio_top.wb_inta_o;
l1 = tb_top.gpio_top.wb_inta_o;
 
// Clear gpio_in pins
gpio_testbench.gpio_mon.set_gpioin(0);
tb_top.gpio_mon.set_gpioin(0);
 
// Advance time
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Sample interrupt request. Should be one.
l2 = gpio_testbench.gpio_top.wb_inta_o;
l2 = tb_top.gpio_top.wb_inta_o;
 
// Clear interrupt request
setctrl(0);
 
// Advance time
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Sample interrupt request. Should be zero.
l3 = gpio_testbench.gpio_top.wb_inta_o;
l3 = tb_top.gpio_top.wb_inta_o;
 
// Get RGPIO_INTS. Should be nonzero.
getints(l4);
862,7 → 859,7
r1 = ((1<<`GPIO_IOS)-1) & 'hffffffff;
 
// Set gpio_in pins
gpio_testbench.gpio_mon.set_gpioin('h00000000);
tb_top.gpio_mon.set_gpioin('h00000000);
 
// Clear old interrupts
setints(0);
877,22 → 874,22
setinte(r1);
 
// Advance time
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Sample interrupt request. Should be zero.
l1 = gpio_testbench.gpio_top.wb_inta_o;
l1 = tb_top.gpio_top.wb_inta_o;
 
// Clear gpio_in pins
gpio_testbench.gpio_mon.set_gpioin('hffffffff);
tb_top.gpio_mon.set_gpioin('hffffffff);
 
// Advance time
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Sample interrupt request. Should be one.
l2 = gpio_testbench.gpio_top.wb_inta_o;
l2 = tb_top.gpio_top.wb_inta_o;
 
// Clear interrupt request
setctrl(0);
899,11 → 896,11
setints(0);
 
// Advance time
@(posedge gpio_testbench.clk);
@(posedge gpio_testbench.clk);
@(posedge tb_top.clk);
@(posedge tb_top.clk);
 
// Sample interrupt request. Should be zero.
l3 = gpio_testbench.gpio_top.wb_inta_o;
l3 = tb_top.gpio_top.wb_inta_o;
 
// Check for errors
if (l1 || !l2 || l3)
927,7 → 924,7
//
// Do continues check for interrupts
//
always @(posedge gpio_testbench.gpio_top.wb_inta_o)
always @(posedge tb_top.gpio_top.wb_inta_o)
if (ints_disabled) begin
$display("Spurious interrupt detected. ");
failed;
941,15 → 938,15
integer i;
initial begin
`ifdef GPIO_DUMP_VCD
$dumpfile("../out/gpio_testbench.vcd");
$dumpfile("../out/tb_top.vcd");
$dumpvars(0);
`endif
nr_failed = 0;
ints_disabled = 1;
ints_working = 0;
gpio_testbench.gpio_mon.set_gpioin(0);
gpio_testbench.gpio_mon.set_gpioaux(0);
gpio_testbench.gpio_mon.set_gpioeclk(0);
tb_top.gpio_mon.set_gpioin(0);
tb_top.gpio_mon.set_gpioaux(0);
tb_top.gpio_mon.set_gpioeclk(0);
$display;
$display("###");
$display("### GPIO IP Core Verification ###");

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