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URL https://opencores.org/ocsvn/gpio/gpio/trunk

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Rev 55 → Rev 54

/tags/rel_12/doc/gpio_spec.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/tags/rel_12/doc/gpio_spec.pdf
tags/rel_12/doc/gpio_spec.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: tags/rel_12/doc/src/gpio_spec.doc =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/rel_12/doc/src/gpio_spec.doc =================================================================== --- tags/rel_12/doc/src/gpio_spec.doc (revision 55) +++ tags/rel_12/doc/src/gpio_spec.doc (nonexistent)
tags/rel_12/doc/src/gpio_spec.doc Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: tags/rel_12/sim/rtl_sim/bin/sim.sh =================================================================== --- tags/rel_12/sim/rtl_sim/bin/sim.sh (revision 55) +++ tags/rel_12/sim/rtl_sim/bin/sim.sh (nonexistent) @@ -1,125 +0,0 @@ -#!/bin/bash - -# -# This script runs RTL and gate-level simulation using different simultion tools. -# Right now Cadence Verilog-XL and NCSim are supported. -# -# Author: Damjan Lampret -# - -# -# User definitions -# - -# Set simulation tool you are using (xl, ncsim, ncver) -SIMTOOL=ncsim - -# Set test bench top module(s) -TB_TOP="tb_tasks" - -# Set include directories -INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/" - -# Set test bench files -BENCH_FILES="../../../bench/verilog/*.v" - -# Set RTL source files -RTL_FILES="../../../rtl/verilog/*.v" - -# Set gate-level netlist files -GATE_FILES="../syn/out/final_gpio.v" - -# Set libraries (standard cell etc.) -LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v" - -# Set parameters for simulation tool -if [ $SIMTOOL == xl ]; then - PARAM="+turbo+3 -q" - for i in $INCLUDE_DIRS; do - INCDIR=$INCDIR" +incdir+$i" - done -elif [ $SIMTOOL == ncver ]; then - NCVER_PARAM="" - for i in $INCLUDE_DIRS; do - INCDIR=$INCDIR" +incdir+$i" - done -elif [ $SIMTOOL == ncsim ]; then - NCPREP_PARAM="-UPDATE +overwrite" - NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT" - for i in $INCLUDE_DIRS; do - INCDIR=$INCDIR" +incdir+$i" - done -else - echo "$SIMTOOL is unsupported simulation tool." - exit 0 -fi - -# -# Don't change anything below unless you know what you are doing -# - -# Run simulation in sim directory -#cd ../sim - -# Run actual simulation - -# Cadence Verilog-XL -if [ $SIMTOOL == xl ]; then - - # RTL simulation - if [ "$1" == rtl ]; then - verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES - - # Gate-level simulation - elif [ "$1" == gate ]; then - verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES - - # Wrong parameter or no parameter - else - echo "Usage: $0 [rtl|gate]" - exit 0 - fi - -# Cadence Ncverilog -elif [ $SIMTOOL == ncver ]; then - - # RTL simulation - if [ "$1" == rtl ]; then - ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES - cp ncverilog.log ../log - - # Gate-level simulation - elif [ "$1" == gate ]; then - ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES - cp ncverilog.log ../log - - # Wrong parameter or no parameter - else - echo "Usage: $0 [rtl|gate]" - exit 0 - fi - -# Cadence Ncsim -elif [ $SIMTOOL == ncsim ]; then - - # RTL simulation - if [ "$1" == rtl ]; then - ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES - ./RUN_NC - - # Gate-level simulation - elif [ "$1" == gate ]; then - ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES - ./RUN_NC - - # Wrong parameter or no parameter - else - echo "Usage: $0 [rtl|gate]" - exit 0 - fi - -# Unsupported simulation tool -else - echo "$SIMTOOL is unsupported simulation tool." - exit 0; -fi
tags/rel_12/sim/rtl_sim/bin/sim.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: tags/rel_12/sim/rtl_sim/bin/sim_file_list =================================================================== --- tags/rel_12/sim/rtl_sim/bin/sim_file_list (revision 55) +++ tags/rel_12/sim/rtl_sim/bin/sim_file_list (nonexistent) @@ -1,7 +0,0 @@ -clkrst.v -gpio_mon.v -wb_master.v -tb_tasks.v -gpio_testbench.v - -
tags/rel_12/sim/rtl_sim/bin/sim_file_list Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: tags/rel_12/sim/rtl_sim/bin/rtl_file_list =================================================================== --- tags/rel_12/sim/rtl_sim/bin/rtl_file_list (revision 55) +++ tags/rel_12/sim/rtl_sim/bin/rtl_file_list (nonexistent) @@ -1 +0,0 @@ -gpio_top.v
tags/rel_12/sim/rtl_sim/bin/rtl_file_list Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: tags/rel_12/sim/rtl_sim/bin/cds.lib =================================================================== --- tags/rel_12/sim/rtl_sim/bin/cds.lib (revision 55) +++ tags/rel_12/sim/rtl_sim/bin/cds.lib (nonexistent) @@ -1,6 +0,0 @@ -# -# cds.lib: Defines the locations of compiled libraries. -# Created by ncprep on Tue Nov 11 00:24:06 2003 -# - -define worklib ./INCA_libs/worklib Index: tags/rel_12/sim/rtl_sim/bin/hdl.var =================================================================== --- tags/rel_12/sim/rtl_sim/bin/hdl.var (revision 55) +++ tags/rel_12/sim/rtl_sim/bin/hdl.var (nonexistent) @@ -1,9 +0,0 @@ -# -# hdl.var: Defines variables used by the INCA tools. -# Created by ncprep on Tue Nov 11 00:24:06 2003 -# - -softinclude $CDS_INST_DIR/tools/inca/files/hdl.var - -define LIB_MAP ( $LIB_MAP, + => worklib ) -define VIEW_MAP ( $VIEW_MAP, .v => v) Index: tags/rel_12/sim/rtl_sim/log/ncelab.log =================================================================== --- tags/rel_12/sim/rtl_sim/log/ncelab.log (revision 55) +++ tags/rel_12/sim/rtl_sim/log/ncelab.log (nonexistent) @@ -1,45 +0,0 @@ -TOOL: ncelab 04.10-b001: Started on Dec 09, 2003 at 12:18:09 -ncelab - -f ncelab.args - -MESSAGES - -NOCOPYRIGHT - -CDSLIB ../bin/cds.lib - -HDLVAR ../bin/hdl.var - -LOGFILE ../log/ncelab.log - -SNAPSHOT worklib.bench:rtl - -NO_TCHK_MSG - -ACCESS +RWC - worklib.tb_tasks - worklib.gpio_testbench - - Elaborating the design hierarchy: - Caching library 'worklib' ....... Done - Building instance overlay tables: .................... Done - Generating native compiled code: - worklib.clkrst:v <0x67faf15a> - streams: 2, words: 1034 - worklib.gpio_mon:v <0x50b5485b> - streams: 6, words: 1408 - worklib.gpio_testbench:v <0x2b2f512c> - streams: 2, words: 300 - worklib.gpio_top:v <0x2a4cd65a> - streams: 72, words: 55544 - worklib.tb_tasks:v <0x3e6d21f9> - streams: 33, words: 52966 - worklib.wb_master:v <0x2119db6d> - streams: 38, words: 21648 - Loading native compiled code: .................... Done - Building instance specific data structures. - Design hierarchy summary: - Instances Unique - Modules: 6 6 - Registers: 122 122 - Scalar wires: 23 - - Vectored wires: 14 - - Always blocks: 24 24 - Initial blocks: 3 3 - Cont. assignments: 10 17 - Pseudo assignments: 2 43 - Simulation timescale: 10ps - Writing initial simulation snapshot: worklib.bench:rtl -TOOL: ncelab 04.10-b001: Exiting on Dec 09, 2003 at 12:18:10 (total: 00:00:01) Index: tags/rel_12/sim/rtl_sim/log/ncvlog.log =================================================================== --- tags/rel_12/sim/rtl_sim/log/ncvlog.log (revision 55) +++ tags/rel_12/sim/rtl_sim/log/ncvlog.log (nonexistent) @@ -1,36 +0,0 @@ -TOOL: ncvlog 04.10-b001: Started on Dec 09, 2003 at 12:18:08 -ncvlog - -f ncvlog.args - -CDSLIB ../bin/cds.lib - -HDLVAR ../bin/hdl.var - -MESSAGES - -INCDIR ../../../bench/verilog - -INCDIR ../../../rtl/verilog - -NOCOPYRIGHT - -LOGFILE ../log/ncvlog.log - ../../../rtl/verilog/gpio_top.v - ../../../bench/verilog/clkrst.v - ../../../bench/verilog/gpio_mon.v - ../../../bench/verilog/wb_master.v - ../../../bench/verilog/tb_tasks.v - ../../../bench/verilog/gpio_testbench.v - -file: ../../../rtl/verilog/gpio_top.v - module worklib.gpio_top:v - errors: 0, warnings: 0 -file: ../../../bench/verilog/clkrst.v - module worklib.clkrst:v - errors: 0, warnings: 0 -file: ../../../bench/verilog/gpio_mon.v - module worklib.gpio_mon:v - errors: 0, warnings: 0 -file: ../../../bench/verilog/wb_master.v - module worklib.wb_master:v - errors: 0, warnings: 0 -file: ../../../bench/verilog/tb_tasks.v - module worklib.tb_tasks:v - errors: 0, warnings: 0 -file: ../../../bench/verilog/gpio_testbench.v - module worklib.gpio_testbench:v - errors: 0, warnings: 0 -TOOL: ncvlog 04.10-b001: Exiting on Dec 09, 2003 at 12:18:09 (total: 00:00:01) Index: tags/rel_12/sim/rtl_sim/log/ncsim.log =================================================================== --- tags/rel_12/sim/rtl_sim/log/ncsim.log (revision 55) +++ tags/rel_12/sim/rtl_sim/log/ncsim.log (nonexistent) @@ -1,43 +0,0 @@ -TOOL: ncsim 04.10-b001: Started on Dec 09, 2003 at 12:18:10 -ncsim - -LICQUEUE - -f ./ncsim.args - -MESSAGES - -NOCOPYRIGHT - -CDSLIB ../bin/cds.lib - -HDLVAR ../bin/hdl.var - -INPUT ncsim.tcl - -LOGFILE ../log/ncsim.log - worklib.bench:rtl - -Loading snapshot worklib.bench:rtl .................... Done -ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc -ncsim> run - -### -### GPIO IP Core Verification ### -### - -I. Testing correct operation of RGPIO_CTRL control bits - - Testing control bit RGPIO_CTRL[ECLK] ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... OK - Testing control bit RGPIO_CTRL[NEC] ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... OK - Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ... OK - -II. Testing modes of operation ... - - Testing input mode ... OK - Testing output mode ... OK - Testing bidirectional I/O ... OK - Testing auxiliary feature ... OK - Testing ptrig features ... OK - -### -### FAILED TESTS: 0 ### -### - -report (deaddead) -exit (00000000) -/projects/highland/gorand/gpio/bench/verilog/tb_tasks.v:1009 $finish(0); -ncsim> quit -TOOL: ncsim 04.10-b001: Exiting on Dec 09, 2003 at 12:21:32 (total: 00:03:22) Index: tags/rel_12/sim/rtl_sim/run/ncelab.args =================================================================== --- tags/rel_12/sim/rtl_sim/run/ncelab.args (revision 55) +++ tags/rel_12/sim/rtl_sim/run/ncelab.args (nonexistent) @@ -1,10 +0,0 @@ --MESSAGES --NOCOPYRIGHT --CDSLIB ../bin/cds.lib --HDLVAR ../bin/hdl.var --LOGFILE ../log/ncelab.log --SNAPSHOT worklib.bench:rtl --NO_TCHK_MSG --ACCESS +RWC -worklib.tb_tasks -worklib.gpio_testbench Index: tags/rel_12/sim/rtl_sim/run/ncvlog.args =================================================================== --- tags/rel_12/sim/rtl_sim/run/ncvlog.args (revision 55) +++ tags/rel_12/sim/rtl_sim/run/ncvlog.args (nonexistent) @@ -1,13 +0,0 @@ --CDSLIB ../bin/cds.lib --HDLVAR ../bin/hdl.var --MESSAGES --INCDIR ../../../bench/verilog --INCDIR ../../../rtl/verilog --NOCOPYRIGHT --LOGFILE ../log/ncvlog.log -../../../rtl/verilog/gpio_top.v -../../../bench/verilog/clkrst.v -../../../bench/verilog/gpio_mon.v -../../../bench/verilog/wb_master.v -../../../bench/verilog/tb_tasks.v -../../../bench/verilog/gpio_testbench.v Index: tags/rel_12/sim/rtl_sim/run/ncsim.args =================================================================== --- tags/rel_12/sim/rtl_sim/run/ncsim.args (revision 55) +++ tags/rel_12/sim/rtl_sim/run/ncsim.args (nonexistent) @@ -1,7 +0,0 @@ --MESSAGES --NOCOPYRIGHT --CDSLIB ../bin/cds.lib --HDLVAR ../bin/hdl.var --INPUT ncsim.tcl --LOGFILE ../log/ncsim.log -worklib.bench:rtl Index: tags/rel_12/sim/rtl_sim/run/ncsim.tcl =================================================================== --- tags/rel_12/sim/rtl_sim/run/ncsim.tcl (revision 55) +++ tags/rel_12/sim/rtl_sim/run/ncsim.tcl (nonexistent) @@ -1,2 +0,0 @@ -run -quit Index: tags/rel_12/sim/rtl_sim/run/run_sim_gpio =================================================================== --- tags/rel_12/sim/rtl_sim/run/run_sim_gpio (revision 55) +++ tags/rel_12/sim/rtl_sim/run/run_sim_gpio (nonexistent) @@ -1,102 +0,0 @@ -#!/bin/csh -f - -if ( $# < 1 ) then - echo "First argument must be a top level module name!" - exit -else - set SIM_TOP = $1 -endif - -set current_par = 1 -set output_waveform = 0 -while ( $current_par < $# ) - @ current_par = $current_par + 1 - case wave: - @ output_waveform = 1 - breaksw - default: - echo 'Unknown option "'$argv[$current_par]'"!' - exit - breaksw - endsw -end - -echo "-CDSLIB ../bin/cds.lib" > ncvlog.args -echo "-HDLVAR ../bin/hdl.var" >> ncvlog.args -echo "-MESSAGES" >> ncvlog.args -echo "-INCDIR ../../../bench/verilog" >> ncvlog.args -echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args -echo "-NOCOPYRIGHT" >> ncvlog.args -echo "-LOGFILE ../log/ncvlog.log" >> ncvlog.args - -foreach filename ( `cat ../bin/rtl_file_list` ) - echo "../../../rtl/verilog/"$filename >> ncvlog.args -end - -foreach filename ( `cat ../bin/sim_file_list` ) - echo "../../../bench/verilog/"$filename >> ncvlog.args -end - -ncvlog -f ncvlog.args - -echo "-MESSAGES" > ncelab.args -echo "-NOCOPYRIGHT" >> ncelab.args -echo "-CDSLIB ../bin/cds.lib" >> ncelab.args -echo "-HDLVAR ../bin/hdl.var" >> ncelab.args -echo "-LOGFILE ../log/ncelab.log" >> ncelab.args -echo "-SNAPSHOT worklib.bench:rtl" >> ncelab.args -echo "-NO_TCHK_MSG" >> ncelab.args -echo "-ACCESS +RWC" >> ncelab.args -echo "worklib.tb_tasks" >> ncelab.args -echo worklib.$SIM_TOP >> ncelab.args - -ncelab -f ncelab.args - -echo "-MESSAGES" > ncsim.args -echo "-NOCOPYRIGHT" >> ncsim.args -echo "-CDSLIB ../bin/cds.lib" >> ncsim.args -echo "-HDLVAR ../bin/hdl.var" >> ncsim.args -echo "-INPUT ncsim.tcl" >> ncsim.args -echo "-LOGFILE ../log/ncsim.log" >> ncsim.args -echo "worklib.bench:rtl" >> ncsim.args - -if ( $output_waveform ) then - echo "database -open waves -shm -into ../out/waves.shm" > ./ncsim.tcl - echo "probe -create -database waves $SIM_TOP -shm -all -depth all" >> ./ncsim.tcl - echo "run" >> ./ncsim.tcl -else - echo "run" > ./ncsim.tcl -endif - -echo "quit" >> ncsim.tcl - -ncsim -LICQUEUE -f ./ncsim.args - -set exit_line_nb = `sed -n '/exit/=' < ../log/ncsim.log` - -#echo "$exit_line_nb" - -set dead_line_nb = 0 - -if ( $exit_line_nb ) then - - @ dead_line_nb = $exit_line_nb - 1 - set exit_line=`sed -n $exit_line_nb's/exit/&/gp' < ../log/ncsim.log` - set dead_line=`sed -n $dead_line_nb's/report/&/gp' < ../log/ncsim.log` - - echo "$dead_line" - echo "$exit_line" - - echo "TEST: gpio" - if ( "$dead_line" == "report (deaddead)" ) then - if ( "$exit_line" == "exit (00000000)" ) then - echo "STATUS: passed" #|tee -a ../log/run_sim.log 2>&1 - else - echo "STATUS: failed" #|tee -a ../log/run_sim.log 2>&1 - endif - else - echo "STATUS: failed" - endif - -endif -
tags/rel_12/sim/rtl_sim/run/run_sim_gpio Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: tags/rel_12/sim/rtl_sim/run/run_sim =================================================================== --- tags/rel_12/sim/rtl_sim/run/run_sim (revision 55) +++ tags/rel_12/sim/rtl_sim/run/run_sim (nonexistent) @@ -1,3 +0,0 @@ -#!/bin/sh -./run_sim_gpio gpio_testbench -
tags/rel_12/sim/rtl_sim/run/run_sim Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: tags/rel_12/syn/run/dodesign =================================================================== --- tags/rel_12/syn/run/dodesign (revision 55) +++ tags/rel_12/syn/run/dodesign (nonexistent) @@ -1,5 +0,0 @@ -#!/bin/sh -f - -# nohup dc_shell -f ../bin/top.scr | tee ../log/top.log -dc_shell -f ../bin/top_gpio.scr > ../log/top_gpio.log -mv command.log ../log
tags/rel_12/syn/run/dodesign Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: tags/rel_12/syn/bin/cons_art_umc18.inc =================================================================== --- tags/rel_12/syn/bin/cons_art_umc18.inc (revision 55) +++ tags/rel_12/syn/bin/cons_art_umc18.inc (nonexistent) @@ -1,51 +0,0 @@ -/* Constraints */ -CLK_UNCERTAINTY = 0.1 /* 100 ps */ -DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */ -DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */ - -/* Clocks constraints */ -create_clock CLK -period CLK_PERIOD -create_clock ECLK -period CLK_PERIOD -set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY -set_dont_touch_network all_clocks() - -/* Reset constraints */ -set_driving_cell -none RST -set_drive 0 RST -set_dont_touch_network RST - -/* All inputs except reset and clock */ -all_inputs_wo_rst_clk = all_inputs() - CLK - RST - -/* Set output delays and load for output signals - * - * All outputs are assumed to go directly into - * external flip-flops for the purpose of this - * synthesis - */ -set_output_delay DFFHQX2_SETUP -clock CLK all_outputs() -set_load load_of(typical/DFFHQX2/D) * 1 all_outputs() - -/* Input delay and driving cell of all inputs - * - * All these signals are assumed to come directly from - * flip-flops for the purpose of this synthesis - * - */ -set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk -set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk - -/* Set design fanout */ -/* -set_max_fanout 10 TOPLEVEL -*/ - -/* Set area constraint */ -set_max_area MAX_AREA - -/* Optimize all near-critical paths to give extra slack for layout */ -c_range = CLK_PERIOD * 0.05 -group_path -critical_range c_range -name CLK -to CLK - -/* Operating conditions */ -set_operating_conditions typical Index: tags/rel_12/syn/bin/tech_art_umc18.inc =================================================================== --- tags/rel_12/syn/bin/tech_art_umc18.inc (revision 55) +++ tags/rel_12/syn/bin/tech_art_umc18.inc (nonexistent) @@ -1,17 +0,0 @@ -/* Set Artisan Sage-X UMC 0.18u standard cell library */ - -search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \ - { /libs/Artisan/aci/sc-x/symbols/synopsys/ } -snps = get_unix_variable("SYNOPSYS") -synthetic_library = { \ - snps + "/libraries/syn/dw01.sldb" \ - snps + "/libraries/syn/dw02.sldb" \ - snps + "/libraries/syn/dw03.sldb" \ - snps + "/libraries/syn/dw04.sldb" \ - snps + "/libraries/syn/dw05.sldb" \ - snps + "/libraries/syn/dw06.sldb" \ - snps + "/libraries/syn/dw07.sldb" } -target_library = { typical.db } -link_library = target_library + synthetic_library -symbol_library = { umc18.sdb } - Index: tags/rel_12/syn/bin/cons_vs_umc18.inc =================================================================== --- tags/rel_12/syn/bin/cons_vs_umc18.inc (revision 55) +++ tags/rel_12/syn/bin/cons_vs_umc18.inc (nonexistent) @@ -1,51 +0,0 @@ -/* Constraints */ -CLK_UNCERTAINTY = 0.1 /* 100 ps */ -DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */ -DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */ - -/* Clocks constraints */ -create_clock CLK -period CLK_PERIOD -create_clock ECLK -period CLK_PERIOD -set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY -set_dont_touch_network all_clocks() - -/* Reset constraints */ -set_driving_cell -none RST -set_drive 0 RST -set_dont_touch_network RST - -/* All inputs except reset and clock */ -all_inputs_wo_rst_clk = all_inputs() - CLK - RST - -/* Set output delays and load for output signals - * - * All outputs are assumed to go directly into - * external flip-flops for the purpose of this - * synthesis - */ -set_output_delay DFFPQ2_SETUP -clock CLK all_outputs() -set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs() - -/* Input delay and driving cell of all inputs - * - * All these signals are assumed to come directly from - * flip-flops for the purpose of this synthesis - * - */ -set_input_delay DFFPQ2_CKQ -clock CLK all_inputs_wo_rst_clk -set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk - -/* Set design fanout */ -/* -set_max_fanout 10 TOPLEVEL -*/ - -/* Set area constraint */ -set_max_area MAX_AREA - -/* Optimize all near-critical paths to give extra slack for layout */ -c_range = CLK_PERIOD * 0.1 -group_path -critical_range c_range -name CLK -to CLK - -/* Operating conditions */ -set_operating_conditions TYPICAL Index: tags/rel_12/syn/bin/save_design.inc =================================================================== --- tags/rel_12/syn/bin/save_design.inc (revision 55) +++ tags/rel_12/syn/bin/save_design.inc (nonexistent) @@ -1,5 +0,0 @@ -/* Save current design using synopsys format */ -write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db - -/* Save current design using verilog format */ -write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v Index: tags/rel_12/syn/bin/tech_vs_umc18.inc =================================================================== --- tags/rel_12/syn/bin/tech_vs_umc18.inc (revision 55) +++ tags/rel_12/syn/bin/tech_vs_umc18.inc (nonexistent) @@ -1,16 +0,0 @@ -/* Set Virtual Silicon UMC 0.18u standard cell library */ - -search_path = {. /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ } -snps = get_unix_variable("SYNOPSYS") -synthetic_library = { \ - snps + "/libraries/syn/dw01.sldb" \ - snps + "/libraries/syn/dw02.sldb" \ - snps + "/libraries/syn/dw03.sldb" \ - snps + "/libraries/syn/dw04.sldb" \ - snps + "/libraries/syn/dw05.sldb" \ - snps + "/libraries/syn/dw06.sldb" \ - snps + "/libraries/syn/dw07.sldb" } -target_library = { umcl18u250t2_typ.db } -link_library = target_library + synthetic_library -symbol_library = { umcl18u250t2.sdb } - Index: tags/rel_12/syn/bin/top_gpio.scr =================================================================== --- tags/rel_12/syn/bin/top_gpio.scr (revision 55) +++ tags/rel_12/syn/bin/top_gpio.scr (nonexistent) @@ -1,65 +0,0 @@ -/* - * User defines for synthesizing GPIO IP core - * - */ -TOPLEVEL = gpio -include select_tech.inc -CLK = clk_i -ECLK = gpio_eclk -RST = rst_i -CLK_PERIOD = 5 /* 200 MHz */ -MAX_AREA = 0 /* Push hard */ -DO_UNGROUP = yes /* yes, no */ -DO_VERIFY = yes /* yes, no */ - -/* Starting timestamp */ -sh date - -/* Set some basic variables related to environment */ -include set_env.inc -STAGE = final - -/* Load libraries */ -include tech_ + TECH + .inc - -/* Load HDL source files */ -include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log - -/* Set design top */ -current_design TOPLEVEL - -/* Link all blocks and uniquify them */ -link -uniquify -check_design > LOG_PATH + check_design_ + TOPLEVEL + .log - -/* Apply constraints */ -if (TECH == "vs_umc18") { - include cons_vs_umc18.inc -} else if (TECH == "art_umc18") { - include cons_art_umc18.inc -} else { - echo "Error: Unsupported technology" - exit -} - -/* Lets do basic synthesis */ -if (DO_UNGROUP == "yes") { - ungroup -all -} -compile -boundary_optimization -map_effort low - -/* Dump gate-level from incremental synthesis */ -include save_design.inc - -/* Generate reports for incremental synthesis */ -include reports.inc - -/* Verify design */ -if (DO_VERIFY == "yes") { - compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log -} - -/* Finish */ -sh date -exit Index: tags/rel_12/syn/bin/reports.inc =================================================================== --- tags/rel_12/syn/bin/reports.inc (revision 55) +++ tags/rel_12/syn/bin/reports.inc (nonexistent) @@ -1,10 +0,0 @@ -/* Basic reports */ -report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log -report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log -report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log -report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log -report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log -/* -report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log -*/ - Index: tags/rel_12/syn/bin/select_tech.inc =================================================================== --- tags/rel_12/syn/bin/select_tech.inc (revision 55) +++ tags/rel_12/syn/bin/select_tech.inc (nonexistent) @@ -1,5 +0,0 @@ -/* Defaults */ - -TECH = vs_umc18 /* vs_umc18, art_umc18 */ -CLK_PERIOD = 5 /* 200 MHz */ -MAX_AREA = 0 /* Push hard */ Index: tags/rel_12/syn/bin/set_env.inc =================================================================== --- tags/rel_12/syn/bin/set_env.inc (revision 55) +++ tags/rel_12/syn/bin/set_env.inc (nonexistent) @@ -1,18 +0,0 @@ -/* Enable Verilog HDL preprocessor */ -hdlin_enable_vpp = true - -/* Set log path */ -LOG_PATH = "../log/" - -/* Set gate-level netlist path */ -GATE_PATH = "../out/" - -/* Set RAMS_PATH */ -RAMS_PATH = "../../../lib/" - -/* Set RTL source path */ -RTL_PATH = "../../rtl/verilog/" - -/* Optimize adders */ -synlib_model_map_effort = high -hlo_share_effort = medium Index: tags/rel_12/syn/bin/read_design.inc =================================================================== --- tags/rel_12/syn/bin/read_design.inc (revision 55) +++ tags/rel_12/syn/bin/read_design.inc (nonexistent) @@ -1,11 +0,0 @@ -/* Set search path for verilog include files */ -search_path = search_path + { RTL_PATH } + { GATE_PATH } - -/* Read verilog files of the GPIO IP core */ -if (TOPLEVEL == "gpio") { - read -f verilog gpio.v -} else { - echo "Non-existing top level." - exit -} - Index: tags/rel_12/bench/verilog/gpio_testbench.v =================================================================== --- tags/rel_12/bench/verilog/gpio_testbench.v (revision 55) +++ tags/rel_12/bench/verilog/gpio_testbench.v (nonexistent) @@ -1,170 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// GPIO Testbench Top //// -//// //// -//// This file is part of the GPIO project //// -//// http://www.opencores.org/cores/gpio/ //// -//// //// -//// Description //// -//// Top level of testbench. It instantiates all blocks. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.5 2003/11/29 16:22:05 gorand -// small changes, for VATS... -// -// Revision 1.4 2003/11/10 23:23:57 gorand -// tests passed. -// -// Revision 1.3 2002/03/13 20:56:16 lampret -// Removed zero padding as per Avi Shamli suggestion. -// -// Revision 1.2 2001/09/18 15:43:28 lampret -// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v. -// -// Revision 1.1 2001/08/21 21:39:27 lampret -// Changed directory structure, port names and drfines. -// -// Revision 1.2 2001/07/14 20:37:24 lampret -// Test bench improvements. -// -// Revision 1.1 2001/06/05 07:45:22 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -`include "timescale.v" -`include "gpio_defines.v" - -module gpio_testbench(); - -parameter aw = `GPIO_ADDRHH+1 ; -parameter dw = 32; -parameter gw = `GPIO_IOS; - -// -// Interconnect wires -// -wire clk; // Clock -wire rst; // Reset -wire cyc; // Cycle valid -wire [aw-1:0] adr; // Address bus -wire [dw-1:0] dat_m; // Data bus from PTC to WBM -wire [3:0] sel; // Data selects -wire we; // Write enable -wire stb; // Strobe -wire [dw-1:0] dat_ptc;// Data bus from WBM to PTC -wire ack; // Successful cycle termination -wire err; // Failed cycle termination -wire [gw-1:0] gpio_aux; // GPIO auxiliary signals -wire [gw-1:0] gpio_in; // GPIO inputs -wire gpio_eclk; // GPIO external clock -wire [gw-1:0] gpio_out; // GPIO outputs -wire [gw-1:0] gpio_oen; // GPIO output enables -wire [ 3 : 0 ] tag_o ; - -// -// Instantiation of Clock/Reset Generator -// -clkrst clkrst( - // Clock - .clk_o(clk), - // Reset - .rst_o(rst) -); - -// -// Instantiation of Master WISHBONE BFM -// -wb_master wb_master( - // WISHBONE Interface - .CLK_I(clk), - .RST_I(rst), - .CYC_O(cyc), - .ADR_O(adr), - .DAT_O(dat_ptc), - .SEL_O(sel), - .WE_O(we), - .STB_O(stb), - .DAT_I(dat_m), - .ACK_I(ack), - .ERR_I(err), - .RTY_I(1'b0), - .TAG_I(4'b0), - .TAG_O ( tag_o ) -); - -// -// Instantiation of PTC core -// -gpio_top gpio_top( - // WISHBONE Interface - .wb_clk_i(clk), - .wb_rst_i(rst), - .wb_cyc_i(cyc), - .wb_adr_i(adr), - .wb_dat_i(dat_ptc), - .wb_sel_i(sel), - .wb_we_i(we), - .wb_stb_i(stb), - .wb_dat_o(dat_m), - .wb_ack_o(ack), - .wb_err_o(err), - .wb_inta_o(), - - // Auxiliary inputs interface - .aux_i(gpio_aux), - - // External GPIO Interface - .ext_pad_i(gpio_in), - .clk_pad_i(gpio_eclk), - .ext_pad_o(gpio_out), - .ext_padoen_o(gpio_oen) -); - -// -// GPIO Monitor -// -gpio_mon gpio_mon( - .gpio_aux(gpio_aux), - .gpio_in(gpio_in), - .gpio_eclk(gpio_eclk), - .gpio_out(gpio_out), - .gpio_oen(gpio_oen) -); - -endmodule Index: tags/rel_12/bench/verilog/clkrst.v =================================================================== --- tags/rel_12/bench/verilog/clkrst.v (revision 55) +++ tags/rel_12/bench/verilog/clkrst.v (nonexistent) @@ -1,80 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Clock and Reset Generator //// -//// //// -//// This file is part of the GPIO project //// -//// http://www.opencores.org/cores/gpio/ //// -//// //// -//// Description //// -//// Clock and reset generator. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.1 2001/06/05 07:45:21 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -`include "timescale.v" - -module clkrst(clk_o, rst_o); - -// -// I/O ports -// -output clk_o; // Clock -output rst_o; // Reset - -// -// Internal regs -// -reg clk_o; // Clock -reg rst_o; // Reset - -initial begin - clk_o = 0; - rst_o = 1; - #20; - rst_o = 0; -end - -// -// Clock -// -always #4 clk_o = ~clk_o; - -endmodule Index: tags/rel_12/bench/verilog/tb_defines.v =================================================================== --- tags/rel_12/bench/verilog/tb_defines.v (revision 55) +++ tags/rel_12/bench/verilog/tb_defines.v (nonexistent) @@ -1,76 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// GPIO Testbench Definitions //// -//// //// -//// This file is part of the GPIO project //// -//// http://www.opencores.org/cores/gpio/ //// -//// //// -//// Description //// -//// Testbench definitions that affect how testbench simulation //// -//// is performed. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.2 2001/08/21 22:01:50 lampret -// More intensive verification. -// -// Revision 1.1 2001/08/21 21:39:27 lampret -// Changed directory structure, port names and drfines. -// -// Revision 1.2 2001/07/14 20:37:23 lampret -// Test bench improvements. -// -// Revision 1.1 2001/06/05 07:45:22 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -// -// Define if you want VCD dump -// -`define GPIO_DUMP_VCD - -// -// Intensity of verification -// -// Higher number means more intensive verification. Higher number -// means more loops of each subtest (e.g. for some subtests -// 5 means 50 loops, for others 100 etc). Good numbers are from 1 -// (very fast and very little verification) to 200 (slow but thorough). -// Default is 200. -// -`define GPIO_VERIF_INTENSITY 200 Index: tags/rel_12/bench/verilog/wb_master.v =================================================================== --- tags/rel_12/bench/verilog/wb_master.v (revision 55) +++ tags/rel_12/bench/verilog/wb_master.v (nonexistent) @@ -1,308 +0,0 @@ -`include "timescale.v" -`include "gpio_defines.v" - -// -*- Mode: Verilog -*- -// Filename : wb_master.v -// Description : Wishbone Master Behavorial -// Author : Winefred Washington -// Created On : Thu Jan 11 21:18:41 2001 -// Last Modified By: . -// Last Modified On: . -// Update Count : 0 -// Status : Unknown, Use with caution! - -// Description Specification -// General Description: 8, 16, 32-bit WISHBONE Master -// Supported cycles: MASTER, READ/WRITE -// MASTER, BLOCK READ/WRITE -// MASTER, RMW -// Data port, size: 8, 16, 32-bit -// Data port, granularity 8-bit -// Data port, Max. operand size 32-bit -// Data transfer ordering: little endian -// Data transfer sequencing: undefined -// - -module wb_master(CLK_I, RST_I, TAG_I, TAG_O, - ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O); - -parameter aw = `GPIO_ADDRHH+1 ; - input CLK_I; - input RST_I; - input [3:0] TAG_I; - output [3:0] TAG_O; - input ACK_I; - output [aw-1:0] ADR_O; - output CYC_O; - input [31:0] DAT_I; - output [31:0] DAT_O; - input ERR_I; - input RTY_I; - output [3:0] SEL_O; - output STB_O; - output WE_O; - - reg [aw-1:0] ADR_O; - reg [3:0] SEL_O; - reg CYC_O; - reg STB_O; - reg WE_O; - reg [31:0] DAT_O; - - wire [15:0] mem_sizes; // determines the data width of an address range - reg [31:0] write_burst_buffer[0:7]; - reg [31:0] read_burst_buffer[0:7]; - - reg GO; - integer cycle_end; - integer address; - integer data; - integer selects; - integer write_flag; - - // - // mem_sizes determines the data widths of memory space - // The memory space is divided into eight regions. Each - // region is controlled by a two bit field. - // - // Bits - // 00 = 8 bit memory space - // 01 = 16 bit - // 10 = 32 bit - // 11 = 64 bit (not supported in this model - // - - assign mem_sizes = 16'b10_01_10_11_00_01_10_11; - - function [1:0] data_width; - input [31:0] adr; - begin - casex (adr[31:29]) - 3'b000: data_width = mem_sizes[15:14]; - 3'b001: data_width = mem_sizes[13:12]; - 3'b010: data_width = mem_sizes[11:10]; - 3'b011: data_width = mem_sizes[9:8]; - 3'b100: data_width = mem_sizes[7:6]; - 3'b101: data_width = mem_sizes[5:4]; - 3'b110: data_width = mem_sizes[3:2]; - 3'b111: data_width = mem_sizes[1:0]; - 3'bxxx: data_width = 2'bxx; - endcase // casex (adr[31:29]) - end - endfunction - - always @(posedge CLK_I or posedge RST_I) - begin - if (RST_I) - begin - GO = 1'b0; - end - end - - // read single - task rd; - input [31:0] adr; - output [31:0] result; - - begin - cycle_end = 1; - address = adr; - selects = 255; - write_flag = 0; - - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - // wait for cycle to start - while (~CYC_O) - @(posedge CLK_I); - - // wait for cycle to end - while (CYC_O) - @(posedge CLK_I); - - result = data; -// $display(" Reading %h from address %h", result, address); - - end - endtask // read - - task wr; - input [31:0] adr; - input [31:0] dat; - input [3:0] sel; - begin - cycle_end = 1; - address = adr; - selects = sel; - write_flag = 1; - data = dat; - - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - // wait for cycle to start - while (~CYC_O) - @(posedge CLK_I); - - // wait for cycle to end - while (CYC_O) - @(posedge CLK_I); -// $display(" Writing %h to address %h", data, address); - - end - endtask // wr - - // block read - task blkrd; - input [31:0] adr; - input end_flag; - output [31:0] result; - - begin - write_flag = 0; - cycle_end = end_flag; - address = adr; - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - result = data; - end - endtask // blkrd - - // block write - task blkwr; - input [31:0] adr; - input [31:0] dat; - input [3:0] sel; - input end_flag; - begin - write_flag = 1; - cycle_end = end_flag; - address = adr; - data = dat; - selects = sel; - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - end - endtask // blkwr - - // RMW - task rmw; - input [31:0] adr; - input [31:0] dat; - input [3:0] sel; - output [31:0] result; - - begin - // read phase - write_flag = 0; - cycle_end = 0; - address = adr; - GO <= 1; - @(posedge CLK_I); -// GO <= 0; - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - result = data; - - // write phase - write_flag = 1; - address = adr; - selects = sel; - GO <= 1; - data <= dat; - cycle_end <= 1; - @(posedge CLK_I); -// GO <= 0; - - while (~(ACK_I & STB_O)) - @(posedge CLK_I); - - end - endtask // rmw - - always @(posedge CLK_I) - begin - if (RST_I) - ADR_O <= 32'h0000_0000; - else - ADR_O <= address; - end - - always @(posedge CLK_I) - begin - if (RST_I | ERR_I | RTY_I) - CYC_O <= 1'b0; - else if ((cycle_end == 1) & ACK_I) - CYC_O <= 1'b0; - else if (GO | CYC_O) begin - CYC_O <= 1'b1; - GO <= 1'b0; - end - end - - // stb control - always @(posedge CLK_I) - begin - if (RST_I | ERR_I | RTY_I) - STB_O <= 1'b0; - else if (STB_O & ACK_I) - STB_O <= 1'b0; - else if (GO | STB_O) - STB_O <= 1'b1; - end - - // selects & data - always @(posedge CLK_I) - begin - if (write_flag == 0) begin - SEL_O <= 4'b1111; - if (STB_O & ACK_I) - data <= DAT_I; - end - else begin - case (data_width(address)) - 2'b00: begin - SEL_O <= {3'b000, selects[0]}; - DAT_O <= {data[7:0], data[7:0], data[7:0], data[7:0]}; - end - 2'b01: begin - SEL_O <= {2'b00, selects[1:0]}; - DAT_O <= {data[15:0], data[15:0]}; - end - 2'b10: begin - SEL_O <= selects; - DAT_O <= data; - end - endcase - end - end - - always @(posedge CLK_I) - begin - if (RST_I) - WE_O <= 1'b0; - else if (GO) - WE_O <= write_flag; - end - -endmodule - - - - - Index: tags/rel_12/bench/verilog/timescale.v =================================================================== --- tags/rel_12/bench/verilog/timescale.v (revision 55) +++ tags/rel_12/bench/verilog/timescale.v (nonexistent) @@ -1 +0,0 @@ -`timescale 1ns/10ps Index: tags/rel_12/bench/verilog/gpio_mon.v =================================================================== --- tags/rel_12/bench/verilog/gpio_mon.v (revision 55) +++ tags/rel_12/bench/verilog/gpio_mon.v (nonexistent) @@ -1,135 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// GPIO Monitor //// -//// //// -//// This file is part of the GPIO project //// -//// http://www.opencores.org/cores/gpio/ //// -//// //// -//// Description //// -//// Generates and monitors GPIO external signals (+auxiliary) //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.1 2001/08/21 21:39:27 lampret -// Changed directory structure, port names and drfines. -// -// Revision 1.2 2001/07/14 20:37:20 lampret -// Test bench improvements. -// -// Revision 1.1 2001/06/05 07:45:22 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -`include "timescale.v" -`include "gpio_defines.v" - -module gpio_mon(gpio_aux, gpio_in, gpio_eclk, gpio_out, gpio_oen); - -parameter gw = `GPIO_IOS; - -// -// I/O ports -// -output [gw-1:0] gpio_aux; // Auxiliary -output [gw-1:0] gpio_in; // GPIO inputs -output gpio_eclk; // GPIO external clock -input [gw-1:0] gpio_out; // GPIO outputs -input [gw-1:0] gpio_oen; // GPIO output enables - -// -// Internal regs -// -reg [gw-1:0] gpio_aux; -reg [gw-1:0] gpio_in; -reg gpio_eclk; - -initial gpio_eclk = 0; - -// -// Set gpio_in -// -task set_gpioin; -input [31:0] val; -begin - gpio_in = val; -end -endtask - -// -// Set gpio_aux -// -task set_gpioaux; -input [31:0] val; -begin - gpio_aux = val; -end -endtask - -// -// Set gpio_eclk -// -task set_gpioeclk; -input [31:0] val; -begin - gpio_eclk = val[0]; -end -endtask - - -// -// Get gpio_out -// -task get_gpioout; -output [31:0] val; -reg [31:0] val; -begin - val = gpio_out; -end -endtask - -// -// Get gpio_oen -// -task get_gpiooen; -output [31:0] val; -begin - val = gpio_oen; -end -endtask - -endmodule Index: tags/rel_12/bench/verilog/tb_tasks.v =================================================================== --- tags/rel_12/bench/verilog/tb_tasks.v (revision 55) +++ tags/rel_12/bench/verilog/tb_tasks.v (nonexistent) @@ -1,1010 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// GPIO Testbench Tasks //// -//// //// -//// This file is part of the GPIO project //// -//// http://www.opencores.org/cores/gpio/ //// -//// //// -//// Description //// -//// Testbench tasks. //// -//// //// -//// To Do: //// -//// Nothing //// -//// //// -//// Author(s): //// -//// - Damjan Lampret, lampret@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: not supported by cvs2svn $ -// Revision 1.8 2003/11/19 14:22:43 gorand -// small changes, to satisfy VATS.. -// -// Revision 1.7 2003/11/10 23:23:57 gorand -// tests passed. -// -// Revision 1.6 2001/12/25 17:21:06 lampret -// Fixed two typos. -// -// Revision 1.5 2001/12/25 17:12:28 lampret -// Added RGPIO_INTS. -// -// Revision 1.4 2001/11/15 02:26:32 lampret -// Updated timing and fixed some typing errors. -// -// Revision 1.3 2001/09/18 16:37:55 lampret -// Changed VCD output location. -// -// Revision 1.2 2001/09/18 15:43:27 lampret -// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v. -// -// Revision 1.1 2001/08/21 21:39:27 lampret -// Changed directory structure, port names and drfines. -// -// Revision 1.2 2001/07/14 20:37:23 lampret -// Test bench improvements. -// -// Revision 1.1 2001/06/05 07:45:22 lampret -// Added initial RTL and test benches. There are still some issues with these files. -// -// - -`include "timescale.v" -`include "gpio_defines.v" -`include "tb_defines.v" - -module tb_tasks; - -integer nr_failed; -integer ints_disabled; -integer ints_working; -integer local_errs; - -parameter sh_addr = `GPIO_ADDRLH+1; -parameter gw = `GPIO_IOS ; -// -// Count/report failed tests -// -task failed; -begin - $display("FAILED !!!"); - nr_failed = nr_failed + 1; -end -endtask - -// -// Set RGPIO_OUT register -// -task setout; -input [31:0] val; - -reg [ 31:0 ] addr ; -begin - addr = `GPIO_RGPIO_OUT <

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