Subversion Repositories gpio

/log/ncelab.log File deleted

/log/ncvlog.log File deleted

/log/ncsim.log File deleted

/run/ncsim.tcl File deleted

/run/run_sim_gpio File deleted

run/run_sim_gpio Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: run/run_sim =================================================================== --- run/run_sim (revision 65) +++ run/run_sim (nonexistent) @@ -1,3 +0,0 @@ -#!/bin/sh -./run_sim_gpio gpio_testbench -

run/run_sim Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: run/ncelab.args =================================================================== --- run/ncelab.args (revision 65) +++ run/ncelab.args (nonexistent) @@ -1,10 +0,0 @@ --MESSAGES --NOCOPYRIGHT --CDSLIB ../bin/cds.lib --HDLVAR ../bin/hdl.var --LOGFILE ../log/ncelab.log --SNAPSHOT worklib.bench:rtl --NO_TCHK_MSG --ACCESS +RWC -worklib.tb_tasks -worklib.gpio_testbench Index: run/ncvlog.args =================================================================== --- run/ncvlog.args (revision 65) +++ run/ncvlog.args (nonexistent) @@ -1,13 +0,0 @@ --CDSLIB ../bin/cds.lib --HDLVAR ../bin/hdl.var --MESSAGES --INCDIR ../../../bench/verilog --INCDIR ../../../rtl/verilog --NOCOPYRIGHT --LOGFILE ../log/ncvlog.log -../../../rtl/verilog/gpio_top.v -../../../bench/verilog/clkrst.v -../../../bench/verilog/gpio_mon.v -../../../bench/verilog/wb_master.v -../../../bench/verilog/tb_tasks.v -../../../bench/verilog/gpio_testbench.v Index: run/ncsim.args =================================================================== --- run/ncsim.args (revision 65) +++ run/ncsim.args (nonexistent) @@ -1,7 +0,0 @@ --MESSAGES --NOCOPYRIGHT --CDSLIB ../bin/cds.lib --HDLVAR ../bin/hdl.var --INPUT ncsim.tcl --LOGFILE ../log/ncsim.log -worklib.bench:rtl Index: bin/sim_file_list =================================================================== --- bin/sim_file_list (revision 65) +++ bin/sim_file_list (nonexistent) @@ -1,7 +0,0 @@ -clkrst.v -gpio_mon.v -wb_master.v -tb_tasks.v -gpio_testbench.v - -

bin/sim_file_list Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/sim.sh =================================================================== --- bin/sim.sh (revision 65) +++ bin/sim.sh (nonexistent) @@ -1,125 +0,0 @@ -#!/bin/bash - -# -# This script runs RTL and gate-level simulation using different simultion tools. -# Right now Cadence Verilog-XL and NCSim are supported. -# -# Author: Damjan Lampret -# - -# -# User definitions -# - -# Set simulation tool you are using (xl, ncsim, ncver) -SIMTOOL=ncsim - -# Set test bench top module(s) -TB_TOP="tb_tasks" - -# Set include directories -INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/" - -# Set test bench files -BENCH_FILES="../../../bench/verilog/*.v" - -# Set RTL source files -RTL_FILES="../../../rtl/verilog/*.v" - -# Set gate-level netlist files -GATE_FILES="../syn/out/final_gpio.v" - -# Set libraries (standard cell etc.) -LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v" - -# Set parameters for simulation tool -if [ $SIMTOOL == xl ]; then - PARAM="+turbo+3 -q" - for i in $INCLUDE_DIRS; do - INCDIR=$INCDIR" +incdir+$i" - done -elif [ $SIMTOOL == ncver ]; then - NCVER_PARAM="" - for i in $INCLUDE_DIRS; do - INCDIR=$INCDIR" +incdir+$i" - done -elif [ $SIMTOOL == ncsim ]; then - NCPREP_PARAM="-UPDATE +overwrite" - NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT" - for i in $INCLUDE_DIRS; do - INCDIR=$INCDIR" +incdir+$i" - done -else - echo "$SIMTOOL is unsupported simulation tool." - exit 0 -fi - -# -# Don't change anything below unless you know what you are doing -# - -# Run simulation in sim directory -#cd ../sim - -# Run actual simulation - -# Cadence Verilog-XL -if [ $SIMTOOL == xl ]; then - - # RTL simulation - if [ "$1" == rtl ]; then - verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES - - # Gate-level simulation - elif [ "$1" == gate ]; then - verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES - - # Wrong parameter or no parameter - else - echo "Usage: $0 [rtl|gate]" - exit 0 - fi - -# Cadence Ncverilog -elif [ $SIMTOOL == ncver ]; then - - # RTL simulation - if [ "$1" == rtl ]; then - ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES - cp ncverilog.log ../log - - # Gate-level simulation - elif [ "$1" == gate ]; then - ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES - cp ncverilog.log ../log - - # Wrong parameter or no parameter - else - echo "Usage: $0 [rtl|gate]" - exit 0 - fi - -# Cadence Ncsim -elif [ $SIMTOOL == ncsim ]; then - - # RTL simulation - if [ "$1" == rtl ]; then - ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES - ./RUN_NC - - # Gate-level simulation - elif [ "$1" == gate ]; then - ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES - ./RUN_NC - - # Wrong parameter or no parameter - else - echo "Usage: $0 [rtl|gate]" - exit 0 - fi - -# Unsupported simulation tool -else - echo "$SIMTOOL is unsupported simulation tool." - exit 0; -fi

bin/sim.sh Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/rtl_file_list =================================================================== --- bin/rtl_file_list (revision 65) +++ bin/rtl_file_list (nonexistent) @@ -1 +0,0 @@ -gpio_top.v

bin/rtl_file_list Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: bin/cds.lib =================================================================== --- bin/cds.lib (revision 65) +++ bin/cds.lib (nonexistent) @@ -1,6 +0,0 @@ -# -# cds.lib: Defines the locations of compiled libraries. -# Created by ncprep on Tue Nov 11 00:24:06 2003 -# - -define worklib ./INCA_libs/worklib Index: bin/hdl.var =================================================================== --- bin/hdl.var (revision 65) +++ bin/hdl.var (nonexistent) @@ -1,9 +0,0 @@ -# -# hdl.var: Defines variables used by the INCA tools. -# Created by ncprep on Tue Nov 11 00:24:06 2003 -# - -softinclude $CDS_INST_DIR/tools/inca/files/hdl.var - -define LIB_MAP ( $LIB_MAP, + => worklib ) -define VIEW_MAP ( $VIEW_MAP, .v => v)