OpenCores
URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 1 to Rev 2
    ↔ Reverse comparison
  •

Rev 1 → Rev 2

/trunk/bench/timescale.vh
0,0 → 1,?rev2len?
`timescale 1ns/10ps
/trunk/bench/clkrst.v
0,0 → 1,77
//////////////////////////////////////////////////////////////////////
//// ////
//// Clock and Reset Generator ////
//// ////
//// This file is part of the GPIO project ////
//// http://www.opencores.org/cores/gpio/ ////
//// ////
//// Description ////
//// Clock and reset generator. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "timescale.vh"
 
module clkrst(clk_o, rst_o);
 
//
// I/O ports
//
output clk_o; // Clock
output rst_o; // Reset
 
//
// Internal regs
//
reg clk_o; // Clock
reg rst_o; // Reset
 
initial begin
clk_o = 0;
rst_o = 1;
#20;
rst_o = 0;
end
 
//
// Clock
//
always #4 clk_o = ~clk_o;
 
endmodule
/trunk/bench/wb_master.v
0,0 → 1,306
`include "timescale.vh"
 
// -*- Mode: Verilog -*-
// Filename : wb_master.v
// Description : Wishbone Master Behavorial
// Author : Winefred Washington
// Created On : Thu Jan 11 21:18:41 2001
// Last Modified By: .
// Last Modified On: .
// Update Count : 0
// Status : Unknown, Use with caution!
 
// Description Specification
// General Description: 8, 16, 32-bit WISHBONE Master
// Supported cycles: MASTER, READ/WRITE
// MASTER, BLOCK READ/WRITE
// MASTER, RMW
// Data port, size: 8, 16, 32-bit
// Data port, granularity 8-bit
// Data port, Max. operand size 32-bit
// Data transfer ordering: little endian
// Data transfer sequencing: undefined
//
 
module wb_master(CLK_I, RST_I, TAG_I, TAG_O,
ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O);
 
input CLK_I;
input RST_I;
input [3:0] TAG_I;
output [3:0] TAG_O;
input ACK_I;
output [31:0] ADR_O;
output CYC_O;
input [31:0] DAT_I;
output [31:0] DAT_O;
input ERR_I;
input RTY_I;
output [3:0] SEL_O;
output STB_O;
output WE_O;
reg [31:0] ADR_O;
reg [3:0] SEL_O;
reg CYC_O;
reg STB_O;
reg WE_O;
reg [31:0] DAT_O;
wire [15:0] mem_sizes; // determines the data width of an address range
reg [31:0] write_burst_buffer[0:7];
reg [31:0] read_burst_buffer[0:7];
reg GO;
integer cycle_end;
integer address;
integer data;
integer selects;
integer write_flag;
//
// mem_sizes determines the data widths of memory space
// The memory space is divided into eight regions. Each
// region is controlled by a two bit field.
//
// Bits
// 00 = 8 bit memory space
// 01 = 16 bit
// 10 = 32 bit
// 11 = 64 bit (not supported in this model
//
assign mem_sizes = 16'b10_01_10_11_00_01_10_11;
 
function [1:0] data_width;
input [31:0] adr;
begin
casex (adr[31:29])
3'b000: data_width = mem_sizes[15:14];
3'b001: data_width = mem_sizes[13:12];
3'b010: data_width = mem_sizes[11:10];
3'b011: data_width = mem_sizes[9:8];
3'b100: data_width = mem_sizes[7:6];
3'b101: data_width = mem_sizes[5:4];
3'b110: data_width = mem_sizes[3:2];
3'b111: data_width = mem_sizes[1:0];
3'bxxx: data_width = 2'bxx;
endcase // casex (adr[31:29])
end
endfunction
always @(posedge CLK_I or posedge RST_I)
begin
if (RST_I)
begin
GO = 1'b0;
end
end
// read single
task rd;
input [31:0] adr;
output [31:0] result;
begin
cycle_end = 1;
address = adr;
selects = 255;
write_flag = 0;
GO <= 1;
@(posedge CLK_I);
// GO <= 0;
 
// wait for cycle to start
while (~CYC_O)
@(posedge CLK_I);
 
// wait for cycle to end
while (CYC_O)
@(posedge CLK_I);
 
result = data;
// $display(" Reading %h from address %h", result, address);
end
endtask // read
task wr;
input [31:0] adr;
input [31:0] dat;
input [3:0] sel;
begin
cycle_end = 1;
address = adr;
selects = sel;
write_flag = 1;
data = dat;
GO <= 1;
@(posedge CLK_I);
// GO <= 0;
 
// wait for cycle to start
while (~CYC_O)
@(posedge CLK_I);
 
// wait for cycle to end
while (CYC_O)
@(posedge CLK_I);
// $display(" Writing %h to address %h", data, address);
 
end
endtask // wr
 
// block read
task blkrd;
input [31:0] adr;
input end_flag;
output [31:0] result;
begin
write_flag = 0;
cycle_end = end_flag;
address = adr;
GO <= 1;
@(posedge CLK_I);
// GO <= 0;
 
while (~(ACK_I & STB_O))
@(posedge CLK_I);
result = data;
end
endtask // blkrd
 
// block write
task blkwr;
input [31:0] adr;
input [31:0] dat;
input [3:0] sel;
input end_flag;
begin
write_flag = 1;
cycle_end = end_flag;
address = adr;
data = dat;
selects = sel;
GO <= 1;
@(posedge CLK_I);
// GO <= 0;
 
while (~(ACK_I & STB_O))
@(posedge CLK_I);
end
endtask // blkwr
 
// RMW
task rmw;
input [31:0] adr;
input [31:0] dat;
input [3:0] sel;
output [31:0] result;
begin
// read phase
write_flag = 0;
cycle_end = 0;
address = adr;
GO <= 1;
@(posedge CLK_I);
// GO <= 0;
 
while (~(ACK_I & STB_O))
@(posedge CLK_I);
result = data;
 
// write phase
write_flag = 1;
address = adr;
selects = sel;
GO <= 1;
data <= dat;
cycle_end <= 1;
@(posedge CLK_I);
// GO <= 0;
 
while (~(ACK_I & STB_O))
@(posedge CLK_I);
end
endtask // rmw
always @(posedge CLK_I)
begin
if (RST_I)
ADR_O <= 32'h0000_0000;
else
ADR_O <= address;
end
always @(posedge CLK_I)
begin
if (RST_I | ERR_I | RTY_I)
CYC_O <= 1'b0;
else if ((cycle_end == 1) & ACK_I)
CYC_O <= 1'b0;
else if (GO | CYC_O) begin
CYC_O <= 1'b1;
GO <= 1'b0;
end
end
 
// stb control
always @(posedge CLK_I)
begin
if (RST_I | ERR_I | RTY_I)
STB_O <= 1'b0;
else if (STB_O & ACK_I)
STB_O <= 1'b0;
else if (GO | STB_O)
STB_O <= 1'b1;
end
 
// selects & data
always @(posedge CLK_I)
begin
if (write_flag == 0) begin
SEL_O <= 4'b1111;
if (STB_O & ACK_I)
data <= DAT_I;
end
else begin
case (data_width(address))
2'b00: begin
SEL_O <= {3'b000, selects[0]};
DAT_O <= {data[7:0], data[7:0], data[7:0], data[7:0]};
end
2'b01: begin
SEL_O <= {2'b00, selects[1:0]};
DAT_O <= {data[15:0], data[15:0]};
end
2'b10: begin
SEL_O <= selects;
DAT_O <= data;
end
endcase
end
end
 
always @(posedge CLK_I)
begin
if (RST_I)
WE_O <= 1'b0;
else if (GO)
WE_O <= write_flag;
end
endmodule
 
 
 
 
 
/trunk/bench/gpio_mon.v
0,0 → 1,125
//////////////////////////////////////////////////////////////////////
//// ////
//// GPIO Monitor ////
//// ////
//// This file is part of the GPIO project ////
//// http://www.opencores.org/cores/gpio/ ////
//// ////
//// Description ////
//// Generates and monitors GPIO external signals (+auxiliary) ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "timescale.vh"
 
module gpio_mon(gpio_aux, gpio_in, gpio_eclk, gpio_out, gpio_oen);
 
parameter gw = 32;
 
//
// I/O ports
//
output [gw-1:0] gpio_aux; // Auxiliary
output [gw-1:0] gpio_in; // GPIO inputs
output gpio_eclk; // GPIO external clock
input [gw-1:0] gpio_out; // GPIO outputs
input [gw-1:0] gpio_oen; // GPIO output enables
 
//
// Internal regs
//
reg [gw-1:0] gpio_aux;
reg [gw-1:0] gpio_in;
reg gpio_eclk;
 
initial gpio_eclk = 0;
 
//
// Set gpio_in
//
task set_gpioin;
input [31:0] val;
begin
gpio_in = val;
end
endtask
 
//
// Set gpio_aux
//
task set_gpioaux;
input [31:0] val;
begin
gpio_aux = val;
end
endtask
 
//
// Set gpio_eclk
//
task set_gpioeclk;
input val;
begin
gpio_eclk = val[0];
end
endtask
 
 
//
// Get gpio_out
//
task get_gpioout;
output [31:0] val;
reg [31:0] val;
begin
val = gpio_out;
end
endtask
 
//
// Get gpio_oen
//
task get_gpiooen;
output [31:0] val;
begin
val = gpio_oen;
end
endtask
 
endmodule
/trunk/bench/tb_top.v
0,0 → 1,146
//////////////////////////////////////////////////////////////////////
//// ////
//// GPIO Testbench Top ////
//// ////
//// This file is part of the GPIO project ////
//// http://www.opencores.org/cores/gpio/ ////
//// ////
//// Description ////
//// Top level of testbench. It instantiates all blocks. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "timescale.vh"
 
module tb_top;
 
parameter aw = 32;
parameter dw = 32;
parameter gw = 32;
 
//
// Interconnect wires
//
wire clk; // Clock
wire rst; // Reset
wire cyc; // Cycle valid
wire [aw-1:0] adr; // Address bus
wire [dw-1:0] dat_m; // Data bus from PTC to WBM
wire [3:0] sel; // Data selects
wire we; // Write enable
wire stb; // Strobe
wire [dw-1:0] dat_ptc;// Data bus from WBM to PTC
wire ack; // Successful cycle termination
wire err; // Failed cycle termination
wire [gw-1:0] gpio_aux; // GPIO auxiliary signals
wire [gw-1:0] gpio_in; // GPIO inputs
wire gpio_eclk; // GPIO external clock
wire [gw-1:0] gpio_out; // GPIO outputs
wire [gw-1:0] gpio_oen; // GPIO output enables
 
//
// Instantiation of Clock/Reset Generator
//
clkrst clkrst(
// Clock
.clk_o(clk),
// Reset
.rst_o(rst)
);
 
//
// Instantiation of Master WISHBONE BFM
//
wb_master wb_master(
// WISHBONE Interface
.CLK_I(clk),
.RST_I(rst),
.CYC_O(cyc),
.ADR_O(adr),
.DAT_O(dat_ptc),
.SEL_O(sel),
.WE_O(we),
.STB_O(stb),
.DAT_I(dat_m),
.ACK_I(ack),
.ERR_I(err),
.RTY_I(0),
.TAG_I(4'b0)
);
 
//
// Instantiation of PTC core
//
gpio gpio(
// WISHBONE Interface
.clk_i(clk),
.rst_i(rst),
.cyc_i(cyc),
.adr_i(adr[15:0]),
.dat_i(dat_ptc),
.sel_i(sel),
.we_i(we),
.stb_i(stb),
.dat_o(dat_m),
.ack_o(ack),
.err_o(err),
.inta_o(),
 
// Auxiliary inputs interface
.gpio_aux(gpio_aux),
 
// External GPIO Interface
.gpio_in(gpio_in),
.gpio_eclk(gpio_eclk),
.gpio_out(gpio_out),
.gpio_oen(gpio_oen)
);
 
//
// GPIO Monitor
//
gpio_mon gpio_mon(
.gpio_aux(gpio_aux),
.gpio_in(gpio_in),
.gpio_eclk(gpio_eclk),
.gpio_out(gpio_out),
.gpio_oen(gpio_oen)
);
 
endmodule
/trunk/bench/tb_defines.vh
0,0 → 1,51
//////////////////////////////////////////////////////////////////////
//// ////
//// GPIO Testbench Definitions ////
//// ////
//// This file is part of the GPIO project ////
//// http://www.opencores.org/cores/gpio/ ////
//// ////
//// Description ////
//// Testbench definitions that affect how testbench simulation ////
//// is performed. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
//`define DEBUG
`define DUMP_VCD
/trunk/bench/tb_tasks.v
0,0 → 1,823
//////////////////////////////////////////////////////////////////////
//// ////
//// GPIO Testbench Tasks ////
//// ////
//// This file is part of the GPIO project ////
//// http://www.opencores.org/cores/gpio/ ////
//// ////
//// Description ////
//// Testbench tasks. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "timescale.vh"
`include "defines.vh"
`include "tb_defines.vh"
 
module tb_tasks;
 
integer nr_failed;
integer ints_disabled;
integer ints_working;
 
//
// Count/report failed tests
//
task failed;
begin
$display("FAILED !!!");
nr_failed = nr_failed + 1;
end
endtask
 
//
// Set RGPIO_OUT register
//
task setout;
input [31:0] val;
 
begin
#100 tb_top.wb_master.wr(`RGPIO_OUT<<2, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_OE register
//
task setoe;
input [31:0] val;
 
begin
#100 tb_top.wb_master.wr(`RGPIO_OE<<2, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_INTE register
//
task setinte;
input [31:0] val;
 
begin
#100 tb_top.wb_master.wr(`RGPIO_INTE<<2, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_PTRIG register
//
task setptrig;
input [31:0] val;
 
begin
#100 tb_top.wb_master.wr(`RGPIO_PTRIG<<2, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_AUX register
//
task setaux;
input [31:0] val;
 
begin
#100 tb_top.wb_master.wr(`RGPIO_AUX<<2, val, 4'b1111);
end
 
endtask
 
//
// Set RGPIO_CTRL register
//
task setctrl;
input [31:0] val;
 
begin
#100 tb_top.wb_master.wr(`RGPIO_CTRL<<2, val, 4'b1111);
end
 
endtask
 
//
// Display RGPIO_IN register
//
task showin;
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`RGPIO_IN<<2, tmp);
$write(" RGPIO_IN: %h", tmp);
end
 
endtask
 
//
// Display RGPIO_OUT register
//
task showout;
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`RGPIO_OUT<<2, tmp);
$write(" RGPIO_OUT: %h", tmp);
end
 
endtask
 
 
//
// Display RGPIO_OE register
//
task showoe;
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`RGPIO_OE<<2, tmp);
$write(" RGPIO_OE:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_INTE register
//
task showinte;
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`RGPIO_INTE<<2, tmp);
$write(" RGPIO_INTE:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_PTRIG register
//
task showptrig;
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`RGPIO_PTRIG<<2, tmp);
$write(" RGPIO_PTRIG:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_AUX register
//
task showaux;
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`RGPIO_AUX<<2, tmp);
$write(" RGPIO_AUX:%h", tmp);
end
 
endtask
 
//
// Display RGPIO_CTRL register
//
task showctrl;
 
reg [31:0] tmp;
begin
#100 tb_top.wb_master.rd(`RGPIO_CTRL<<2, tmp);
$write(" RGPIO_CTRL: %h", tmp);
end
 
endtask
 
//
// Compare parameter with RGPIO_IN register
//
task comp_in;
input [31:0] val;
output ret;
 
reg [31:0] tmp;
reg ret;
begin
#100 tb_top.wb_master.rd(`RGPIO_IN<<2, tmp);
 
if (tmp == val)
ret = 1;
else
ret = 0;
end
 
endtask
 
//
// Get RGPIO_IN register
//
task getin;
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`RGPIO_IN<<2, tmp);
end
 
endtask
 
//
// Get RGPIO_OUT register
//
task getout;
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`RGPIO_OUT<<2, tmp);
end
 
endtask
 
//
// Get RGPIO_OE register
//
task getoe;
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`RGPIO_OE<<2, tmp);
end
 
endtask
 
//
// Get RGPIO_INTE register
//
task getinte;
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`RGPIO_INTE<<2, tmp);
end
 
endtask
 
//
// Get RGPIO_PTRIG register
//
task getptrig;
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`RGPIO_PTRIG<<2, tmp);
end
 
endtask
 
//
// Get RGPIO_AUX register
//
task getaux;
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`RGPIO_AUX<<2, tmp);
end
 
endtask
 
//
// Get RGPIO_CTRL register
//
task getctrl;
output [31:0] tmp;
 
begin
#100 tb_top.wb_master.rd(`RGPIO_CTRL<<2, tmp);
end
 
endtask
 
//
// Test operation of control bit RGPIO_CTRL[ECLK]
//
task test_eclk;
integer l1, l2, l3;
begin
$write(" Testing control bit RGPIO_CTRL[ECLK] ...");
 
//
// Phase 1
//
// GPIO uses WISHBONE clock to latch gpio_in
//
 
// Put something on gpio_in pins
tb_top.gpio_mon.set_gpioin('d12345678);
 
// Reset GPIO_CTRL
setctrl(0);
 
// Wait for time to advance
#1000;
 
// Read RGPIO_IN
getin(l1);
 
//
// Phase 2
//
// GPIO uses external clock to latch gpio_in
//
 
// Set GPIO to use external clock
setctrl(1 << `RGPIO_CTRL_ECLK);
 
// Put something else on gpio_in pins
tb_top.gpio_mon.set_gpioin('d55667788);
 
// Wait for time to advance
#1000;
 
// Read RGPIO_IN (should be the same as l1)
getin(l2);
 
// Make an external clock
tb_top.gpio_mon.set_gpioeclk(0);
#10;
tb_top.gpio_mon.set_gpioeclk(1);
#10;
 
// Read RGPIO_IN (should be different than l2)
getin(l3);
 
//
// Phase 3
//
// Compare phases
//
if (l1 == l2 && l2 == 'd12345678 && l3 == 'd55667788)
$display(" OK");
else
failed;
end
endtask
 
//
// Test operation of control bit RGPIO_CTRL[NEC]
//
task test_nec;
integer l1, l2;
begin
$write(" Testing control bit RGPIO_CTRL[NEC] ...");
 
//
// Phase 1
//
// Compare RGPIO_IN before and after negative edge
//
 
// Clear RGPIO_IN
tb_top.gpio_mon.set_gpioin('d0);
 
// Set GPIO to use WB clock
setctrl(0);
 
// Advance time
#1000;
 
// Set GPIO to use external clock and set RGPIO_CTRL[NEC]
setctrl(1 << `RGPIO_CTRL_ECLK | 1 << `RGPIO_CTRL_NEC);
 
// Put something on gpio_in pins
tb_top.gpio_mon.set_gpioin('d11112222);
 
// Wait for time to advance
#1000;
 
// Read RGPIO_IN
getin(l1);
 
// Make an external clock
tb_top.gpio_mon.set_gpioeclk(1);
#10;
tb_top.gpio_mon.set_gpioeclk(0);
#10;
 
// Read RGPIO_IN (should be different than l1)
getin(l2);
 
//
// Phase 2
//
// Compare phases
//
if (!l1 && l2 == 'd11112222)
$display(" OK");
else
failed;
end
endtask
 
//
// Test input polled mode, output mode and bidirectional
//
task test_simple;
integer l1, l2, l3, l4;
integer i, err;
begin
$write(" Testing input mode ...");
 
//
// Phase 1
//
// Compare RGPIO_IN and gpio_in
//
 
// Set GPIO to use WB clock
setctrl(0);
 
err = 0;
for (i = 0; i < 10; i = i +1) begin
// Put something on gpio_in pins
l1 = $random;
tb_top.gpio_mon.set_gpioin(l1);
 
// Advance time
#1000;
 
// Read RGPIO_IN
getin(l2);
 
// Compare gpio_in and RGPIO_IN. Should be equal.
if (l1 != l2)
err = err + 1;
end
 
// Phase 2
//
// Output result for previous test
//
if (!err)
$display(" OK");
else
failed;
 
$write(" Testing output mode ...");
 
//
// Phase 3
//
// Compare RGPIO_OUT and gpio_out
//
 
err = 0;
for (i = 0; i < 10; i = i +1) begin
// Put something in RGPIO_OUT pins
l1 = $random;
setout(l1);
 
// Advance time
#1000;
 
// Read gpio_out
tb_top.gpio_mon.get_gpioout(l2);
 
// Compare gpio_out and RGPIO_OUT. Should be equal.
if (l1 != l2)
err = err + 1;
end
 
// Phase 4
//
// Output result for previous test
//
if (!err)
$display(" OK");
else
failed;
 
$write(" Testing bidirectional I/O ...");
 
//
// Phase 5
//
// Compare RGPIO_OE and gpio_oen
//
 
err = 0;
for (i = 0; i < 10; i = i +1) begin
// Put something in RGPIO_OE pins
l1 = $random;
setoe(l1);
 
// Advance time
#1000;
 
// Read gpio_oen
tb_top.gpio_mon.get_gpiooen(l2);
 
// Compare gpio_oen and RGPIO_OE. Should be exactly opposite.
if (l1 != ~l2)
err = err + 1;
end
 
// Phase 6
//
// Output result for previous test
//
if (!err)
$display(" OK");
else
failed;
 
$write(" Testing auxiliary feature ...");
 
//
// Phase 7
//
// Compare RGPIO_OUT, gpio_out, RGPIO_AUX and gpio_aux
//
 
err = 0;
for (i = 0; i < 100; i = i +1) begin
// Put something on gpio_aux pins
l1 = $random;
tb_top.gpio_mon.set_gpioaux(l1);
 
// Put something in RGPIO_AUX pins
l2 = $random;
setaux(l2);
 
// Put something in RGPIO_OUT pins
l3 = $random;
setout(l3);
 
// Advance time
#1000;
 
// Read gpio_out
tb_top.gpio_mon.get_gpioout(l4);
 
// Compare gpio_out, RGPIO_OUT, RGPIO_AUX and gpio_aux.
// RGPIO_AUX specifies which gpio_aux bits and RGPIO_OUT
// bits are present on gpio_out and where
if ((l1 & l2 | l3 & ~l2) != l4)
err = err + 1;
end
 
// Phase 8
//
// Output result for previous test
//
if (!err)
$display(" OK");
else
failed;
 
end
endtask
 
//
// Test interrupts
//
task test_ints;
integer l1, l2, l3;
integer i, rnd, err;
begin
$write(" Testing control bis RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ...");
 
//
// Phase 1
//
// Generate patterns on inputs in interrupt mode
//
 
// Disable spurious interrupt monitor
ints_disabled = 0;
 
err = 0;
for( i = 0; i < 10; i = i + 1) begin
 
// Get some random bits
rnd = $random;
 
// Set gpio_in pins
tb_top.gpio_mon.set_gpioin('hffffffff);
 
// Low level triggering
setptrig(0);
 
// Enable interrupts in RGPIO_CTRL
setctrl(1 << `RGPIO_CTRL_INTE);
 
// Enable interrupts in RGPIO_INTE
setinte(rnd);
 
// Advance time
#100;
 
// Sample interrupt request. Should be zero.
l1 = tb_top.gpio.inta_o;
 
// Clear gpio_in pins
tb_top.gpio_mon.set_gpioin(0);
 
// Advance time
#100;
 
// Sample interrupt request. Should be one.
l2 = tb_top.gpio.inta_o;
 
// Clear interrupt request
setctrl(0);
 
// Advance time
#100;
 
// Sample interrupt request. Should be zero.
l3 = tb_top.gpio.inta_o;
 
// Check for errors
if (l1 || !l2 || l3)
err = err +1;
end
// Enable spurious interrupt monitor
ints_disabled = 1;
 
// Phase 2
//
// Check results
//
if (!err)
$display(" OK");
else
failed;
end
endtask
 
//
// Test ptrig
//
task test_ptrig;
integer l1, l2, l3;
integer i, rnd, err;
begin
$write(" Testing ptrig features ...");
 
//
// Phase 1
//
// Generate patterns on inputs in interrupt mode
//
 
// Disable spurious interrupt monitor
ints_disabled = 0;
 
err = 0;
for( i = 0; i < 10; i = i + 1) begin
 
// Get some random bits
rnd = $random;
 
// Set gpio_in pins
tb_top.gpio_mon.set_gpioin('h00000000);
 
// High level triggering
setptrig('hffffffff);
 
// Enable interrupts in RGPIO_CTRL
setctrl(1 << `RGPIO_CTRL_INTE);
 
// Enable interrupts in RGPIO_INTE
setinte(rnd);
 
// Advance time
#100;
 
// Sample interrupt request. Should be zero.
l1 = tb_top.gpio.inta_o;
 
// Clear gpio_in pins
tb_top.gpio_mon.set_gpioin('hffffffff);
 
// Advance time
#100;
 
// Sample interrupt request. Should be one.
l2 = tb_top.gpio.inta_o;
 
// Clear interrupt request
setctrl(0);
 
// Advance time
#100;
 
// Sample interrupt request. Should be zero.
l3 = tb_top.gpio.inta_o;
 
// Check for errors
if (l1 || !l2 || l3)
err = err +1;
end
// Enable spurious interrupt monitor
ints_disabled = 1;
 
// Phase 2
//
// Check results
//
if (!err)
$display(" OK");
else
failed;
end
endtask
 
//
// Do continues check for interrupts
//
always @(posedge tb_top.gpio.inta_o)
if (ints_disabled) begin
$display("Spurious interrupt detected. ");
failed;
ints_working = 9876;
$display;
end
 
//
// Start of testbench test tasks
//
initial begin
`ifdef DUMP_VCD
$dumpfile("../sim/tb_top.vcd");
$dumpvars(0);
`endif
nr_failed = 0;
ints_disabled = 1;
ints_working = 0;
tb_top.gpio_mon.set_gpioin(0);
tb_top.gpio_mon.set_gpioaux(0);
tb_top.gpio_mon.set_gpioeclk(0);
$display;
$display("###");
$display("### GPIO IP Core Verification ###");
$display("###");
$display;
$display("I. Testing correct operation of RGPIO_CTRL control bits");
$display;
test_eclk;
test_nec;
test_ints;
$display;
$display("II. Testing modes of operation ...");
$display;
test_simple;
test_ptrig;
$display;
$display("###");
$display("### FAILED TESTS: %d ###", nr_failed);
$display("###");
$display;
$finish;
end
 
endmodule
/trunk/rtl/gpio.v
0,0 → 1,349
//////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE General-Purpose I/O ////
//// ////
//// This file is part of the GPIO project ////
//// http://www.opencores.org/cores/gpio/ ////
//// ////
//// Description ////
//// Implementation of GPIO IP core according to ////
//// GPIO IP core specification document. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "timescale.vh"
`include "defines.vh"
 
module gpio(
// WISHBONE Interface
clk_i, rst_i, cyc_i, adr_i, dat_i, sel_i, we_i, stb_i,
dat_o, ack_o, err_o, inta_o,
 
// Auxiliary inputs interface
gpio_aux,
 
// External GPIO Interface
gpio_in, gpio_eclk, gpio_out, gpio_oen
);
 
parameter dw = 32;
parameter aw = 16;
parameter gw = 32;
 
//
// WISHBONE Interface
//
input clk_i; // Clock
input rst_i; // Reset
input cyc_i; // cycle valid input
input [aw-1:0] adr_i; // address bus inputs
input [dw-1:0] dat_i; // input data bus
input [3:0] sel_i; // byte select inputs
input we_i; // indicates write transfer
input stb_i; // strobe input
output [dw-1:0] dat_o; // output data bus
output ack_o; // normal termination
output err_o; // termination w/ error
output inta_o; // Interrupt request output
 
// Auxiliary Inputs Interface
input [gw-1:0] gpio_aux; // Auxiliary inputs
 
//
// External GPIO Interface
//
input [gw-1:0] gpio_in; // GPIO Inputs
input gpio_eclk; // GPIO Eclk
output [gw-1:0] gpio_out; // GPIO Outputs
output [gw-1:0] gpio_oen; // GPIO output drivers enables
 
`ifdef GPIO_IMPLEMENTED
 
//
// GPIO Input Register (or no register)
//
`ifdef RGPIO_IN
reg [gw-1:0] rgpio_in; // RGPIO_IN register
`else
wire [gw-1:0] rgpio_in; // No register
`endif
 
//
// GPIO Output Register (or no register)
//
`ifdef RGPIO_OUT
reg [gw-1:0] rgpio_out; // RGPIO_OUT register
`else
wire [gw-1:0] rgpio_out; // No register
`endif
 
//
// GPIO Output Driver Enable Register (or no register)
//
`ifdef RGPIO_OE
reg [gw-1:0] rgpio_oe; // RGPIO_OE register
`else
wire [gw-1:0] rgpio_oe; // No register
`endif
 
//
// GPIO Interrupt Enable Register (or no register)
//
`ifdef RGPIO_INTE
reg [gw-1:0] rgpio_inte; // RGPIO_INTE register
`else
wire [gw-1:0] rgpio_inte; // No register
`endif
 
//
// GPIO Positive edge Triggered Register (or no register)
//
`ifdef RGPIO_PTRIG
reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register
`else
wire [gw-1:0] rgpio_ptrig; // No register
`endif
 
//
// GPIO Auxiliary select Register (or no register)
//
`ifdef RGPIO_AUX
reg [gw-1:0] rgpio_aux; // RGPIO_AUX register
`else
wire [gw-1:0] rgpio_aux; // No register
`endif
 
//
// GPIO Control Register (or no register)
//
`ifdef RGPIO_CTRL
reg [3:0] rgpio_ctrl; // RGPIO_CTRL register
`else
wire [3:0] rgpio_ctrl; // No register
`endif
 
//
// Internal wires & regs
//
wire rgpio_in_sel; // RGPIO_IN select
wire rgpio_out_sel; // RGPIO_OUT select
wire rgpio_oe_sel; // RGPIO_OE select
wire rgpio_inte_sel; // RGPIO_INTE select
wire rgpio_ptrig_sel;// RGPIO_PTRIG select
wire rgpio_aux_sel; // RGPIO_AUX select
wire rgpio_ctrl_sel; // RGPIO_CTRL select
wire latch_clk; // Latch clock
reg [dw-1:0] dat_o; // Data out
 
//
// All WISHBONE transfer terminations are successful
//
assign ack_o = cyc_i & stb_i;
assign err_o = 1'b0;
 
//
// Latch clock is selected by RGPIO_CTRL[ECLK]. When it is set,
// external clock is used.
//
assign latch_clk = rgpio_ctrl[`RGPIO_CTRL_ECLK] ?
gpio_eclk ^ rgpio_ctrl[`RGPIO_CTRL_NEC] : clk_i;
 
//
// PWM output driver enables are inverted RGPIO_OE bits
//
assign gpio_oen = ~rgpio_oe;
 
//
// GPIO registers address decoder
//
assign rgpio_in_sel = cyc_i & stb_i & (adr_i[`GPIOOFS_BITS] == `RGPIO_IN);
assign rgpio_out_sel = cyc_i & stb_i & (adr_i[`GPIOOFS_BITS] == `RGPIO_OUT);
assign rgpio_oe_sel = cyc_i & stb_i & (adr_i[`GPIOOFS_BITS] == `RGPIO_OE);
assign rgpio_inte_sel = cyc_i & stb_i & (adr_i[`GPIOOFS_BITS] == `RGPIO_INTE);
assign rgpio_ptrig_sel = cyc_i & stb_i & (adr_i[`GPIOOFS_BITS] == `RGPIO_PTRIG);
assign rgpio_aux_sel = cyc_i & stb_i & (adr_i[`GPIOOFS_BITS] == `RGPIO_AUX);
assign rgpio_ctrl_sel = cyc_i & stb_i & (adr_i[`GPIOOFS_BITS] == `RGPIO_CTRL);
 
//
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
//
`ifdef RGPIO_CTRL
always @(posedge clk_i or posedge rst_i)
if (rst_i)
rgpio_ctrl <= #1 4'b0;
else if (rgpio_ctrl_sel && we_i)
rgpio_ctrl <= #1 dat_i[3:0];
else if (rgpio_ctrl[`RGPIO_CTRL_INTE])
rgpio_ctrl[`RGPIO_CTRL_INT] <= #1 rgpio_ctrl[`RGPIO_CTRL_INT] | inta_o;
`else
assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1
`endif
 
//
// Write to RGPIO_OUT
//
`ifdef RGPIO_OUT
always @(posedge clk_i or posedge rst_i)
if (rst_i)
rgpio_out <= #1 {gw{1'b0}};
else if (rgpio_out_sel && we_i)
rgpio_out <= #1 dat_i[gw-1:0];
`else
assign rgpio_out = `DEF_RPGIO_OUT; // RGPIO_OUT = 0x0
`endif
 
//
// Write to RGPIO_OE
//
`ifdef RGPIO_OE
always @(posedge clk_i or posedge rst_i)
if (rst_i)
rgpio_oe <= #1 {gw{1'b0}};
else if (rgpio_oe_sel && we_i)
rgpio_oe <= #1 dat_i[gw-1:0];
`else
assign rgpio_oe = `DEF_RPGIO_OE; // RGPIO_OE = 0x0
`endif
 
//
// Write to RGPIO_INTE
//
`ifdef RGPIO_INTE
always @(posedge clk_i or posedge rst_i)
if (rst_i)
rgpio_inte <= #1 {gw{1'b0}};
else if (rgpio_inte_sel && we_i)
rgpio_inte <= #1 dat_i[gw-1:0];
`else
assign rgpio_inte = `DEF_RPGIO_INTE; // RGPIO_INTE = 0x0
`endif
 
//
// Write to RGPIO_PTRIG
//
`ifdef RGPIO_PTRIG
always @(posedge clk_i or posedge rst_i)
if (rst_i)
rgpio_ptrig <= #1 {gw{1'b0}};
else if (rgpio_ptrig_sel && we_i)
rgpio_ptrig <= #1 dat_i[gw-1:0];
`else
assign rgpio_ptrig = `DEF_RPGIO_PTRIG; // RGPIO_PTRIG = 0x0
`endif
 
//
// Write to RGPIO_AUX
//
`ifdef RGPIO_AUX
always @(posedge clk_i or posedge rst_i)
if (rst_i)
rgpio_aux <= #1 {gw{1'b0}};
else if (rgpio_aux_sel && we_i)
rgpio_aux <= #1 dat_i[gw-1:0];
`else
assign rgpio_aux = `DEF_RPGIO_AUX; // RGPIO_AUX = 0x0
`endif
 
//
// Latch into RGPIO_IN
//
`ifdef RGPIO_IN
always @(posedge latch_clk or posedge rst_i)
if (rst_i)
rgpio_in <= #1 {gw{1'b0}};
else
rgpio_in <= #1 gpio_in;
`else
assign rgpio_in = gpio_in;
`endif
 
//
// Read GPIO registers
//
always @(adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
rgpio_ptrig or rgpio_aux or rgpio_ctrl)
case (adr_i[`GPIOOFS_BITS]) // synopsys full_case parallel_case
`ifdef GPIO_READREGS
`RGPIO_IN: dat_o[gw-1:0] <= rgpio_in;
`RGPIO_OUT: dat_o[gw-1:0] <= rgpio_out;
`RGPIO_OE: dat_o[gw-1:0] <= rgpio_oe;
`RGPIO_INTE: dat_o[gw-1:0] <= rgpio_inte;
`RGPIO_PTRIG: dat_o[gw-1:0] <= rgpio_ptrig;
`RGPIO_AUX: dat_o[gw-1:0] <= rgpio_aux;
`endif
default: dat_o[3:0] <= rgpio_ctrl;
endcase
 
//
// Generate interrupt request
//
assign inta_o = ((gpio_in ^ ~rgpio_ptrig) & rgpio_inte) ? rgpio_ctrl[`RGPIO_CTRL_INTE] : 1'b0;
 
//
// Generate output enables
//
assign gpio_oen = ~rgpio_oe;
 
//
// Generate outputs
//
assign gpio_out = rgpio_out & ~rgpio_aux | gpio_aux & rgpio_aux;
 
`else
 
//
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
// is cleared and WISHBONE transfers complete with errors
//
assign inta_o = 1'b0;
assign ack_o = 1'b0;
assign err_o = cyc_i & stb_i;
assign gpio_oen = ~(gw'b0);
assign gpio_out = gw'b0;
 
//
// Read GPIO registers
//
`ifdef GPIO_READREGS
assign dat_o = {dw{1'b0}};
`endif
 
`endif
 
endmodule
/trunk/rtl/defines.vh
0,0 → 1,63
//////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE GPIO Definitions ////
//// ////
//// This file is part of the GPIO project ////
//// http://www.opencores.org/cores/gpio/ ////
//// ////
//// Description ////
//// GPIO IP Definitions. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`define GPIO_IMPLEMENTED
`define GPIO_READREGS
`define GPIOOFS_BITS 4:2
`define RGPIO_IN 3'h0 // Address 0x00
`define RGPIO_OUT 3'h1 // Address 0x04
`define RGPIO_OE 3'h2 // Address 0x08
`define RGPIO_INTE 3'h3 // Address 0x0c
`define RGPIO_PTRIG 3'h4 // Address 0x10
`define RGPIO_AUX 3'h5 // Address 0x14
`define RGPIO_CTRL 3'h6 // Address 0x18
 
`define RGPIO_CTRL_ECLK 0
`define RGPIO_CTRL_NEC 1
`define RGPIO_CTRL_INTE 2
`define RGPIO_CTRL_INT 3
/trunk/sim/xl.sh
0,0 → 1,4
#!/bin/sh
cd ../sim
verilog +turbo+3 -q ../bench/wb_master.v ../bench/clkrst.v ../bench/tb_top.v ../bench/tb_tasks.v \
../bench/gpio_mon.v ../rtl/gpio.v +incdir+../rtl/ +incdir+../bench/
trunk/sim/xl.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.