URL
https://opencores.org/ocsvn/gpio/gpio/trunk
Subversion Repositories gpio
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 11 to Rev 12
- ↔ Reverse comparison
Rev 11 → Rev 12
/trunk/bench/verilog/tb_top.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/21 21:39:27 lampret |
// Changed directory structure, port names and drfines. |
// |
// Revision 1.2 2001/07/14 20:37:24 lampret |
// Test bench improvements. |
// |
53,7 → 56,7
// |
|
`include "timescale.v" |
`include "defines.v" |
`include "gpio_defines.v" |
|
module tb_top; |
|
114,7 → 117,7
// |
// Instantiation of PTC core |
// |
gpio gpio( |
gpio_top gpio_top( |
// WISHBONE Interface |
.wb_clk_i(clk), |
.wb_rst_i(rst), |
/trunk/bench/verilog/tb_tasks.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/21 21:39:27 lampret |
// Changed directory structure, port names and drfines. |
// |
// Revision 1.2 2001/07/14 20:37:23 lampret |
// Test bench improvements. |
// |
53,7 → 56,7
// |
|
`include "timescale.v" |
`include "defines.v" |
`include "gpio_defines.v" |
`include "tb_defines.v" |
|
module tb_tasks; |
677,7 → 680,7
#100; |
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// Sample interrupt request. Should be zero. |
l1 = tb_top.gpio.wb_inta_o; |
l1 = tb_top.gpio_top.wb_inta_o; |
|
// Clear gpio_in pins |
tb_top.gpio_mon.set_gpioin(0); |
686,7 → 689,7
#100; |
|
// Sample interrupt request. Should be one. |
l2 = tb_top.gpio.wb_inta_o; |
l2 = tb_top.gpio_top.wb_inta_o; |
|
// Clear interrupt request |
setctrl(0); |
695,7 → 698,7
#100; |
|
// Sample interrupt request. Should be zero. |
l3 = tb_top.gpio.wb_inta_o; |
l3 = tb_top.gpio_top.wb_inta_o; |
|
// Check for errors |
if (l1 || !l2 || l3) |
757,7 → 760,7
#100; |
|
// Sample interrupt request. Should be zero. |
l1 = tb_top.gpio.wb_inta_o; |
l1 = tb_top.gpio_top.wb_inta_o; |
|
// Clear gpio_in pins |
tb_top.gpio_mon.set_gpioin('hffffffff); |
766,7 → 769,7
#100; |
|
// Sample interrupt request. Should be one. |
l2 = tb_top.gpio.wb_inta_o; |
l2 = tb_top.gpio_top.wb_inta_o; |
|
// Clear interrupt request |
setctrl(0); |
775,7 → 778,7
#100; |
|
// Sample interrupt request. Should be zero. |
l3 = tb_top.gpio.wb_inta_o; |
l3 = tb_top.gpio_top.wb_inta_o; |
|
// Check for errors |
if (l1 || !l2 || l3) |
799,7 → 802,7
// |
// Do continues check for interrupts |
// |
always @(posedge tb_top.gpio.wb_inta_o) |
always @(posedge tb_top.gpio_top.wb_inta_o) |
if (ints_disabled) begin |
$display("Spurious interrupt detected. "); |
failed; |
/trunk/sim/rtl_sim/bin/sim.sh
12,7 → 12,7
# |
|
# Set simulation tool you are using (xl, ncsim, ncver) |
SIMTOOL=ncver |
SIMTOOL=ncsim |
|
# Set test bench top module(s) |
TB_TOP="tb_tasks" |