URL
https://opencores.org/ocsvn/gpio/gpio/trunk
Subversion Repositories gpio
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 36 to Rev 37
- ↔ Reverse comparison
Rev 36 → Rev 37
/trunk/bench/verilog/wb_master.v
1,4 → 1,5
`include "timescale.v" |
`include "gpio_defines.v" |
|
// -*- Mode: Verilog -*- |
// Filename : wb_master.v |
25,12 → 26,13
module wb_master(CLK_I, RST_I, TAG_I, TAG_O, |
ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O); |
|
parameter aw = `GPIO_ADDRHH+1 ; |
input CLK_I; |
input RST_I; |
input [3:0] TAG_I; |
output [3:0] TAG_O; |
input ACK_I; |
output [31:0] ADR_O; |
output [aw-1:0] ADR_O; |
output CYC_O; |
input [31:0] DAT_I; |
output [31:0] DAT_O; |
40,7 → 42,7
output STB_O; |
output WE_O; |
|
reg [31:0] ADR_O; |
reg [aw-1:0] ADR_O; |
reg [3:0] SEL_O; |
reg CYC_O; |
reg STB_O; |
/trunk/bench/verilog/gpio_mon.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2001/08/21 21:39:27 lampret |
// Changed directory structure, port names and drfines. |
// |
// Revision 1.2 2001/07/14 20:37:20 lampret |
// Test bench improvements. |
// |
53,10 → 56,11
// |
|
`include "timescale.v" |
`include "gpio_defines.v" |
|
module gpio_mon(gpio_aux, gpio_in, gpio_eclk, gpio_out, gpio_oen); |
|
parameter gw = 32; |
parameter gw = `GPIO_IOS; |
|
// |
// I/O ports |
/trunk/bench/verilog/tb_top.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/03/13 20:56:16 lampret |
// Removed zero padding as per Avi Shamli suggestion. |
// |
// Revision 1.2 2001/09/18 15:43:28 lampret |
// Changed gpio top level into gpio_top. Changed defines.v into gpio_defines.v. |
// |
63,7 → 66,7
|
module tb_top; |
|
parameter aw = 32; |
parameter aw = `GPIO_ADDRHH+1 ; |
parameter dw = 32; |
parameter gw = `GPIO_IOS; |
|
86,6 → 89,7
wire gpio_eclk; // GPIO external clock |
wire [gw-1:0] gpio_out; // GPIO outputs |
wire [gw-1:0] gpio_oen; // GPIO output enables |
wire [ 3 : 0 ] tag_o ; |
|
// |
// Instantiation of Clock/Reset Generator |
113,8 → 117,9
.DAT_I(dat_m), |
.ACK_I(ack), |
.ERR_I(err), |
.RTY_I(0), |
.TAG_I(4'b0) |
.RTY_I(1'b0), |
.TAG_I(4'b0), |
.TAG_O ( tag_o ) |
); |
|
// |
125,7 → 130,7
.wb_clk_i(clk), |
.wb_rst_i(rst), |
.wb_cyc_i(cyc), |
.wb_adr_i(adr[15:0]), |
.wb_adr_i(adr), |
.wb_dat_i(dat_ptc), |
.wb_sel_i(sel), |
.wb_we_i(we), |
/trunk/bench/verilog/tb_tasks.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2001/12/25 17:21:06 lampret |
// Fixed two typos. |
// |
// Revision 1.5 2001/12/25 17:12:28 lampret |
// Added RGPIO_INTS. |
// |
79,7 → 82,7
integer local_errs; |
|
parameter sh_addr = `GPIO_ADDRLH+1; |
|
parameter gw = `GPIO_IOS ; |
// |
// Count/report failed tests |
// |
96,8 → 99,16
task setout; |
input [31:0] val; |
|
reg [ 31:0 ] addr ; |
begin |
addr = `GPIO_RGPIO_OUT <<sh_addr ; |
#100 tb_top.wb_master.wr(`GPIO_RGPIO_OUT<<sh_addr, val, 4'b1111); |
/* $display ( " addr : %h %h", addr, val ) ; |
$display ( " out_pad : %h ", tb_top.gpio_top.out_pad ) ; |
$display ( " rgpio_aux : %h ", tb_top.gpio_top.rgpio_aux) ; |
$display ( " aux_i : %h ", tb_top.gpio_top.aux_i ) ; |
$display ( " rgpio_out : %h ", tb_top.gpio_top.rgpio_out ) ; |
*/ |
end |
|
endtask |
411,8 → 422,8
// Test operation of control bit RGPIO_CTRL[ECLK] |
// |
task test_eclk; |
integer l1, l2, l3; |
integer r1, r2, r3; |
reg [gw-1:0 ] l1, l2, l3; |
reg [gw-1:0 ] r1, r2, r3; |
begin |
|
// Set external clock to low state |
570,7 → 581,7
// Test input polled mode, output mode and bidirectional |
// |
task test_simple; |
integer l1, l2, l3, l4; |
reg [gw-1:0] l1, l2, l3, l4; |
integer i, err; |
begin |
$write(" Testing input mode ..."); |