URL
https://opencores.org/ocsvn/gpio/gpio/trunk
Subversion Repositories gpio
Compare Revisions
- This comparison shows the changes necessary to convert path
/gpio/tags/rel_15/sim
- from Rev 64 to Rev 65
- ↔ Reverse comparison
Rev 64 → Rev 65
/rtl_sim/log/ncelab.log
0,0 → 1,45
TOOL: ncelab 04.10-b001: Started on Dec 17, 2003 at 12:34:14 |
ncelab |
-f ncelab.args |
-MESSAGES |
-NOCOPYRIGHT |
-CDSLIB ../bin/cds.lib |
-HDLVAR ../bin/hdl.var |
-LOGFILE ../log/ncelab.log |
-SNAPSHOT worklib.bench:rtl |
-NO_TCHK_MSG |
-ACCESS +RWC |
worklib.tb_tasks |
worklib.gpio_testbench |
|
Elaborating the design hierarchy: |
Caching library 'worklib' ....... Done |
Building instance overlay tables: .................... Done |
Generating native compiled code: |
worklib.clkrst:v <0x67faf15a> |
streams: 2, words: 1034 |
worklib.gpio_mon:v <0x50b5485b> |
streams: 6, words: 1408 |
worklib.gpio_testbench:v <0x26ac113d> |
streams: 2, words: 300 |
worklib.gpio_top:v <0x566f67ec> |
streams: 205, words: 164573 |
worklib.tb_tasks:v <0x0ae72b6b> |
streams: 39, words: 57166 |
worklib.wb_master:v <0x008f4b18> |
streams: 38, words: 21666 |
Loading native compiled code: .................... Done |
Building instance specific data structures. |
Design hierarchy summary: |
Instances Unique |
Modules: 6 6 |
Registers: 130 130 |
Scalar wires: 85 - |
Vectored wires: 13 - |
Always blocks: 56 56 |
Initial blocks: 3 3 |
Cont. assignments: 40 79 |
Pseudo assignments: 2 49 |
Simulation timescale: 10ps |
Writing initial simulation snapshot: worklib.bench:rtl |
TOOL: ncelab 04.10-b001: Exiting on Dec 17, 2003 at 12:34:15 (total: 00:00:01) |
/rtl_sim/log/ncvlog.log
0,0 → 1,36
TOOL: ncvlog 04.10-b001: Started on Dec 17, 2003 at 12:34:13 |
ncvlog |
-f ncvlog.args |
-CDSLIB ../bin/cds.lib |
-HDLVAR ../bin/hdl.var |
-MESSAGES |
-INCDIR ../../../bench/verilog |
-INCDIR ../../../rtl/verilog |
-NOCOPYRIGHT |
-LOGFILE ../log/ncvlog.log |
../../../rtl/verilog/gpio_top.v |
../../../bench/verilog/clkrst.v |
../../../bench/verilog/gpio_mon.v |
../../../bench/verilog/wb_master.v |
../../../bench/verilog/tb_tasks.v |
../../../bench/verilog/gpio_testbench.v |
|
file: ../../../rtl/verilog/gpio_top.v |
module worklib.gpio_top:v |
errors: 0, warnings: 0 |
file: ../../../bench/verilog/clkrst.v |
module worklib.clkrst:v |
errors: 0, warnings: 0 |
file: ../../../bench/verilog/gpio_mon.v |
module worklib.gpio_mon:v |
errors: 0, warnings: 0 |
file: ../../../bench/verilog/wb_master.v |
module worklib.wb_master:v |
errors: 0, warnings: 0 |
file: ../../../bench/verilog/tb_tasks.v |
module worklib.tb_tasks:v |
errors: 0, warnings: 0 |
file: ../../../bench/verilog/gpio_testbench.v |
module worklib.gpio_testbench:v |
errors: 0, warnings: 0 |
TOOL: ncvlog 04.10-b001: Exiting on Dec 17, 2003 at 12:34:14 (total: 00:00:01) |
/rtl_sim/log/ncsim.log
0,0 → 1,47
TOOL: ncsim 04.10-b001: Started on Dec 17, 2003 at 12:34:15 |
ncsim |
-LICQUEUE |
-f ./ncsim.args |
-MESSAGES |
-NOCOPYRIGHT |
-CDSLIB ../bin/cds.lib |
-HDLVAR ../bin/hdl.var |
-INPUT ncsim.tcl |
-LOGFILE ../log/ncsim.log |
worklib.bench:rtl |
|
Loading snapshot worklib.bench:rtl .................... Done |
ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc |
ncsim> database -open waves -shm -into ../out/waves.shm |
Created SHM database waves |
ncsim> probe -create -database waves gpio_testbench -shm -all -depth all |
Created probe 1 |
ncsim> run |
|
### |
### GPIO IP Core Verification ### |
### |
|
I. Testing correct operation of RGPIO_CTRL control bits |
|
Testing control bit RGPIO_CTRL[ECLK] ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... OK |
Testing control bit RGPIO_CTRL[NEC] ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... OK |
Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ... OK |
|
II. Testing modes of operation ... |
|
Testing input mode ... OK |
Testing output mode ... OK |
Testing bidirectional I/O ... OK |
Testing auxiliary feature ... OK |
Testing ptrig features ... OK |
|
### |
### FAILED TESTS: 0 ### |
### |
|
report (deaddead) |
exit (00000000) |
/projects/highland/gorand/gpio/bench/verilog/tb_tasks.v:1095 $finish(0); |
ncsim> quit |
TOOL: ncsim 04.10-b001: Exiting on Dec 17, 2003 at 12:35:10 (total: 00:00:55) |
/rtl_sim/run/ncsim.tcl
0,0 → 1,4
database -open waves -shm -into ../out/waves.shm |
probe -create -database waves gpio_testbench -shm -all -depth all |
run |
quit |
/rtl_sim/run/run_sim_gpio
0,0 → 1,102
#!/bin/csh -f |
|
if ( $# < 1 ) then |
echo "First argument must be a top level module name!" |
exit |
else |
set SIM_TOP = $1 |
endif |
|
set current_par = 1 |
set output_waveform = 0 |
while ( $current_par < $# ) |
@ current_par = $current_par + 1 |
case wave: |
@ output_waveform = 1 |
breaksw |
default: |
echo 'Unknown option "'$argv[$current_par]'"!' |
exit |
breaksw |
endsw |
end |
|
echo "-CDSLIB ../bin/cds.lib" > ncvlog.args |
echo "-HDLVAR ../bin/hdl.var" >> ncvlog.args |
echo "-MESSAGES" >> ncvlog.args |
echo "-INCDIR ../../../bench/verilog" >> ncvlog.args |
echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args |
echo "-NOCOPYRIGHT" >> ncvlog.args |
echo "-LOGFILE ../log/ncvlog.log" >> ncvlog.args |
|
foreach filename ( `cat ../bin/rtl_file_list` ) |
echo "../../../rtl/verilog/"$filename >> ncvlog.args |
end |
|
foreach filename ( `cat ../bin/sim_file_list` ) |
echo "../../../bench/verilog/"$filename >> ncvlog.args |
end |
|
ncvlog -f ncvlog.args |
|
echo "-MESSAGES" > ncelab.args |
echo "-NOCOPYRIGHT" >> ncelab.args |
echo "-CDSLIB ../bin/cds.lib" >> ncelab.args |
echo "-HDLVAR ../bin/hdl.var" >> ncelab.args |
echo "-LOGFILE ../log/ncelab.log" >> ncelab.args |
echo "-SNAPSHOT worklib.bench:rtl" >> ncelab.args |
echo "-NO_TCHK_MSG" >> ncelab.args |
echo "-ACCESS +RWC" >> ncelab.args |
echo "worklib.tb_tasks" >> ncelab.args |
echo worklib.$SIM_TOP >> ncelab.args |
|
ncelab -f ncelab.args |
|
echo "-MESSAGES" > ncsim.args |
echo "-NOCOPYRIGHT" >> ncsim.args |
echo "-CDSLIB ../bin/cds.lib" >> ncsim.args |
echo "-HDLVAR ../bin/hdl.var" >> ncsim.args |
echo "-INPUT ncsim.tcl" >> ncsim.args |
echo "-LOGFILE ../log/ncsim.log" >> ncsim.args |
echo "worklib.bench:rtl" >> ncsim.args |
|
if ( $output_waveform ) then |
echo "database -open waves -shm -into ../out/waves.shm" > ./ncsim.tcl |
echo "probe -create -database waves $SIM_TOP -shm -all -depth all" >> ./ncsim.tcl |
echo "run" >> ./ncsim.tcl |
else |
echo "run" > ./ncsim.tcl |
endif |
|
echo "quit" >> ncsim.tcl |
|
ncsim -LICQUEUE -f ./ncsim.args |
|
set exit_line_nb = `sed -n '/exit/=' < ../log/ncsim.log` |
|
#echo "$exit_line_nb" |
|
set dead_line_nb = 0 |
|
if ( $exit_line_nb ) then |
|
@ dead_line_nb = $exit_line_nb - 1 |
set exit_line=`sed -n $exit_line_nb's/exit/&/gp' < ../log/ncsim.log` |
set dead_line=`sed -n $dead_line_nb's/report/&/gp' < ../log/ncsim.log` |
|
echo "$dead_line" |
echo "$exit_line" |
|
echo "TEST: gpio" |
if ( "$dead_line" == "report (deaddead)" ) then |
if ( "$exit_line" == "exit (00000000)" ) then |
echo "STATUS: passed" #|tee -a ../log/run_sim.log 2>&1 |
else |
echo "STATUS: failed" #|tee -a ../log/run_sim.log 2>&1 |
endif |
else |
echo "STATUS: failed" |
endif |
|
endif |
|
rtl_sim/run/run_sim_gpio
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl_sim/run/run_sim
===================================================================
--- rtl_sim/run/run_sim (nonexistent)
+++ rtl_sim/run/run_sim (revision 65)
@@ -0,0 +1,3 @@
+#!/bin/sh
+./run_sim_gpio gpio_testbench
+
rtl_sim/run/run_sim
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl_sim/run/ncelab.args
===================================================================
--- rtl_sim/run/ncelab.args (nonexistent)
+++ rtl_sim/run/ncelab.args (revision 65)
@@ -0,0 +1,10 @@
+-MESSAGES
+-NOCOPYRIGHT
+-CDSLIB ../bin/cds.lib
+-HDLVAR ../bin/hdl.var
+-LOGFILE ../log/ncelab.log
+-SNAPSHOT worklib.bench:rtl
+-NO_TCHK_MSG
+-ACCESS +RWC
+worklib.tb_tasks
+worklib.gpio_testbench
Index: rtl_sim/run/ncvlog.args
===================================================================
--- rtl_sim/run/ncvlog.args (nonexistent)
+++ rtl_sim/run/ncvlog.args (revision 65)
@@ -0,0 +1,13 @@
+-CDSLIB ../bin/cds.lib
+-HDLVAR ../bin/hdl.var
+-MESSAGES
+-INCDIR ../../../bench/verilog
+-INCDIR ../../../rtl/verilog
+-NOCOPYRIGHT
+-LOGFILE ../log/ncvlog.log
+../../../rtl/verilog/gpio_top.v
+../../../bench/verilog/clkrst.v
+../../../bench/verilog/gpio_mon.v
+../../../bench/verilog/wb_master.v
+../../../bench/verilog/tb_tasks.v
+../../../bench/verilog/gpio_testbench.v
Index: rtl_sim/run/ncsim.args
===================================================================
--- rtl_sim/run/ncsim.args (nonexistent)
+++ rtl_sim/run/ncsim.args (revision 65)
@@ -0,0 +1,7 @@
+-MESSAGES
+-NOCOPYRIGHT
+-CDSLIB ../bin/cds.lib
+-HDLVAR ../bin/hdl.var
+-INPUT ncsim.tcl
+-LOGFILE ../log/ncsim.log
+worklib.bench:rtl
Index: rtl_sim/bin/INCA_libs/worklib/dir_keeper
===================================================================
Index: rtl_sim/bin/sim_file_list
===================================================================
--- rtl_sim/bin/sim_file_list (nonexistent)
+++ rtl_sim/bin/sim_file_list (revision 65)
@@ -0,0 +1,7 @@
+clkrst.v
+gpio_mon.v
+wb_master.v
+tb_tasks.v
+gpio_testbench.v
+
+
rtl_sim/bin/sim_file_list
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl_sim/bin/sim.sh
===================================================================
--- rtl_sim/bin/sim.sh (nonexistent)
+++ rtl_sim/bin/sim.sh (revision 65)
@@ -0,0 +1,125 @@
+#!/bin/bash
+
+#
+# This script runs RTL and gate-level simulation using different simultion tools.
+# Right now Cadence Verilog-XL and NCSim are supported.
+#
+# Author: Damjan Lampret
+#
+
+#
+# User definitions
+#
+
+# Set simulation tool you are using (xl, ncsim, ncver)
+SIMTOOL=ncsim
+
+# Set test bench top module(s)
+TB_TOP="tb_tasks"
+
+# Set include directories
+INCLUDE_DIRS="../../../rtl/verilog/ ../../../bench/verilog/"
+
+# Set test bench files
+BENCH_FILES="../../../bench/verilog/*.v"
+
+# Set RTL source files
+RTL_FILES="../../../rtl/verilog/*.v"
+
+# Set gate-level netlist files
+GATE_FILES="../syn/out/final_gpio.v"
+
+# Set libraries (standard cell etc.)
+LIB_FILES="/libs/Virtual_silicon/UMCL18U250D2_2.1/verilog_simulation_models/*.v"
+
+# Set parameters for simulation tool
+if [ $SIMTOOL == xl ]; then
+ PARAM="+turbo+3 -q"
+ for i in $INCLUDE_DIRS; do
+ INCDIR=$INCDIR" +incdir+$i"
+ done
+elif [ $SIMTOOL == ncver ]; then
+ NCVER_PARAM=""
+ for i in $INCLUDE_DIRS; do
+ INCDIR=$INCDIR" +incdir+$i"
+ done
+elif [ $SIMTOOL == ncsim ]; then
+ NCPREP_PARAM="-UPDATE +overwrite"
+ NCSIM_PARAM="-MESSAGES -NOCOPYRIGHT"
+ for i in $INCLUDE_DIRS; do
+ INCDIR=$INCDIR" +incdir+$i"
+ done
+else
+ echo "$SIMTOOL is unsupported simulation tool."
+ exit 0
+fi
+
+#
+# Don't change anything below unless you know what you are doing
+#
+
+# Run simulation in sim directory
+#cd ../sim
+
+# Run actual simulation
+
+# Cadence Verilog-XL
+if [ $SIMTOOL == xl ]; then
+
+ # RTL simulation
+ if [ "$1" == rtl ]; then
+ verilog $PARAM $INCDIR $BENCH_FILES $RTL_FILES
+
+ # Gate-level simulation
+ elif [ "$1" == gate ]; then
+ verilog $PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
+
+ # Wrong parameter or no parameter
+ else
+ echo "Usage: $0 [rtl|gate]"
+ exit 0
+ fi
+
+# Cadence Ncverilog
+elif [ $SIMTOOL == ncver ]; then
+
+ # RTL simulation
+ if [ "$1" == rtl ]; then
+ ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $RTL_FILES
+ cp ncverilog.log ../log
+
+ # Gate-level simulation
+ elif [ "$1" == gate ]; then
+ ncverilog $NCVER_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
+ cp ncverilog.log ../log
+
+ # Wrong parameter or no parameter
+ else
+ echo "Usage: $0 [rtl|gate]"
+ exit 0
+ fi
+
+# Cadence Ncsim
+elif [ $SIMTOOL == ncsim ]; then
+
+ # RTL simulation
+ if [ "$1" == rtl ]; then
+ ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $RTL_FILES
+ ./RUN_NC
+
+ # Gate-level simulation
+ elif [ "$1" == gate ]; then
+ ncprep $NCPREP_PARAM $INCDIR $BENCH_FILES $GATE_FILES $LIB_FILES
+ ./RUN_NC
+
+ # Wrong parameter or no parameter
+ else
+ echo "Usage: $0 [rtl|gate]"
+ exit 0
+ fi
+
+# Unsupported simulation tool
+else
+ echo "$SIMTOOL is unsupported simulation tool."
+ exit 0;
+fi
rtl_sim/bin/sim.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl_sim/bin/rtl_file_list
===================================================================
--- rtl_sim/bin/rtl_file_list (nonexistent)
+++ rtl_sim/bin/rtl_file_list (revision 65)
@@ -0,0 +1 @@
+gpio_top.v
rtl_sim/bin/rtl_file_list
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl_sim/bin/cds.lib
===================================================================
--- rtl_sim/bin/cds.lib (nonexistent)
+++ rtl_sim/bin/cds.lib (revision 65)
@@ -0,0 +1,6 @@
+#
+# cds.lib: Defines the locations of compiled libraries.
+# Created by ncprep on Tue Nov 11 00:24:06 2003
+#
+
+define worklib ./INCA_libs/worklib
Index: rtl_sim/bin/hdl.var
===================================================================
--- rtl_sim/bin/hdl.var (nonexistent)
+++ rtl_sim/bin/hdl.var (revision 65)
@@ -0,0 +1,9 @@
+#
+# hdl.var: Defines variables used by the INCA tools.
+# Created by ncprep on Tue Nov 11 00:24:06 2003
+#
+
+softinclude $CDS_INST_DIR/tools/inca/files/hdl.var
+
+define LIB_MAP ( $LIB_MAP, + => worklib )
+define VIEW_MAP ( $VIEW_MAP, .v => v)