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URL https://opencores.org/ocsvn/gpio/gpio/trunk

Subversion Repositories gpio

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /gpio/trunk/sim/rtl_sim/log
    from Rev 56 to Rev 65
    ↔ Reverse comparison
  •

Rev 56 → Rev 65

/ncelab.log
0,0 → 1,45
TOOL: ncelab 04.10-b001: Started on Dec 17, 2003 at 12:34:14
ncelab
-f ncelab.args
-MESSAGES
-NOCOPYRIGHT
-CDSLIB ../bin/cds.lib
-HDLVAR ../bin/hdl.var
-LOGFILE ../log/ncelab.log
-SNAPSHOT worklib.bench:rtl
-NO_TCHK_MSG
-ACCESS +RWC
worklib.tb_tasks
worklib.gpio_testbench
 
Elaborating the design hierarchy:
Caching library 'worklib' ....... Done
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.clkrst:v <0x67faf15a>
streams: 2, words: 1034
worklib.gpio_mon:v <0x50b5485b>
streams: 6, words: 1408
worklib.gpio_testbench:v <0x26ac113d>
streams: 2, words: 300
worklib.gpio_top:v <0x566f67ec>
streams: 205, words: 164573
worklib.tb_tasks:v <0x0ae72b6b>
streams: 39, words: 57166
worklib.wb_master:v <0x008f4b18>
streams: 38, words: 21666
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 6 6
Registers: 130 130
Scalar wires: 85 -
Vectored wires: 13 -
Always blocks: 56 56
Initial blocks: 3 3
Cont. assignments: 40 79
Pseudo assignments: 2 49
Simulation timescale: 10ps
Writing initial simulation snapshot: worklib.bench:rtl
TOOL: ncelab 04.10-b001: Exiting on Dec 17, 2003 at 12:34:15 (total: 00:00:01)
/ncvlog.log
0,0 → 1,36
TOOL: ncvlog 04.10-b001: Started on Dec 17, 2003 at 12:34:13
ncvlog
-f ncvlog.args
-CDSLIB ../bin/cds.lib
-HDLVAR ../bin/hdl.var
-MESSAGES
-INCDIR ../../../bench/verilog
-INCDIR ../../../rtl/verilog
-NOCOPYRIGHT
-LOGFILE ../log/ncvlog.log
../../../rtl/verilog/gpio_top.v
../../../bench/verilog/clkrst.v
../../../bench/verilog/gpio_mon.v
../../../bench/verilog/wb_master.v
../../../bench/verilog/tb_tasks.v
../../../bench/verilog/gpio_testbench.v
 
file: ../../../rtl/verilog/gpio_top.v
module worklib.gpio_top:v
errors: 0, warnings: 0
file: ../../../bench/verilog/clkrst.v
module worklib.clkrst:v
errors: 0, warnings: 0
file: ../../../bench/verilog/gpio_mon.v
module worklib.gpio_mon:v
errors: 0, warnings: 0
file: ../../../bench/verilog/wb_master.v
module worklib.wb_master:v
errors: 0, warnings: 0
file: ../../../bench/verilog/tb_tasks.v
module worklib.tb_tasks:v
errors: 0, warnings: 0
file: ../../../bench/verilog/gpio_testbench.v
module worklib.gpio_testbench:v
errors: 0, warnings: 0
TOOL: ncvlog 04.10-b001: Exiting on Dec 17, 2003 at 12:34:14 (total: 00:00:01)
/ncsim.log
0,0 → 1,47
TOOL: ncsim 04.10-b001: Started on Dec 17, 2003 at 12:34:15
ncsim
-LICQUEUE
-f ./ncsim.args
-MESSAGES
-NOCOPYRIGHT
-CDSLIB ../bin/cds.lib
-HDLVAR ../bin/hdl.var
-INPUT ncsim.tcl
-LOGFILE ../log/ncsim.log
worklib.bench:rtl
 
Loading snapshot worklib.bench:rtl .................... Done
ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc
ncsim> database -open waves -shm -into ../out/waves.shm
Created SHM database waves
ncsim> probe -create -database waves gpio_testbench -shm -all -depth all
Created probe 1
ncsim> run
 
###
### GPIO IP Core Verification ###
###
 
I. Testing correct operation of RGPIO_CTRL control bits
 
Testing control bit RGPIO_CTRL[ECLK] ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... OK
Testing control bit RGPIO_CTRL[NEC] ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... OK
Testing control bit RGPIO_CTRL[INTE] and RGPIO_CTRL[INT] ... OK
 
II. Testing modes of operation ...
 
Testing input mode ... OK
Testing output mode ... OK
Testing bidirectional I/O ... OK
Testing auxiliary feature ... OK
Testing ptrig features ... OK
 
###
### FAILED TESTS: 0 ###
###
 
report (deaddead)
exit (00000000)
/projects/highland/gorand/gpio/bench/verilog/tb_tasks.v:1095 $finish(0);
ncsim> quit
TOOL: ncsim 04.10-b001: Exiting on Dec 17, 2003 at 12:35:10 (total: 00:00:55)

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