URL
https://opencores.org/ocsvn/gpio/gpio/trunk
Subversion Repositories gpio
Compare Revisions
- This comparison shows the changes necessary to convert path
/gpio/trunk/sim/rtl_sim/run
- from Rev 56 to Rev 65
- ↔ Reverse comparison
Rev 56 → Rev 65
/ncsim.tcl
0,0 → 1,4
database -open waves -shm -into ../out/waves.shm |
probe -create -database waves gpio_testbench -shm -all -depth all |
run |
quit |
/run_sim_gpio
0,0 → 1,102
#!/bin/csh -f |
|
if ( $# < 1 ) then |
echo "First argument must be a top level module name!" |
exit |
else |
set SIM_TOP = $1 |
endif |
|
set current_par = 1 |
set output_waveform = 0 |
while ( $current_par < $# ) |
@ current_par = $current_par + 1 |
case wave: |
@ output_waveform = 1 |
breaksw |
default: |
echo 'Unknown option "'$argv[$current_par]'"!' |
exit |
breaksw |
endsw |
end |
|
echo "-CDSLIB ../bin/cds.lib" > ncvlog.args |
echo "-HDLVAR ../bin/hdl.var" >> ncvlog.args |
echo "-MESSAGES" >> ncvlog.args |
echo "-INCDIR ../../../bench/verilog" >> ncvlog.args |
echo "-INCDIR ../../../rtl/verilog" >> ncvlog.args |
echo "-NOCOPYRIGHT" >> ncvlog.args |
echo "-LOGFILE ../log/ncvlog.log" >> ncvlog.args |
|
foreach filename ( `cat ../bin/rtl_file_list` ) |
echo "../../../rtl/verilog/"$filename >> ncvlog.args |
end |
|
foreach filename ( `cat ../bin/sim_file_list` ) |
echo "../../../bench/verilog/"$filename >> ncvlog.args |
end |
|
ncvlog -f ncvlog.args |
|
echo "-MESSAGES" > ncelab.args |
echo "-NOCOPYRIGHT" >> ncelab.args |
echo "-CDSLIB ../bin/cds.lib" >> ncelab.args |
echo "-HDLVAR ../bin/hdl.var" >> ncelab.args |
echo "-LOGFILE ../log/ncelab.log" >> ncelab.args |
echo "-SNAPSHOT worklib.bench:rtl" >> ncelab.args |
echo "-NO_TCHK_MSG" >> ncelab.args |
echo "-ACCESS +RWC" >> ncelab.args |
echo "worklib.tb_tasks" >> ncelab.args |
echo worklib.$SIM_TOP >> ncelab.args |
|
ncelab -f ncelab.args |
|
echo "-MESSAGES" > ncsim.args |
echo "-NOCOPYRIGHT" >> ncsim.args |
echo "-CDSLIB ../bin/cds.lib" >> ncsim.args |
echo "-HDLVAR ../bin/hdl.var" >> ncsim.args |
echo "-INPUT ncsim.tcl" >> ncsim.args |
echo "-LOGFILE ../log/ncsim.log" >> ncsim.args |
echo "worklib.bench:rtl" >> ncsim.args |
|
if ( $output_waveform ) then |
echo "database -open waves -shm -into ../out/waves.shm" > ./ncsim.tcl |
echo "probe -create -database waves $SIM_TOP -shm -all -depth all" >> ./ncsim.tcl |
echo "run" >> ./ncsim.tcl |
else |
echo "run" > ./ncsim.tcl |
endif |
|
echo "quit" >> ncsim.tcl |
|
ncsim -LICQUEUE -f ./ncsim.args |
|
set exit_line_nb = `sed -n '/exit/=' < ../log/ncsim.log` |
|
#echo "$exit_line_nb" |
|
set dead_line_nb = 0 |
|
if ( $exit_line_nb ) then |
|
@ dead_line_nb = $exit_line_nb - 1 |
set exit_line=`sed -n $exit_line_nb's/exit/&/gp' < ../log/ncsim.log` |
set dead_line=`sed -n $dead_line_nb's/report/&/gp' < ../log/ncsim.log` |
|
echo "$dead_line" |
echo "$exit_line" |
|
echo "TEST: gpio" |
if ( "$dead_line" == "report (deaddead)" ) then |
if ( "$exit_line" == "exit (00000000)" ) then |
echo "STATUS: passed" #|tee -a ../log/run_sim.log 2>&1 |
else |
echo "STATUS: failed" #|tee -a ../log/run_sim.log 2>&1 |
endif |
else |
echo "STATUS: failed" |
endif |
|
endif |
|
run_sim_gpio
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: run_sim
===================================================================
--- run_sim (nonexistent)
+++ run_sim (revision 65)
@@ -0,0 +1,3 @@
+#!/bin/sh
+./run_sim_gpio gpio_testbench
+
run_sim
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ncelab.args
===================================================================
--- ncelab.args (nonexistent)
+++ ncelab.args (revision 65)
@@ -0,0 +1,10 @@
+-MESSAGES
+-NOCOPYRIGHT
+-CDSLIB ../bin/cds.lib
+-HDLVAR ../bin/hdl.var
+-LOGFILE ../log/ncelab.log
+-SNAPSHOT worklib.bench:rtl
+-NO_TCHK_MSG
+-ACCESS +RWC
+worklib.tb_tasks
+worklib.gpio_testbench
Index: ncvlog.args
===================================================================
--- ncvlog.args (nonexistent)
+++ ncvlog.args (revision 65)
@@ -0,0 +1,13 @@
+-CDSLIB ../bin/cds.lib
+-HDLVAR ../bin/hdl.var
+-MESSAGES
+-INCDIR ../../../bench/verilog
+-INCDIR ../../../rtl/verilog
+-NOCOPYRIGHT
+-LOGFILE ../log/ncvlog.log
+../../../rtl/verilog/gpio_top.v
+../../../bench/verilog/clkrst.v
+../../../bench/verilog/gpio_mon.v
+../../../bench/verilog/wb_master.v
+../../../bench/verilog/tb_tasks.v
+../../../bench/verilog/gpio_testbench.v
Index: ncsim.args
===================================================================
--- ncsim.args (nonexistent)
+++ ncsim.args (revision 65)
@@ -0,0 +1,7 @@
+-MESSAGES
+-NOCOPYRIGHT
+-CDSLIB ../bin/cds.lib
+-HDLVAR ../bin/hdl.var
+-INPUT ncsim.tcl
+-LOGFILE ../log/ncsim.log
+worklib.bench:rtl