OpenCores
URL https://opencores.org/ocsvn/hf-risc/hf-risc/trunk

Subversion Repositories hf-risc

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 20 to Rev 21
    Reverse comparison

Rev 20 → Rev 21

/hf-risc/trunk/software/app/interrupt_test.c
1,6 → 1,6
#include <hf-risc.h>
 
volatile int32_t ccount=0, ccount2=0, cmpcount=0, cmp2count=0, irq0count=0, irq1count=0;
volatile int32_t ccount=0, ccount2=0, cmpcount=0, cmp2count=0;
 
/*
ISRs - interrupt service routines
41,14 → 41,6
COMPARE2 = val; // update compare2 reg, clear irq
}
 
void irq0_handler(void){
irq0count++;
}
 
void irq1_handler(void){
irq1count++;
}
 
int main(void){
// register ISRs
interrupt_register(IRQ_COUNTER, counter_handler);
57,8 → 49,6
interrupt_register(IRQ_COUNTER2_NOT, counter_handler2);
interrupt_register(IRQ_COMPARE, compare_handler);
interrupt_register(IRQ_COMPARE2, compare2_handler);
interrupt_register(EXT_IRQ0, irq0_handler);
interrupt_register(EXT_IRQ1, irq1_handler);
 
// initialize compare registers, clear compare irqs
COMPARE = COUNTER + (CPU_SPEED/1000) * 5;
65,15 → 55,15
COMPARE2 = COUNTER + (CPU_SPEED/1000) * 1;
 
// set interrupt mask (unmask peripheral interrupts)
IRQ_MASK = (IRQ_COUNTER | IRQ_COUNTER2 | IRQ_COMPARE | IRQ_COMPARE2 | EXT_IRQ0 | EXT_IRQ1);
IRQ_MASK = (IRQ_COUNTER | IRQ_COUNTER2 | IRQ_COMPARE | IRQ_COMPARE2);
 
// global interrupts enable
IRQ_STATUS = 1;
 
ccount=0; ccount2=0; cmpcount=0; cmp2count=0; irq0count=0; irq1count=0;
ccount=0; ccount2=0; cmpcount=0; cmp2count=0;
 
for(;;){
printf("\ninterrupts -> counter18: %d counter16: %d compare: %d compare2: %d ext_irq0: %d ext_irq1: %d", ccount, ccount2, cmpcount, cmp2count, irq0count, irq1count);
printf("\ninterrupts -> counter18: %d counter16: %d compare: %d compare2: %d", ccount, ccount2, cmpcount, cmp2count);
}
}
 

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