URL
https://opencores.org/ocsvn/i2c/i2c/trunk
Subversion Repositories i2c
Compare Revisions
- This comparison shows the changes necessary to convert path
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- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/trunk/rtl/verilog/i2c_master_defines.v
6,9 → 6,3
`define I2C_CMD_STOP 4'b0010 |
`define I2C_CMD_WRITE 4'b0100 |
`define I2C_CMD_READ 4'b1000 |
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// asynchronous reset level |
// I2C_RST_LVL == 1'b0 asynchronous active low reset |
// I2C_RST_LVL == 1'b1 asynchronous active high reset |
`define I2C_RST_LVL 1'b0 |
/trunk/rtl/verilog/i2c_master_top.v
13,6 → 13,9
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o, |
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o ); |
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// parameters |
parameter ARST_LVL = 1'b0; // asynchronous reset level |
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// |
// inputs & outputs |
// |
73,7 → 76,7
// |
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// generate internal reset |
wire rst_i = arst_i ^ `I2C_RST_LVL; |
wire rst_i = arst_i ^ ARST_LVL; |
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// generate acknowledge output signal |
assign wb_ack_o = wb_cyc_i && wb_stb_i; // because timing is always honored |
216,3 → 219,4
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