OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 24 to Rev 25
    ↔ Reverse comparison
  •

Rev 24 → Rev 25

/trunk/bench/verilog/tst_bench_top.v
37,10 → 37,10
 
// CVS Log
//
// $Id: tst_bench_top.v,v 1.2 2002-03-17 10:26:38 rherveille Exp $
// $Id: tst_bench_top.v,v 1.3 2002-10-30 18:11:06 rherveille Exp $
//
// $Date: 2002-03-17 10:26:38 $
// $Revision: 1.2 $
// $Date: 2002-10-30 18:11:06 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
47,6 → 47,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/03/17 10:26:38 rherveille
// Fixed some race conditions in the i2c-slave model.
// Added debug information.
// Added headers.
//
 
`include "timescale.v"
 
144,277 → 149,248
pullup p2(sda); // pullup sda line
 
initial
begin
// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
force i2c_slave.debug = 1'b0; // disable i2c_slave debug information
begin
`ifdef WAVES
$shm_open("waves");
$shm_probe("AS",tst_bench_top,"AS");
$display("INFO: Signal dump enabled ...\n\n");
`endif
 
$display("\nstatus: %t Testbench started\n\n", $time);
// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
force i2c_slave.debug = 1'b0; // disable i2c_slave debug information
 
$dumpfile("bench.vcd");
$dumpvars(1, tst_bench_top);
$dumpvars(1, tst_bench_top.i2c_slave);
$display("\nstatus: %t Testbench started\n\n", $time);
 
// initially values
clk = 0;
// $dumpfile("bench.vcd");
// $dumpvars(1, tst_bench_top);
// $dumpvars(1, tst_bench_top.i2c_slave);
 
// reset system
rstn = 1'b1; // negate reset
#2;
rstn = 1'b0; // assert reset
repeat(20) @(posedge clk);
rstn = 1'b1; // negate reset
// initially values
clk = 0;
 
$display("status: %t done reset", $time);
@(posedge clk);
// reset system
rstn = 1'b1; // negate reset
#2;
rstn = 1'b0; // assert reset
repeat(20) @(posedge clk);
rstn = 1'b1; // negate reset
 
//
// program core
//
$display("status: %t done reset", $time);
 
// program internal registers
// u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
u0.wb_write(1, PRER_LO, 8'h3e); // load prescaler lo-byte
u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
@(posedge clk);
 
$display("status: %t programmed registers", $time);
//
// program core
//
 
u0.wb_cmp(0, PRER_LO, 8'h3e); // verify prescaler lo-byte
u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
// program internal registers
// u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
$display("status: %t programmed registers", $time);
 
$display("status: %t verified registers", $time);
u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
$display("status: %t verified registers", $time);
 
u0.wb_write(1, CTR, 8'h80); // enable core
u0.wb_write(1, CTR, 8'h80); // enable core
$display("status: %t core enabled", $time);
 
$display("status: %t enabled core", $time);
//
// access slave (write)
//
 
//
// access slave (write)
//
// drive slave address
u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
u0.wb_write(0, CR, 8'h90); // set command (start, write)
$display("status: %t generate 'start', write cmd a0 (slave address+write)", $time);
 
// drive slave address
u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
u0.wb_write(0, CR, 8'h90); // set command (start, write)
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(0, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
$display("status: %t generate 'start', write cmd a0 (slave address+write)", $time);
// send memory address
u0.wb_write(1, TXR, 8'h01); // present slave's memory address
u0.wb_write(0, CR, 8'h10); // set command (write)
$display("status: %t write slave memory address 01", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while (q[1])
u0.wb_read(0, SR, q); // poll it until it is zero
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(0, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
$display("status: %t tip==0", $time);
// send memory contents
u0.wb_write(1, TXR, 8'ha5); // present data
u0.wb_write(0, CR, 8'h10); // set command (write)
$display("status: %t write data a5", $time);
 
// send memory address
u0.wb_write(1, TXR, 8'h01); // present slave's memory address
u0.wb_write(0, CR, 8'h10); // set command (write)
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
$display("status: %t write slave memory address 01", $time);
// send memory contents for next memory address (auto_inc)
u0.wb_write(1, TXR, 8'h5a); // present data
u0.wb_write(0, CR, 8'h50); // set command (stop, write)
$display("status: %t write next data 5a, generate 'stop'", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while (q[1])
u0.wb_read(0, SR, q); // poll it until it is zero
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
$display("status: %t tip==0", $time);
//
// delay
//
// #100000; // wait for 100us.
// $display("status: %t wait 100us", $time);
 
// send memory contents
u0.wb_write(1, TXR, 8'ha5); // present data
u0.wb_write(0, CR, 8'h10); // set command (write)
//
// access slave (read)
//
 
$display("status: %t write data a5", $time);
// drive slave address
u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
u0.wb_write(0, CR, 8'h90); // set command (start, write)
$display("status: %t generate 'start', write cmd a0 (slave address+write)", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while (q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
$display("status: %t tip==0", $time);
// send memory address
u0.wb_write(1, TXR, 8'h01); // present slave's memory address
u0.wb_write(0, CR, 8'h10); // set command (write)
$display("status: %t write slave address 01", $time);
 
// send memory contents for next memory address (auto_inc)
u0.wb_write(1, TXR, 8'h5a); // present data
u0.wb_write(0, CR, 8'h50); // set command (stop, write)
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
$display("status: %t write next data 5a, generate 'stop'", $time);
// drive slave address
u0.wb_write(1, TXR, 8'ha1); // present slave's address, set read-bit
u0.wb_write(0, CR, 8'h90); // set command (start, write)
$display("status: %t generate 'repeated start', write cmd a1 (slave address+read)", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while (q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
$display("status: %t tip==0", $time);
// read data from slave
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
$display("status: %t read + ack", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
//
// delay
//
#100000; // wait for 100us.
// check data just received
u0.wb_read(1, RXR, qq);
if(qq !== 8'ha5)
$display("\nERROR: Expected a5, received %x at time %t", qq, $time);
 
$display("status: %t wait 100us", $time);
// read data from slave
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
$display("status: %t read + ack", $time);
 
//
// access slave (read)
//
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// drive slave address
u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
u0.wb_write(0, CR, 8'h90); // set command (start, write)
// check data just received
u0.wb_read(1, RXR, qq);
if(qq !== 8'h5a)
$display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
 
$display("status: %t generate 'start', write cmd a0 (slave address+write)", $time);
// read data from slave
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
$display("status: %t read + ack", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while (q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
$display("status: %t tip==0", $time);
// check data just received
u0.wb_read(1, RXR, qq);
$display("status: %t received %x from 3rd read address", $time, qq);
 
// send memory address
u0.wb_write(1, TXR, 8'h01); // present slave's memory address
u0.wb_write(0, CR, 8'h10); // set command (write)
// read data from slave
u0.wb_write(1, CR, 8'h28); // set command (read, nack_read)
$display("status: %t read + nack", $time);
 
$display("status: %t write slave address 01", $time);
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while (q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
// check data just received
u0.wb_read(1, RXR, qq);
$display("status: %t received %x from 4th read address", $time, qq);
 
$display("status: %t tip==0", $time);
//
// check invalid slave memory address
//
 
// drive slave address
u0.wb_write(1, TXR, 8'ha1); // present slave's address, set read-bit
u0.wb_write(0, CR, 8'h90); // set command (start, write)
// drive slave address
u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
u0.wb_write(0, CR, 8'h90); // set command (start, write)
$display("status: %t generate 'start', write cmd a0 (slave address+write). Check invalid address", $time);
 
$display("status: %t generate 'repeated start', write cmd a1 (slave address+read)", $time);
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while (q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
// send memory address
u0.wb_write(1, TXR, 8'h10); // present slave's memory address
u0.wb_write(0, CR, 8'h10); // set command (write)
$display("status: %t write slave memory address 10", $time);
 
$display("status: %t tip==0", $time);
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
// read data from slave
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
// slave should have send NACK
$display("status: %t Check for nack", $time);
if(!q[7])
$display("\nERROR: Expected NACK, received ACK\n");
 
$display("status: %t read + ack", $time);
// read data from slave
u0.wb_write(1, CR, 8'h40); // set command (stop)
$display("status: %t generate 'stop'", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while (q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
 
$display("status: %t tip==0", $time);
#25000; // wait 25us
$display("\n\nstatus: %t Testbench done", $time);
$finish;
end
 
// check data just received
u0.wb_read(1, RXR, qq);
if (qq !== 8'ha5)
$display("\nERROR: Expected a5, received %x at time %t", qq, $time);
 
// read data from slave
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
 
$display("status: %t read + ack", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while (q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
 
$display("status: %t tip==0", $time);
 
// check data just received
u0.wb_read(1, RXR, qq);
if (qq !== 8'h5a)
$display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
 
// read data from slave
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
 
$display("status: %t read + ack", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while (q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
 
$display("status: %t tip==0", $time);
 
// check data just received
u0.wb_read(1, RXR, qq);
$display("status: %t received %x from 3rd read address", $time, qq);
 
// read data from slave
u0.wb_write(1, CR, 8'h28); // set command (read, nack_read)
$display("status: %t read + nack", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while (q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
 
$display("status: %t tip==0", $time);
 
// check data just received
u0.wb_read(1, RXR, qq);
$display("status: %t received %x from 4th read address", $time, qq);
 
//
// check invalid slave memory address
//
 
// drive slave address
u0.wb_write(1, TXR, 8'ha0); // present slave address, set write-bit (== !read)
u0.wb_write(0, CR, 8'h90); // set command (start, write)
 
$display("status: %t generate 'start', write cmd a0 (slave address+write). Check invalid address", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while (q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
 
$display("status: %t tip==0", $time);
 
// send memory address
u0.wb_write(1, TXR, 8'h10); // present slave's memory address
u0.wb_write(0, CR, 8'h10); // set command (write)
 
$display("status: %t write slave memory address 10", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while (q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
 
$display("status: %t tip==0", $time);
 
// slave should have send NACK
$display("status: %t Check for nack", $time);
if (!q[7])
$display("\nERROR: Expected NACK, received ACK\n");
 
// read data from slave
u0.wb_write(1, CR, 8'h40); // set command (stop)
 
$display("status: %t generate 'stop'", $time);
 
// check tip bit
u0.wb_read(1, SR, q);
while (q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
 
$display("status: %t tip==0", $time);
 
 
#25000; // wait 25us
 
$display("\n\nstatus: %t Testbench done", $time);
 
$stop;
end
 
endmodule
 
 
/trunk/bench/verilog/i2c_slave_model.v
36,10 → 36,10
 
// CVS Log
//
// $Id: i2c_slave_model.v,v 1.2 2002-03-17 10:26:38 rherveille Exp $
// $Id: i2c_slave_model.v,v 1.3 2002-10-30 18:11:06 rherveille Exp $
//
// $Date: 2002-03-17 10:26:38 $
// $Revision: 1.2 $
// $Date: 2002-10-30 18:11:06 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
46,6 → 46,11
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/03/17 10:26:38 rherveille
// Fixed some race conditions in the i2c-slave model.
// Added debug information.
// Added headers.
//
 
`include "timescale.v"
 
84,6 → 89,7
reg ld; // load downcounter
 
reg sda_o; // sda-drive level
wire sda_dly; // delayed version of sda
 
// statemachine declaration
parameter idle = 3'b000;
100,197 → 106,232
//
 
initial
begin
sda_o = 1'b1;
state = idle;
end
begin
sda_o = 1'b1;
state = idle;
end
 
// generate shift register
always@(posedge scl)
sr <= #1 {sr[6:0],sda};
always @(posedge scl)
sr <= #1 {sr[6:0],sda};
 
//detect my_address
assign my_adr = (sr[7:1] == I2C_ADR);
// FIXME: This should not be a generic assign, but rather
// FIXME: This should not be a generic assign, but rather
// qualified on address transfer phase and probably reset by stop
 
//generate bit-counter
always@(posedge scl)
if (ld)
bit_cnt <= #1 3'b111;
else
bit_cnt <= #1 bit_cnt - 3'h1;
always @(posedge scl)
if(ld)
bit_cnt <= #1 3'b111;
else
bit_cnt <= #1 bit_cnt - 3'h1;
 
//generate access done signal
assign acc_done = !(|bit_cnt);
 
// generate delayed version of sda
// this model assumes a hold time for sda after the falling edge of scl.
// According to the Phillips i2c spec, there s/b a 0 ns hold time for sda
// with regards to scl. If the data changes coincident with the clock, the
// acknowledge is missed
// Fix by Michael Sosnoski
assign #1 sda_dly = sda;
 
 
//detect start condition
always@(negedge sda)
if (scl)
begin
sta <= #1 1'b1;
always @(negedge sda)
if(scl)
begin
sta <= #1 1'b1;
 
if (debug)
$display("DEBUG i2c_slave; start condition detected at %t", $time);
end
else
sta <= #1 1'b0;
if(debug)
$display("DEBUG i2c_slave; start condition detected at %t", $time);
end
else
sta <= #1 1'b0;
 
always@(posedge scl)
d_sta <= #1 sta;
always @(posedge scl)
d_sta <= #1 sta;
 
// detect stop condition
always@(posedge sda)
if (scl)
begin
sto <= #1 1'b1;
always @(posedge sda)
if(scl)
begin
sto <= #1 1'b1;
 
if (debug)
$display("DEBUG i2c_slave; stop condition detected at %t", $time);
end
else
sto <= #1 1'b0;
if(debug)
$display("DEBUG i2c_slave; stop condition detected at %t", $time);
end
else
sto <= #1 1'b0;
 
//generate i2c_reset signal
assign i2c_reset = sta || sto;
 
// generate statemachine
always@(negedge scl or posedge sto)
if (sto || (sta && !d_sta) )
begin
state <= #1 idle; // reset statemachine
always @(negedge scl or posedge sto)
if (sto || (sta && !d_sta) )
begin
state <= #1 idle; // reset statemachine
 
sda_o <= #1 1'b1;
ld <= #1 1'b1;
end
else
begin
// initial settings
sda_o <= #1 1'b1;
ld <= #1 1'b0;
case (state) // synopsys full_case parallel_case
idle: // idle state
if (acc_done && my_adr)
begin
state <= #1 slave_ack;
rw <= #1 sr[0];
sda_o <= #1 1'b1;
ld <= #1 1'b1;
end
else
begin
// initial settings
sda_o <= #1 1'b1;
ld <= #1 1'b0;
 
sda_o <= #1 1'b0; // generate i2c_ack
case(state) // synopsys full_case parallel_case
idle: // idle state
if (acc_done && my_adr)
begin
state <= #1 slave_ack;
rw <= #1 sr[0];
sda_o <= #1 1'b0; // generate i2c_ack
 
#2;
if (debug && rw)
$display("DEBUG i2c_slave; command byte received (read) at %t", $time);
if (debug && !rw)
$display("DEBUG i2c_slave; command byte received (write) at %t", $time);
#2;
if(debug && rw)
$display("DEBUG i2c_slave; command byte received (read) at %t", $time);
if(debug && !rw)
$display("DEBUG i2c_slave; command byte received (write) at %t", $time);
 
if (rw)
begin
mem_do <= #1 mem[mem_adr];
if(rw)
begin
mem_do <= #1 mem[mem_adr];
 
if (debug)
begin
#2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr);
#2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x", mem[4'h0], mem[4'h1], mem[4'h2]);
end
end
end
if(debug)
begin
#2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr);
#2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x", mem[4'h0], mem[4'h1], mem[4'h2]);
end
end
end
 
slave_ack:
begin
if (rw)
begin
state <= #1 data;
sda_o <= #1 mem_do[7];
end
else
state <= #1 get_mem_adr;
slave_ack:
begin
if(rw)
begin
state <= #1 data;
sda_o <= #1 mem_do[7];
end
else
state <= #1 get_mem_adr;
 
ld <= #1 1'b1;
end
ld <= #1 1'b1;
end
 
get_mem_adr: // wait for memory address
if (acc_done)
begin
state <= #1 gma_ack;
mem_adr <= #1 sr; // store memory address
get_mem_adr: // wait for memory address
if(acc_done)
begin
state <= #1 gma_ack;
mem_adr <= #1 sr; // store memory address
sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address
 
sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address
if(debug)
#1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o);
end
 
if (debug)
#1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o);
end
gma_ack:
begin
state <= #1 data;
ld <= #1 1'b1;
end
 
gma_ack:
begin
state <= #1 data;
ld <= #1 1'b1;
end
data: // receive or drive data
begin
if(rw)
sda_o <= #1 mem_do[7];
 
data: // receive or drive data
begin
if (rw)
sda_o <= #1 mem_do[7];
if(acc_done)
begin
state <= #1 data_ack;
mem_adr <= #2 mem_adr + 8'h1;
sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read
 
if (acc_done)
begin
state <= #1 data_ack;
if(rw)
begin
#3 mem_do <= mem[mem_adr];
 
mem_adr <= #2 mem_adr + 8'h1;
if(debug)
#5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr);
end
 
if (rw)
begin
#3 mem_do <= mem[mem_adr];
if(!rw)
begin
mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory
 
if (debug)
#5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr);
end
if(debug)
#2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr);
end
end
end
 
if (!rw)
begin
mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory
data_ack:
begin
ld <= #1 1'b1;
 
if (debug)
#2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr);
end
if(rw)
if(sda) // read operation && master send NACK
begin
state <= #1 idle;
sda_o <= #1 1'b1;
end
else
begin
state <= #1 data;
sda_o <= #1 mem_do[7];
end
else
begin
state <= #1 data;
sda_o <= #1 1'b1;
end
end
 
sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read
end
end
endcase
end
 
data_ack:
begin
ld <= #1 1'b1;
// read data from memory
always @(posedge scl)
if(!acc_done && rw)
mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation
 
if (rw)
if (sda) // read operation && master send NACK
begin
state <= #1 idle;
sda_o <= #1 1'b1;
end
else
begin
state <= #1 data;
sda_o <= #1 mem_do[7];
end
else
begin
state <= #1 data;
sda_o <= #1 1'b1;
end
end
// generate tri-states
assign sda = sda_o ? 1'bz : 1'b0;
 
endcase
end
 
// read data from memory
always@(posedge scl)
if (!acc_done && rw)
mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation
//
// Timing checks
//
 
// generate tri-states
assign sda = sda_o ? 1'bz : 1'b0;
wire tst_sto = sto;
wire tst_sta = sta;
 
specify
specparam normal_scl_low = 4700,
normal_scl_high = 4000,
normal_tsu_sta = 4700,
normal_tsu_sto = 4000,
normal_sta_sto = 4700,
 
fast_scl_low = 1300,
fast_scl_high = 600,
fast_tsu_sta = 1300,
fast_tsu_sto = 600,
fast_sta_sto = 1300;
 
$width(negedge scl, normal_scl_low); // scl high time
$width(posedge scl, normal_scl_high); // scl low time
 
$setup(negedge sda &&& scl, negedge scl, normal_tsu_sta); // start condition
$setup(posedge scl, posedge sda &&& scl, normal_tsu_sto); // stop condition
 
$setup(posedge tst_sta, posedge tst_scl, normal_sta_sto); // stop to start time
endspecify
 
endmodule
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.