URL
https://opencores.org/ocsvn/i2c/i2c/trunk
Subversion Repositories i2c
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- This comparison shows the changes necessary to convert path
/
- from Rev 33 to Rev 34
- ↔ Reverse comparison
Rev 33 → Rev 34
/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
37,10 → 37,10
|
-- CVS Log |
-- |
-- $Id: i2c_master_bit_ctrl.vhd,v 1.5 2002-12-26 16:05:47 rherveille Exp $ |
-- $Id: i2c_master_bit_ctrl.vhd,v 1.6 2003-02-01 02:03:06 rherveille Exp $ |
-- |
-- $Date: 2002-12-26 16:05:47 $ |
-- $Revision: 1.5 $ |
-- $Date: 2003-02-01 02:03:06 $ |
-- $Revision: 1.6 $ |
-- $Author: rherveille $ |
-- $Locker: $ |
-- $State: Exp $ |
47,6 → 47,9
-- |
-- Change History: |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.5 2002/12/26 16:05:47 rherveille |
-- Core is now a Multimaster I2C controller. |
-- |
-- Revision 1.4 2002/11/30 22:24:37 rherveille |
-- Cleaned up code |
-- |
148,7 → 151,8
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration) |
signal dscl_oen : std_logic; -- delayed scl_oen signals |
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs |
signal clk_en, slave_wait :std_logic; -- clock generation signals |
signal clk_en, slave_wait : std_logic; -- clock generation signals |
signal ial : std_logic; -- internal arbitration lost signal |
-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation) |
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis) |
|
253,7 → 257,8
al <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not dcmd_stop); |
end if; |
end process gen_al; |
|
ial <= al; |
|
-- generate dout signal, store dout on rising edge of SCL |
gen_dout: process(clk) |
begin |
276,7 → 281,7
isda_oen <= '1'; |
sda_chk <= '0'; |
elsif (clk'event and clk = '1') then |
if (rst = '1') then |
if (rst = '1' or ial = '1') then |
c_state <= idle; |
cmd_ack <= '0'; |
iscl_oen <= '1'; |
426,3 → 431,4
sda_o <= '0'; |
sda_oen <= isda_oen; |
end architecture structural; |
|
/trunk/rtl/vhdl/i2c_master_top.vhd
37,10 → 37,10
|
-- CVS Log |
-- |
-- $Id: i2c_master_top.vhd,v 1.4 2002-12-26 16:05:47 rherveille Exp $ |
-- $Id: i2c_master_top.vhd,v 1.5 2003-02-01 02:03:06 rherveille Exp $ |
-- |
-- $Date: 2002-12-26 16:05:47 $ |
-- $Revision: 1.4 $ |
-- $Date: 2003-02-01 02:03:06 $ |
-- $Revision: 1.5 $ |
-- $Author: rherveille $ |
-- $Locker: $ |
-- $State: Exp $ |
47,6 → 47,9
-- |
-- Change History: |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.4 2002/12/26 16:05:47 rherveille |
-- Core is now a Multimaster I2C controller. |
-- |
-- Revision 1.3 2002/11/30 22:24:37 rherveille |
-- Cleaned up code |
-- |
337,7 → 340,8
-- assign status register bits |
sr(7) <= rxack; |
sr(6) <= i2c_busy; |
sr(5 downto 2) <= (others => '0'); -- reserved |
sr(5) <= al; |
sr(4 downto 2) <= (others => '0'); -- reserved |
sr(1) <= tip; |
sr(0) <= irq_flag; |
end block; |