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    from Rev 34 to Rev 35
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Rev 34 → Rev 35

/trunk/rtl/verilog/i2c_master_bit_ctrl.v
37,10 → 37,10
 
// CVS Log
//
// $Id: i2c_master_bit_ctrl.v,v 1.7 2002-12-26 16:05:12 rherveille Exp $
// $Id: i2c_master_bit_ctrl.v,v 1.8 2003-02-05 00:06:10 rherveille Exp $
//
// $Date: 2002-12-26 16:05:12 $
// $Revision: 1.7 $
// $Date: 2003-02-05 00:06:10 $
// $Revision: 1.8 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
47,6 → 47,9
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.7 2002/12/26 16:05:12 rherveille
// Small code simplifications
//
// Revision 1.6 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
210,22 → 213,50
 
// synchronize SCL and SDA inputs
// reduce metastability risc
always @(posedge clk)
begin
sSCL <= #1 scl_i;
sSDA <= #1 sda_i;
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sSCL <= #1 1'b1;
sSDA <= #1 1'b1;
 
dSCL <= #1 sSCL;
dSDA <= #1 sSDA;
end
dSCL <= #1 1'b1;
dSDA <= #1 1'b1;
end
else if (rst)
begin
sSCL <= #1 1'b1;
sSDA <= #1 1'b1;
 
dSCL <= #1 1'b1;
dSDA <= #1 1'b1;
end
else
begin
sSCL <= #1 scl_i;
sSDA <= #1 sda_i;
 
dSCL <= #1 sSCL;
dSDA <= #1 sSDA;
end
 
// detect start condition => detect falling edge on SDA while SCL is high
// detect stop condition => detect rising edge on SDA while SCL is high
always @(posedge clk)
begin
sta_condition <= #1 ~sSDA & dSDA & sSCL;
sto_condition <= #1 sSDA & ~dSDA & sSCL;
end
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sta_condition <= #1 1'b0;
sto_condition <= #1 1'b0;
end
else if (rst)
begin
sta_condition <= #1 1'b0;
sto_condition <= #1 1'b0;
end
else
begin
sta_condition <= #1 ~sSDA & dSDA & sSCL;
sto_condition <= #1 sSDA & ~dSDA & sSCL;
end
 
// generate i2c bus busy signal
always @(posedge clk or negedge nReset)
241,13 → 272,26
// 1) master drives SDA high, but the i2c bus is low
// 2) stop detected while not requested
reg cmd_stop, dcmd_stop;
always @(posedge clk)
begin
cmd_stop <= #1 cmd == `I2C_CMD_STOP;
dcmd_stop <= #1 cmd_stop;
always @(posedge clk or negedge nReset)
if (~nReset)
begin
cmd_stop <= #1 1'b0;
dcmd_stop <= #1 1'b0;
al <= #1 1'b0;
end
else if (rst)
begin
cmd_stop <= #1 1'b0;
dcmd_stop <= #1 1'b0;
al <= #1 1'b0;
end
else
begin
cmd_stop <= #1 cmd == `I2C_CMD_STOP;
dcmd_stop <= #1 cmd_stop;
al <= #1 (sda_chk & ~sSDA & sda_oen) | (sto_condition & ~dcmd_stop);
end
 
al <= #1 (sda_chk & ~sSDA & sda_oen) | (sto_condition & ~dcmd_stop);
end
 
// generate dout signal (store SDA on rising edge of SCL)
always @(posedge clk)
/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
37,10 → 37,10
 
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.6 2003-02-01 02:03:06 rherveille Exp $
-- $Id: i2c_master_bit_ctrl.vhd,v 1.7 2003-02-05 00:06:02 rherveille Exp $
--
-- $Date: 2003-02-01 02:03:06 $
-- $Revision: 1.6 $
-- $Date: 2003-02-05 00:06:02 $
-- $Revision: 1.7 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
47,6 → 47,9
--
-- Change History:
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
206,24 → 209,46
signal ibusy : std_logic; -- internal busy signal
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk)
synch_scl_sda: process(clk, nReset)
begin
if (clk'event and clk = '1') then
sSCL <= scl_i;
sSDA <= sda_i;
if (nReset = '0') then
sSCL <= '1';
sSDA <= '1';
 
dSCL <= sSCL;
dSDA <= sSDA;
dSCL <= '1';
dSDA <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= '1';
sSDA <= '1';
 
dSCL <= '1';
dSDA <= '1';
else
sSCL <= scl_i;
sSDA <= sda_i;
 
dSCL <= sSCL;
dSDA <= sSDA;
end if;
end if;
end process synch_SCL_SDA;
 
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk)
detect_sta_sto: process(clk, nReset)
begin
if (clk'event and clk = '1') then
sta_condition <= (not sSDA and dSDA) and sSCL;
sto_condition <= (sSDA and not dSDA) and sSCL;
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
sta_condition <= (not sSDA and dSDA) and sSCL;
sto_condition <= (sSDA and not dSDA) and sSCL;
end if;
end if;
end process detect_sta_sto;
 
244,20 → 269,30
 
 
-- generate arbitration lost signal
gen_al: process(clk)
gen_al: process(clk, nReset)
begin
if (clk'event and clk = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
dcmd_stop <= cmd_stop;
if (nReset = '0') then
cmd_stop <= '0';
dcmd_stop <= '0';
ial <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
dcmd_stop <= '0';
ial <= '0';
else
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
dcmd_stop <= cmd_stop;
 
al <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not dcmd_stop);
ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not dcmd_stop);
end if;
end if;
end process gen_al;
ial <= al;
al <= ial;
 
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk)

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