URL
https://opencores.org/ocsvn/i2c/i2c/trunk
Subversion Repositories i2c
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 37 to Rev 38
- ↔ Reverse comparison
Rev 37 → Rev 38
/trunk/rtl/verilog/i2c_master_byte_ctrl.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: i2c_master_byte_ctrl.v,v 1.5 2002-12-26 15:02:32 rherveille Exp $ |
// $Id: i2c_master_byte_ctrl.v,v 1.6 2003-08-09 07:01:33 rherveille Exp $ |
// |
// $Date: 2002-12-26 15:02:32 $ |
// $Revision: 1.5 $ |
// $Date: 2003-08-09 07:01:33 $ |
// $Revision: 1.6 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/12/26 15:02:32 rherveille |
// Core is now a Multimaster I2C controller |
// |
// Revision 1.4 2002/11/30 22:24:40 rherveille |
// Cleaned up code |
// |
309,13 → 312,16
begin |
c_state <= #1 ST_IDLE; |
core_cmd <= #1 `I2C_CMD_NOP; |
|
// generate command acknowledge signal |
cmd_ack <= #1 1'b1; |
end |
|
// assign ack_out output to bit_controller_rxd (contains last received bit) |
ack_out <= #1 core_rxd; |
|
// generate command acknowledge signal |
cmd_ack <= #1 1'b1; |
// // generate command acknowledge signal |
// cmd_ack <= #1 1'b1; |
|
core_txd <= #1 1'b1; |
end |
327,6 → 333,9
begin |
c_state <= #1 ST_IDLE; |
core_cmd <= #1 `I2C_CMD_NOP; |
|
// generate command acknowledge signal |
cmd_ack <= #1 1'b1; |
end |
|
endcase |
/trunk/rtl/verilog/i2c_master_bit_ctrl.v
37,10 → 37,10
|
// CVS Log |
// |
// $Id: i2c_master_bit_ctrl.v,v 1.9 2003-03-10 14:26:37 rherveille Exp $ |
// $Id: i2c_master_bit_ctrl.v,v 1.10 2003-08-09 07:01:33 rherveille Exp $ |
// |
// $Date: 2003-03-10 14:26:37 $ |
// $Revision: 1.9 $ |
// $Date: 2003-08-09 07:01:33 $ |
// $Revision: 1.10 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.9 2003/03/10 14:26:37 rherveille |
// Fixed cmd_ack generation item (no bug). |
// |
// Revision 1.8 2003/02/05 00:06:10 rherveille |
// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. |
// |
274,26 → 277,22
// aribitration lost when: |
// 1) master drives SDA high, but the i2c bus is low |
// 2) stop detected while not requested |
reg cmd_stop, dcmd_stop; |
reg cmd_stop; |
always @(posedge clk or negedge nReset) |
if (~nReset) |
begin |
cmd_stop <= #1 1'b0; |
dcmd_stop <= #1 1'b0; |
al <= #1 1'b0; |
end |
cmd_stop <= #1 1'b0; |
else if (rst) |
begin |
cmd_stop <= #1 1'b0; |
dcmd_stop <= #1 1'b0; |
al <= #1 1'b0; |
end |
cmd_stop <= #1 1'b0; |
else if (clk_en) |
cmd_stop <= #1 cmd == `I2C_CMD_STOP; |
|
always @(posedge clk or negedge nReset) |
if (~nReset) |
al <= #1 1'b0; |
else if (rst) |
al <= #1 1'b0; |
else |
begin |
cmd_stop <= #1 cmd == `I2C_CMD_STOP; |
dcmd_stop <= #1 cmd_stop; |
al <= #1 (sda_chk & ~sSDA & sda_oen) | (sto_condition & ~dcmd_stop); |
end |
al <= #1 (sda_chk & ~sSDA & sda_oen) | (sto_condition & ~cmd_stop); |
|
|
// generate dout signal (store SDA on rising edge of SCL) |
/trunk/rtl/vhdl/i2c_master_byte_ctrl.vhd
37,10 → 37,10
|
-- CVS Log |
-- |
-- $Id: i2c_master_byte_ctrl.vhd,v 1.3 2002-12-26 16:05:47 rherveille Exp $ |
-- $Id: i2c_master_byte_ctrl.vhd,v 1.4 2003-08-09 07:01:13 rherveille Exp $ |
-- |
-- $Date: 2002-12-26 16:05:47 $ |
-- $Revision: 1.3 $ |
-- $Date: 2003-08-09 07:01:13 $ |
-- $Revision: 1.4 $ |
-- $Author: rherveille $ |
-- $Locker: $ |
-- $State: Exp $ |
47,6 → 47,9
-- |
-- Change History: |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.3 2002/12/26 16:05:47 rherveille |
-- Core is now a Multimaster I2C controller. |
-- |
-- Revision 1.2 2002/11/30 22:24:37 rherveille |
-- Cleaned up code |
-- |
322,14 → 325,14
else |
c_state <= st_idle; |
core_cmd <= I2C_CMD_NOP; |
|
-- generate command acknowledge signal |
host_ack <= '1'; |
end if; |
|
-- assign ack_out output to core_rxd (contains last received bit) |
ack_out <= core_rxd; |
|
-- generate command acknowledge signal |
host_ack <= '1'; |
|
core_txd <= '1'; |
else |
core_txd <= ack_in; |
339,6 → 342,9
if (core_ack = '1') then |
c_state <= st_idle; |
core_cmd <= I2C_CMD_NOP; |
|
-- generate command acknowledge signal |
host_ack <= '1'; |
end if; |
|
when others => -- illegal states |
/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
37,10 → 37,10
|
-- CVS Log |
-- |
-- $Id: i2c_master_bit_ctrl.vhd,v 1.7 2003-02-05 00:06:02 rherveille Exp $ |
-- $Id: i2c_master_bit_ctrl.vhd,v 1.8 2003-08-09 07:01:13 rherveille Exp $ |
-- |
-- $Date: 2003-02-05 00:06:02 $ |
-- $Revision: 1.7 $ |
-- $Date: 2003-08-09 07:01:13 $ |
-- $Revision: 1.8 $ |
-- $Author: rherveille $ |
-- $Locker: $ |
-- $State: Exp $ |
47,6 → 47,9
-- |
-- Change History: |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.7 2003/02/05 00:06:02 rherveille |
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. |
-- |
-- Revision 1.6 2003/02/01 02:03:06 rherveille |
-- Fixed a few 'arbitration lost' bugs. VHDL version only. |
-- |
205,7 → 208,7
signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA |
signal sta_condition : std_logic; -- start detected |
signal sto_condition : std_logic; -- stop detected |
signal cmd_stop, dcmd_stop : std_logic; -- STOP command |
signal cmd_stop : std_logic; -- STOP command |
signal ibusy : std_logic; -- internal busy signal |
begin |
-- synchronize SCL and SDA inputs |
273,22 → 276,20
begin |
if (nReset = '0') then |
cmd_stop <= '0'; |
dcmd_stop <= '0'; |
ial <= '0'; |
elsif (clk'event and clk = '1') then |
if (rst = '1') then |
cmd_stop <= '0'; |
dcmd_stop <= '0'; |
ial <= '0'; |
else |
if (cmd = I2C_CMD_STOP) then |
cmd_stop <= '1'; |
else |
cmd_stop <= '0'; |
end if; |
dcmd_stop <= cmd_stop; |
if (clk_en = '1') then |
if (cmd = I2C_CMD_STOP) then |
cmd_stop <= '1'; |
else |
cmd_stop <= '0'; |
end if; |
|
ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not dcmd_stop); |
ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop); |
end if; |
end if; |
end process gen_al; |
/trunk/rtl/vhdl/i2c_master_top.vhd
37,10 → 37,10
|
-- CVS Log |
-- |
-- $Id: i2c_master_top.vhd,v 1.5 2003-02-01 02:03:06 rherveille Exp $ |
-- $Id: i2c_master_top.vhd,v 1.6 2003-08-09 07:01:13 rherveille Exp $ |
-- |
-- $Date: 2003-02-01 02:03:06 $ |
-- $Revision: 1.5 $ |
-- $Date: 2003-08-09 07:01:13 $ |
-- $Revision: 1.6 $ |
-- $Author: rherveille $ |
-- $Locker: $ |
-- $State: Exp $ |
47,6 → 47,9
-- |
-- Change History: |
-- $Log: not supported by cvs2svn $ |
-- Revision 1.5 2003/02/01 02:03:06 rherveille |
-- Fixed a few 'arbitration lost' bugs. VHDL version only. |
-- |
-- Revision 1.4 2002/12/26 16:05:47 rherveille |
-- Core is now a Multimaster I2C controller. |
-- |
233,25 → 236,24
gen_cr: process(rst_i, wb_clk_i) |
begin |
if (rst_i = '0') then |
cr <= (others => '0'); |
cr <= (others => '0'); |
elsif (wb_clk_i'event and wb_clk_i = '1') then |
if (wb_rst_i = '1') then |
cr <= (others => '0'); |
elsif (wb_wacc = '1') then |
if ( (core_en = '1') and (wb_adr_i = 4) ) then |
-- only take new commands when i2c core enabled |
-- pending commands are finished |
cr <= wb_dat_i; |
end if; |
else |
if (done = '1' or i2c_al = '1') then |
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done |
-- or arbitration lost |
end if; |
if (wb_rst_i = '1') then |
cr <= (others => '0'); |
elsif (wb_wacc = '1') then |
if ( (core_en = '1') and (wb_adr_i = 4) ) then |
-- only take new commands when i2c core enabled |
-- pending commands are finished |
cr <= wb_dat_i; |
end if; |
else |
if (done = '1' or i2c_al = '1') then |
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost |
end if; |
|
cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0' |
cr(0) <= '0'; -- clear IRQ_ACK bit |
end if; |
cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0' |
cr(0) <= '0'; -- clear IRQ_ACK bit |
end if; |
end if; |
end process gen_cr; |
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