URL
https://opencores.org/ocsvn/i2c/i2c/trunk
Subversion Repositories i2c
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- This comparison shows the changes necessary to convert path
/
- from Rev 53 to Rev 54
- ↔ Reverse comparison
Rev 53 → Rev 54
/trunk/bench/verilog/tst_bench_top.v
37,10 → 37,10
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// CVS Log |
// |
// $Id: tst_bench_top.v,v 1.6 2004-02-28 15:40:42 rherveille Exp $ |
// $Id: tst_bench_top.v,v 1.7 2005-02-27 09:24:18 rherveille Exp $ |
// |
// $Date: 2004-02-28 15:40:42 $ |
// $Revision: 1.6 $ |
// $Date: 2005-02-27 09:24:18 $ |
// $Revision: 1.7 $ |
// $Author: rherveille $ |
// $Locker: $ |
// $State: Exp $ |
47,6 → 47,9
// |
// Change History: |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2004/02/28 15:40:42 rherveille |
// *** empty log message *** |
// |
// Revision 1.4 2003/12/05 11:04:38 rherveille |
// Added slave address configurability |
// |
71,7 → 74,7
reg rstn; |
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wire [31:0] adr; |
wire [ 7:0] dat_i, dat_o; |
wire [ 7:0] dat_i, dat_o, dat0_i, dat1_i; |
wire we; |
wire stb; |
wire cyc; |
80,9 → 83,8
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reg [7:0] q, qq; |
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wire scl, scl_o, scl_oen; |
wire sda, sda_o, sda_oen; |
reg rscl, rsda; |
wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen; |
wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen; |
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parameter PRER_LO = 3'b000; |
parameter PRER_HI = 3'b001; |
122,6 → 124,11
.rty(1'b0) |
); |
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wire stb0 = stb & ~adr[3]; |
wire stb1 = stb & adr[3]; |
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assign dat_i = ({{8'd8}{stb0}} & dat0_i) | ({{8'd8}{stb1}} & dat1_i); |
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// hookup wishbone_i2c_master core |
i2c_master_top i2c_top ( |
|
131,9 → 138,9
.arst_i(rstn), |
.wb_adr_i(adr[2:0]), |
.wb_dat_i(dat_o), |
.wb_dat_o(dat_i), |
.wb_dat_o(dat0_i), |
.wb_we_i(we), |
.wb_stb_i(stb), |
.wb_stb_i(stb0), |
.wb_cyc_i(cyc), |
.wb_ack_o(ack), |
.wb_inta_o(inta), |
140,13 → 147,37
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// i2c signals |
.scl_pad_i(scl), |
.scl_pad_o(scl_o), |
.scl_padoen_o(scl_oen), |
.scl_pad_o(scl0_o), |
.scl_padoen_o(scl0_oen), |
.sda_pad_i(sda), |
.sda_pad_o(sda_o), |
.sda_padoen_o(sda_oen) |
.sda_pad_o(sda0_o), |
.sda_padoen_o(sda0_oen) |
), |
i2c_top2 ( |
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// wishbone interface |
.wb_clk_i(clk), |
.wb_rst_i(1'b0), |
.arst_i(rstn), |
.wb_adr_i(adr[2:0]), |
.wb_dat_i(dat_o), |
.wb_dat_o(dat1_i), |
.wb_we_i(we), |
.wb_stb_i(stb1), |
.wb_cyc_i(cyc), |
.wb_ack_o(ack), |
.wb_inta_o(inta), |
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// i2c signals |
.scl_pad_i(scl), |
.scl_pad_o(scl1_o), |
.scl_padoen_o(scl1_oen), |
.sda_pad_i(sda), |
.sda_pad_o(sda1_o), |
.sda_padoen_o(sda1_oen) |
); |
|
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// hookup i2c slave model |
i2c_slave_model #(SADR) i2c_slave ( |
.scl(scl), |
153,13 → 184,12
.sda(sda) |
); |
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// create i2c lines |
always rscl = #600 scl_oen ? 1'bz : scl_o; // create tri-state buffer for i2c_master scl line |
always rsda = #600 sda_oen ? 1'bz : sda_o; // create tri-state buffer for i2c_master sda line |
// create i2c lines |
delay m0_scl (scl0_oen ? 1'bz : scl0_o, scl), |
m1_scl (scl1_oen ? 1'bz : scl1_o, scl), |
m0_sda (sda0_oen ? 1'bz : sda0_o, sda), |
m1_sda (sda1_oen ? 1'bz : sda1_o, sda); |
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assign scl = rscl; |
assign sda = rsda; |
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pullup p1(scl); // pullup scl line |
pullup p2(sda); // pullup sda line |
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412,5 → 442,15
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endmodule |
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module delay (in, out); |
input in; |
output out; |
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assign out = in; |
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specify |
(in => out) = (600,600); |
endspecify |
endmodule |
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