OpenCores
URL https://opencores.org/ocsvn/i650/i650/trunk

Subversion Repositories i650

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 14 to Rev 15
    ↔ Reverse comparison
  •

Rev 14 → Rev 15

/i650/trunk/rtl/operator_ctl.v
37,10 → 37,12
input wu, hp,
input [0:3] early_idx, ontime_idx,
input [0:6] cmd_digit_in, io_buffer_in, gs_in,
input [0:6] cmd_digit_in, io_buffer_in, gs_in, acc_ontime, dist_ontime,
prog_ontime,
input [0:5] command,
output reg[0:6] data_out, addr_out, console_out,
output [0:6] display_digit,
output reg console_to_addr,
output reg[0:14] gs_ram_addr,
output reg read_gs, write_gs,
71,6 → 73,10
assign ri_storage = disp_sw_ri;
assign ro_storage = disp_sw_ro;
assign storage_control = run_control | disp_sw_ro;
assign display_digit = (disp_sw_lacc | disp_sw_uacc)? acc_ontime
: (disp_sw_dist | disp_sw_ri | disp_sw_ro)? dist_ontime
: disp_sw_pgm? prog_ontime
: `biq_blank;
//-----------------------------------------------------------------------------
// Calculate the RAM address of the general storage word at address gs_addr_.
130,7 → 136,11
`define state_clear_drum_2 6'd42
`define state_clear_drum_3 6'd43
`define state_load_gs_1 6'd44
`define state_load_gs_1 6'd45
`define state_load_gs_2 6'd45
`define state_dump_gs_1 6'd46
`define state_dump_gs_2 6'd47
`define state_dump_gs_3 6'd48
`define state_dump_gs_4 6'd49
always @(posedge clk) begin
if (rst) begin
452,7 → 462,6
state <= `state_write_gs_1;
end
end
end
`cmd_read_acc: begin
489,6 → 498,10
end
`cmd_dump_gs: begin
if (ctl_sw_manual) begin
busy <= 1;
state <= `state_dump_gs_1;
end
end
`cmd_power_on_reset: begin
703,13 → 716,13
`state_read_gs_4: begin
state <= `state_read_gs_5;
gs_ram_addr <= gs_ram_addr + 1;
gs_ram_addr <= (gs_ram_addr + 1) % 32768;
end
`state_read_gs_5: begin
digit_ready <= 1;
cmd_digit_out <= gs_in;
gs_ram_addr <= gs_ram_addr + 1;
gs_ram_addr <= (gs_ram_addr + 1) % 32768;
if (dx) begin
state <= `state_read_gs_6;
read_gs <= 0;
763,7 → 776,7
`state_write_gs_4: begin
write_gs <= 1;
console_out <= cmd_digit_in;
gs_ram_addr <= gs_ram_addr + 1;
gs_ram_addr <= (gs_ram_addr + 1) % 32768;
if (d10) begin
digit_ready <= 0;
state <= `state_write_gs_5;
776,16 → 789,14
end
// 0 : Ignore if not in manual
// Clear gs_ram_addr
// 1 : Synchronize with d10
// Turn on console_write_gs
// 1 : Synchronize with dx
// Put first dx digit
// 2 : Put a digit:
// dx: blank
// d0: minus
// d1-d10: zero
// gs_ram_addr++
`state_clear_drum_1: begin
if (d10) begin
if (dx) begin
console_out <= `biq_blank;
gs_ram_addr <= 15'd0;
write_gs <= 1;
797,7 → 808,7
console_out <= dx? `biq_blank
: d0? `biq_minus
: `biq_0;
gs_ram_addr <= gs_ram_addr + 1;
gs_ram_addr <= (gs_ram_addr + 1) % 32768;
if (gs_ram_addr == 15'd23999) begin
write_gs <= 0;
state <= `state_idle;
812,9 → 823,9
end
`state_load_gs_2: begin
gs_ram_addr <= gs_ram_addr + 1;
gs_ram_addr <= (gs_ram_addr + 1) % 32768;
console_out <= cmd_digit_in;
if (gs_ram_addr == 15d'23999) begin
if (gs_ram_addr == 15'd23999) begin
write_gs <= 0;
digit_ready <= 0;
state <= `state_idle;
821,6 → 832,32
end
end
`state_dump_gs_1: begin
gs_ram_addr <= 15'd0;
read_gs <= 1;
state <= `state_dump_gs_2;
end
`state_dump_gs_2: begin
gs_ram_addr <= (gs_ram_addr + 1) % 32768;
state <= `state_dump_gs_3;
end
`state_dump_gs_3: begin
digit_ready <= 1;
gs_ram_addr <= (gs_ram_addr + 1) % 32768;
cmd_digit_out <= gs_in;
if (gs_ram_addr == 15'd23999) begin
state <= `state_dump_gs_4;
end
end
`state_dump_gs_4: begin
digit_ready <= 0;
read_gs <= 0;
state <= `state_idle;
end
endcase;
end
end;
/i650/trunk/rtl/accumulator.v
32,8 → 32,8
module accumulator (
input rst,
input ap, bp, dp,
input dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,
input dxu, d0u, d1l,
input d1, d2, d10,
input dxu, d0u,
input wu, wl,
input [0:6] adder_out,
input acc_regen_gate, right_shift_gate, acc_ri_gate,
55,7 → 55,7
// Read into ontime_out
//-----------------------------------------------------------------------------
wire acc_reset = reset_op_latch | man_acc_reset
| (zero_shift_count & wl & (d1l | d2));
| (zero_shift_count & wl & (d1 | d2));
always @(posedge ap) begin
if (rst) begin
early_out <= `biq_blank;
/i650/trunk/rtl/toplev.v
37,9 → 37,10
input [0:6] cmd_digit_in, io_buffer_in,
input [0:5] command,
 
output [0:6] cmd_digit_out,
output [0:6] cmd_digit_out, display_digit,
output busy, digit_ready, punch_card, read_card, card_digit_ready,
output synch
output digit_sync, word_upper,
output [0:3] digit_ctr
);
wire ap, bp, cp, dp;
52,7 → 53,9
wire [0:9] digit_idx;
wire [0:3] early_idx, ontime_idx;
assign synch = bp;
assign digit_sync = bp;
assign digit_ctr = ontime_idx;
assign word_upper = wu;
timing tm (
.clk(clk),
112,6 → 115,11
);
//-----------------------------------------------------------------------------
// Accumulator
//-----------------------------------------------------------------------------
wire [0:6] ac_early_out, ac_ontime_out, ac_ped_out;
//-----------------------------------------------------------------------------
// General storage
//-----------------------------------------------------------------------------
wire [0:4] gs_out;
120,7 → 128,7
//-----------------------------------------------------------------------------
// Operator controls
//-----------------------------------------------------------------------------
wire [0:6] oc_data_out, oc_addr_out, oc_console_out;
wire [0:6] oc_data_out, oc_addr_out, oc_console_out, oc_display_digit;
wire oc_console_to_addr;
wire [0:14] oc_gs_ram_addr;
wire oc_read_gs, oc_write_gs;
129,7 → 137,8
oc_storage_control;
wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000,
oc_hard_reset;
assign display_digit = oc_display_digit;
//-----------------------------------------------------------------------------
// Translators
//-----------------------------------------------------------------------------
137,6 → 146,32
wire [0:4] tr_gs_in;
wire [0:6] tr_select_out;
 
accumulator ac (
.rst(rst),
.ap(ap),
.bp(bp),
.dp(dp),
.d1(d1),
.d2(d2),
.d10(d10),
.dxu(dxu),
.d0u(d0u),
.wu(wu),
.wl(wl),
.adder_out(`biq_0),
.acc_regen_gate(1'b1),
.right_shift_gate(1'b0),
.acc_ri_gate(1'b0),
.zero_shift_count(1'b0),
.man_acc_reset(oc_man_acc_reset),
.reset_op_latch(1'b0),
.early_idx(early_idx),
.ontime_idx(ontime_idx),
.early_out(ac_early_out),
.ontime_out(ac_ontime_out),
.ped_out(ac_ped_out)
);
 
gen_store gs (
.rst(oc_hard_reset),
.ap(ap),
176,10 → 211,14
.cmd_digit_in(cmd_digit_in),
.io_buffer_in(io_buffer_in),
.gs_in(tr_select_out),
.acc_ontime(ac_ontime_out),
.dist_ontime(`biq_blank),
.prog_ontime(`biq_blank),
.command(command),
.data_out(oc_data_out),
.addr_out(oc_addr_out),
.console_out(oc_console_out),
.display_digit(oc_display_digit),
.console_to_addr(oc_console_to_addr),
.gs_ram_addr(oc_gs_ram_addr),
.read_gs(oc_read_gs),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.