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URL https://opencores.org/ocsvn/i650/i650/trunk

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  • This comparison shows the changes necessary to convert path 
    /i650
    from Rev 19 to Rev 20
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  •

Rev 19 → Rev 20

/trunk/rtl/checking.v
35,7 → 35,7
);
//-----------------------------------------------------------------------------
// .
// Validate bi-quinary digit.
//-----------------------------------------------------------------------------
wire q0_or_q1 = biq[`biq_q0] | biq[`biq_q1];
wire q2_or_q3_or_q4 = biq[`biq_q2] | biq[`biq_q3] | biq[`biq_q4];
46,12 → 46,12
wire q3_and_q4 = biq[`biq_q3] & biq[`biq_q4];
wire q2_and_q3 = biq[`biq_q2] & biq[`biq_q3];
assign invalid = (q2_and_q4)
| (q3_and_q4)
| (q2_and_q3)
| (q0_or_q1 & q2_or_q3_or_q4)
| (q0_and_q1)
| (b0_and_b5)
| ~(b0_or_b5 & (q0_or_q1 | q2_or_q3_or_q4));
| (q3_and_q4)
| (q2_and_q3)
| (q0_or_q1 & q2_or_q3_or_q4)
| (q0_and_q1)
| (b0_and_b5)
| ~(b0_or_b5 & (q0_or_q1 | q2_or_q3_or_q4));
endmodule
 
71,6 → 71,9
biq_check bc2 (prog_ontime, prog_invalid);
biq_check bc3 (dist_ontime, dist_invalid);
assign error_stop = tlu_or_zero_check | acc_error | prog_error | dist_error;
assign acc_check_light = acc_error;
assign prog_check_light = prog_error;
assign dist_check_light = dist_error;
always @(posedge bp)
if (rst) begin
/trunk/rtl/accumulator.v
32,7 → 32,7
module accumulator (
input rst,
input ap, bp, dp,
input dx, d1, d2, d10,
input dx, d1, d2,
input dxu, d0u,
input wu, wl,
input [0:6] adder_out,
/trunk/rtl/gen_store.v
69,20 → 69,18
//-----------------------------------------------------------------------------
// A : Read from RAM at on-time address.
//-----------------------------------------------------------------------------
always @(posedge ap) begin
always @(posedge ap)
if (rst) begin
gs_out <= `biq_blank;
end else begin
gs_out <= gs_mem[gs_addr];
end
end;
end;
//-----------------------------------------------------------------------------
// D : Write to RAM at early address.
//-----------------------------------------------------------------------------
always @(posedge dp) begin
always @(posedge dp)
if (write_gate)
gs_mem[gs_addr_early] <= gs_in;
end;
endmodule
/trunk/rtl/timing.v
45,6 → 45,7
output reg[0:3] early_idx, ontime_idx
);
 
reg ctr_reset;
reg[0:3] digit_ctr;
reg[0:3] word_ctr;
reg[0:2] sector_ctr;
61,25 → 62,26
//-----------------------------------------------------------------------------
// 650 four-phase clock
//-----------------------------------------------------------------------------
always @(posedge rst, posedge clk) begin
always @(posedge clk)
if (rst) begin
ctr_reset <= 1;
ap <= 1;
bp <= 0;
cp <= 0;
dp <= 0;
end else begin
if (dp) ctr_reset <= 0;
ap <= dp;
bp <= ap;
cp <= bp;
dp <= cp;
end;
end;
//-----------------------------------------------------------------------------
// Counter-based timing signals
//-----------------------------------------------------------------------------
always @(posedge rst, posedge dp) begin
if (rst) begin
always @(posedge dp)
if (ctr_reset) begin
dx <= 0;
d0 <= 0;
d1 <= 0;
242,6 → 244,5
end
endcase;
end;
end;
endmodule
/trunk/rtl/operator_ctl.v
131,7 → 131,6
`define state_read_gs_6 6'd35
`define state_write_gs_1 6'd36
`define state_write_gs_2 6'd37
`define state_write_gs_2a 6'd63
`define state_write_gs_3 6'd38
`define state_write_gs_4 6'd39
`define state_write_gs_5 6'd40
154,7 → 153,7
`define state_dump_gs_3 6'd57
`define state_dump_gs_4 6'd58
always @(posedge clk) begin
always @(posedge clk)
if (rst) begin
console_to_addr <= 0;
pgm_start <= 0;
780,13 → 779,6
end
end
`state_write_gs_2a: begin
if (d9) begin
digit_ready <= 1;
state <= `state_write_gs_3;
end
end
`state_write_gs_3: begin
if (d10) begin
gs_ram_addr <= gs_word_addr;
939,10 → 931,9
end
endcase;
end
end;
end;
always @(posedge ap) begin
always @(posedge ap)
if (hard_reset) begin
data_out <= `biq_blank;
addr_out <= `biq_blank;
949,15 → 940,13
end else begin
data_out <= d10? `biq_blank : storage_entry_sw[early_idx];
addr_out <= (d3 | d4 | d5 | d6)? addr_sel_sw[early_idx[2:3]] : `biq_blank;
end
end;
end;
always @(posedge ap) begin
always @(posedge ap)
if (hard_reset) begin
punch_card <= 0;
read_card <= 0;
card_digit_ready <= 0;
end
end;
end;
endmodule
/trunk/rtl/prog_step.v
0,0 → 1,78
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// IBM 650 Reconstruction in Verilog (i650)
//
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
// http:////www.opencores.org/project,i650
//
// Description: Program step register.
//
// Additional Comments: See US 2959351, Fig. 62.
//
// Copyright (c) 2015 Robert Abeles
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
`include "defines.v"
 
module prog_step (
input rst,
input ap, dp,
input dx, d0, d10,
input [0:3] early_idx, ontime_idx,
input man_prog_reset, rips,
input [0:6] adder_out, sel_store_out,
input prog_ped_regen, prog_add, // see tlu 86d
output reg [0:6] early_out, ontime_out,
output [0:6] ped_out,
output prog_restart_sig
);
 
reg [0:6] digits [0:15];
reg ri_prog_step;
//-----------------------------------------------------------------------------
// AP -- Read digits RAM, write early and ontime outs
// Start/stop RI control
// Generate prog_restart_sig
//-----------------------------------------------------------------------------
digit_pulse pr_sig (rst, ap, ~rips, 1'b1, prog_restart_sig);
always @(posedge ap)
if (rst) begin
ri_prog_step <= 0;
early_out <= `biq_blank;
ontime_out <= `biq_blank;
end else begin
if (d0) begin
ri_prog_step <= rips;
end
early_out <= (dx | d10)? `biq_blank : digits[early_idx];
ontime_out <= man_prog_reset? `biq_0 : early_out;
end;
//-----------------------------------------------------------------------------
// DP
//-----------------------------------------------------------------------------
assign ped_out = ri_prog_step? sel_store_out
: prog_ped_regen? ontime_out
: prog_add? adder_out
: `biq_blank;
always @(posedge dp)
digits[ontime_idx] <= (dx | d0)? `biq_blank : ped_out;
 
endmodule
trunk/rtl/prog_step.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/toplev.v =================================================================== --- trunk/rtl/toplev.v (revision 19) +++ trunk/rtl/toplev.v (revision 20) @@ -118,6 +118,12 @@ // Accumulator //----------------------------------------------------------------------------- wire [0:6] ac_early_out, ac_ontime_out, ac_ped_out; + + //----------------------------------------------------------------------------- + // Distributor + //----------------------------------------------------------------------------- + wire [0:6] ds_early_out, ds_ontime_out; + wire ds_back_sig; //----------------------------------------------------------------------------- // Register validity checking @@ -146,6 +152,12 @@ assign display_digit = oc_display_digit; //----------------------------------------------------------------------------- + // Program step register + //----------------------------------------------------------------------------- + wire [0:6] ps_early_out, ps_ontime_out, ps_ped_out; + wire ps_restart_sig; + + //----------------------------------------------------------------------------- // Translators //----------------------------------------------------------------------------- wire tr_gs_write; @@ -160,7 +172,6 @@ .dx(dx), .d1(d1), .d2(d2), - .d10(d10), .dxu(dxu), .d0u(d0u), .wu(wu), @@ -184,8 +195,8 @@ .bp(bp), .d1_dx(d1_dx), .acc_ontime(ac_ontime_out), - .prog_ontime(7'b0), - .dist_ontime(7'b0), + .prog_ontime(ps_ontime_out), + .dist_ontime(ds_ontime_out), .error_reset(oc_err_reset), .tlu_or_zero_check(1'b0), .error_stop(ck_error_stop), @@ -194,6 +205,28 @@ .dist_check_light(ck_dist_check_light) ); + distributor ds ( + .rst(rst), + .ap(ap), + .cp(cp), + .dp(dp), + .dx(dx), + .d0(d0), + .d10(d10), + .selected_storage(7'd0), + .ri_dist(1'd0), + .acc_ontime(ac_ontime_out), + .start_acc_dist_ri(1'd0), + .end_acc_dist_ri(1'd0), + .acc_dist_ri(1'd0), + .man_acc_reset(oc_man_acc_reset), + .early_idx(early_idx), + .ontime_idx(ontime_idx), + .ontime_out(ds_ontime_out), + .early_out(ds_early_out), + .dist_back_sig(ds_back_sig) + ); + gen_store gs ( .rst(oc_hard_reset), .ap(ap), @@ -236,8 +269,8 @@ .io_buffer_in(io_buffer_in), .gs_in(tr_select_out), .acc_ontime(ac_ontime_out), - .dist_ontime(`biq_blank), - .prog_ontime(`biq_blank), + .dist_ontime(ds_ontime_out), + .prog_ontime(ps_ontime_out), .command(command), .data_out(oc_data_out), .addr_out(oc_addr_out), @@ -269,6 +302,27 @@ .card_digit_ready(card_digit_ready) ); + prog_step ps ( + .rst(rst), + .ap(ap), + .dp(dp), + .dx(dx), + .d0(d0), + .d10(d10), + .early_idx(early_idx), + .ontime_idx(ontime_idx), + .man_prog_reset(oc_man_pgm_reset), + .rips(1'b0), + .adder_out(7'b0), + .sel_store_out(7'b0), + .prog_ped_regen(1'b1), + .prog_add(1'b0), + .early_out(ps_early_out), + .ontime_out(ps_ontime_out), + .ped_out(ps_ped_out), + .prog_restart_sig(ps_restart_sig) + ); + translators tr ( .dist_early_out(`biq_blank), .bs_out(`biq_blank),
/trunk/rtl/distributor.v
0,0 → 1,105
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// IBM 650 Reconstruction in Verilog (i650)
//
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
// http:////www.opencores.org/project,i650
//
// Description: Distributor register.
//
// Additional Comments: See US 2959351, Fig. 61.
//
// Copyright (c) 2015 Robert Abeles
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
`include "defines.v"
 
module distributor (
input rst,
input ap, cp, dp,
input dx, d0, d10,
input [0:6] selected_storage,
input ri_dist, // commutator 81f, dx:bp
input [0:6] acc_ontime,
input start_acc_dist_ri, end_acc_dist_ri, acc_dist_ri,
input man_acc_reset,
input [0:3] early_idx, ontime_idx,
output reg[0:6] ontime_out, early_out,
output dist_back_sig
);
 
reg [0:6] digits [0:15];
reg ri_dist_from_stor, dist_regen_ctl, ri_from_acc, ri_from_acc_delay;
//-----------------------------------------------------------------------------
// A -- Read digits RAM, write early and ontime outs
//-----------------------------------------------------------------------------
always @(posedge ap)
if (rst) begin
early_out <= `biq_blank;
ontime_out <= `biq_blank;
end else begin
early_out <= (dist_regen_ctl | d10)? `biq_blank : digits[early_idx];
ontime_out <= dx? `biq_0
: man_acc_reset? (d0? `biq_plus : `biq_0)
: early_out;
end;
//-----------------------------------------------------------------------------
// C
//-----------------------------------------------------------------------------
always @(posedge cp)
if (rst) begin
ri_dist_from_stor <= 0;
dist_regen_ctl <= 0;
ri_from_acc <= 0;
ri_from_acc_delay <= 0;
end else begin
if (d10) begin
ri_dist_from_stor <= 0;
end else if (ri_dist) begin
ri_dist_from_stor <= 1;
end
if (d10 | end_acc_dist_ri) begin
dist_regen_ctl <= 0;
end else if (ri_dist | start_acc_dist_ri) begin
dist_regen_ctl <= 1;
end
if (acc_dist_ri) begin
ri_from_acc_delay <= 1;
end else if (ri_from_acc_delay) begin
ri_from_acc_delay <= 0;
ri_from_acc <= 1;
end else begin
ri_from_acc <= 0;
end
end;
 
//-----------------------------------------------------------------------------
// D
//-----------------------------------------------------------------------------
always @(posedge dp)
digits[ontime_idx] <= ri_dist_from_stor? selected_storage
: ri_from_acc? acc_ontime
: ontime_out;
digit_pulse bk_sig (rst, dp, ~dist_regen_ctl, 1'b1, dist_back_sig);
endmodule
trunk/rtl/distributor.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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