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URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

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Rev 16 → Rev 17

/iso7816_3_master/trunk/test/DummyCard.v
166,7 → 166,7
 
//stuff which can be changed by command and affect ATR
always @(posedge isoVdd) begin
useIndirectConventionConfig<=1'b1;
useIndirectConventionConfig<=1'b0;
end
 
integer i;
/iso7816_3_master/trunk/test/tsAnalyzer.v
57,8 → 57,8
assign tsReceived = ~waitTs;
assign atrIsEarly = ~waitTs & (resetCnt<(16'h100+16'd400));
assign atrIsLate = resetCnt>(16'h100+16'd40000);
assign useIndirectConvention = ~waitTs & (ts==8'h03);//03 is 3F written LSB first and complemented
assign tsError = ~waitTs & (ts!=8'h3B) & ~useIndirectConvention;
assign useIndirectConvention = ~waitTs & (ts==8'h3F);
assign tsError = ~waitTs & (ts!=8'h3B) & (ts!=8'h3F);
 
assign isActivated = isoReset & isoVdd;
wire fsm_nReset=nReset & isoReset & isoVdd;
72,7 → 72,7
waitTs<=1'b0;
case(rxData)
8'h3B: ts<=rxData;
8'h03: ts<=8'h3F;
8'h03: ts<=8'h3F;//03 is 3F written LSB first and complemented
default: ts<=rxData;
endcase
end
/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
223,6 → 223,7
reg ppsValidSoFar;
reg ppsAccepted;
wire ppsDataMatch = (tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]==dataOut);
wire [3:0] earlyAtrK = (4'h0==tdiCnt) ? dataOut[3:0] : atrK;
always @(posedge isoClk, negedge rxCore_nReset) begin
if(~rxCore_nReset) begin
ppsValidSoFar<=1'b0;
236,7 → 237,7
fsmState<=ATR_TDI;
atrHasTck<=1'b0;
tempBytesCnt<=8'h0;
tdiStruct<=12'h0;
tdiStruct<={4'h0,8'h80};//0x80 as default TDi to consider T0 as a TDi
atrCompleted<=1'b0;
atrK<=4'b0;
end else if(isActivated) begin
247,36 → 248,33
case(fsmState)
ATR_TDI: begin
if(endOfRx) begin
if(tempBytesCnt==nIfBytes) begin //TDi bytes
tempBytesCnt <= 2'h0;
tdiStruct <= {tdiCnt+1,dataOut};
if(tempBytesCnt+1==nIfBytes) begin //TDi bytes
if(4'h0==tdiCnt) begin//this is T0
atrK <= dataOut[3:0];
fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :
(4'b0!=dataOut[3:0]) ? ATR_HISTORICAL : T0_HEADER;
end else begin//TDi, i from 1 to 15
fsmState <= (4'b0!=dataOut[7:4]) ? ATR_TDI :
(4'b0!=atrK) ? ATR_HISTORICAL : T0_HEADER;
end
tempBytesCnt <= 2'h0;
tdiStruct <= {tdiCnt+1,dataOut};
if(12'h0=={dataOut,atrK}) begin
atrCompleted <= 1'b1;
{waitCardTx,waitTermTx}<=2'b01;
end
if((1'b0==tdiStruct[7]) |//we just received the last interface byte
(4'b0==dataOut[7:4])) begin //or new TDi indicate no further interface bytes
fsmState <= (4'b0!=earlyAtrK) ? ATR_HISTORICAL :
atrHasTck ? ATR_TCK : T0_HEADER;
end else begin//TDi, i from 1 to 15
fsmState <= ATR_TDI;
end
end else begin //TA, TB or TC bytes
//TODO: get relevant info
//check if we just received the last interface byte
if((tempBytesCnt+1==nIfBytes) & (1'b0==tdiStruct[7])) begin
tempBytesCnt <= 2'h0;
fsmState <= (4'b0!=atrK) ? ATR_HISTORICAL : T0_HEADER;
end else begin
tempBytesCnt <= tempBytesCnt+1;
end
tempBytesCnt <= tempBytesCnt+1;
end
end
end
ATR_HISTORICAL: begin
if(endOfRx) begin
if(tempBytesCnt==(atrK-1)) begin
if(tempBytesCnt+1==atrK) begin
tempBytesCnt <= 8'h0;
if(atrHasTck) begin
fsmState <= ATR_TCK;
/iso7816_3_master/trunk/sources/Iso7816_3_Master.v
107,7 → 107,7
assign atrIsEarly = ~waitTs & (resetCnt<(16'h100+16'd400));
assign atrIsLate = resetCnt>(16'h100+16'd40000);
assign useIndirectConvention = ~waitTs & (ts==8'h3F);
assign tsError = ~waitTs & (ts!=8'h3B) & ~useIndirectConvention;
assign tsError = ~waitTs & (ts!=8'h3B) & (ts!=8'h3F);
always @(posedge comClk, negedge nReset) begin
if(~nReset) begin
isoClkEn <= 1'b0;
122,7 → 122,7
waitTs<=1'b0;
case(dataOut)
8'h3B: ts<=dataOut;
8'h03: ts<=8'h3F;
8'h03: ts<=8'h3F;//03 is 3F written LSB first and complemented
default: ts<=dataOut;
endcase
end

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