OpenCores
URL https://opencores.org/ocsvn/keras_to_fpga/keras_to_fpga/trunk

Subversion Repositories keras_to_fpga

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /keras_to_fpga
    from Rev 2 to Rev 3
    Reverse comparison

Rev 2 → Rev 3

/trunk/scripts/sim_env.do
9,7 → 9,7
set env(ROOT_DIR) ../../../..
set env(PROJECT_DIR) ../../..
 
set env(LIB_BASE_DIR) $env(PROJECT_DIR)/$env(LIB_BASE)
set env(LIB_BASE_DIR) $env(ROOT_DIR)/$env(LIB_BASE)
 
# load sim procedures
do $env(LIB_BASE_DIR)/scripts/sim_procs.do
/trunk/sim/tests/tb_mnist_mlp/files.f
2,8 → 2,8
 
${LIB_BASE_DIR}/axi4_stream_lib/src/recursive_axis_catenate.sv
 
${PROJECT_DIR}/src/fpga/rom.sv
${PROJECT_DIR}/src/fpga/axis_rom.sv
${LIB_BASE_DIR}/basal/src/ROM/rom.sv
${LIB_BASE_DIR}/basal/src/ROM/axis_rom.sv
 
${PROJECT_DIR}/src/math/axis_mac.sv
 
/trunk/sim/tests/tb_mnist_mlp/init_test.do
22,7 → 22,7
 
# vlog -f ./tb_pkg_files.f
vlog $env(LIB_BASE_DIR)/BFM/src/axis_video_frame/avf_pkg.sv
vlog $env(PROJECT_DIR)/sim/src/anf/anf_pkg.sv
vlog $env(LIB_BASE_DIR)/BFM/src/anf/anf_pkg.sv
 
vlog -f ./tb_files.f
 
/trunk/sim/tests/tb_mnist_mlp/tb_top.sv
31,20 → 31,21
import tb_top_pkg::*;
 
// --------------------------------------------------------------------
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
localparam realtime PERIODS[1] = '{10ns};
localparam CLOCK_COUNT = $size(PERIODS);
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
// --------------------------------------------------------------------
wire aclk = clk_100mhz;
wire tb_rst_s;
wire aresetn = ~tb_rst_s;
bit tb_clk[CLOCK_COUNT];
wire tb_aresetn;
bit tb_reset[CLOCK_COUNT];
 
sync_reset sync_reset(aclk, tb_rst, tb_rst_s);
tb_base #(.N(CLOCK_COUNT), .PERIODS(PERIODS)) tb(.*);
 
// --------------------------------------------------------------------
wire aclk = tb_clk[0];
wire aresetn = ~tb_reset[0];
 
// --------------------------------------------------------------------
axis_if #(.N(N), .U(U)) axis_in(.*);
axis_if #(.N(N), .U(U)) axis_out(.*);
axis_if #(.N(N), .U(U)) axis_stub(.*);
72,11 → 73,11
// repeat(16) @(posedge aclk);
// $stop;
end
 
// // --------------------------------------------------------------------
// int in_index = 0;
// real in_data;
 
// initial
// fork
// forever @(negedge aclk)
97,7 → 98,7
// --------------------------------------------------------------------
int out_index = 0;
real out_data;
 
initial
fork
forever @(negedge aclk)
/trunk/sim/tests/tb_xor/files.f
2,8 → 2,8
 
${LIB_BASE_DIR}/axi4_stream_lib/src/recursive_axis_catenate.sv
 
${PROJECT_DIR}/src/fpga/rom.sv
${PROJECT_DIR}/src/fpga/axis_rom.sv
${LIB_BASE_DIR}/basal/src/ROM/rom.sv
${LIB_BASE_DIR}/basal/src/ROM/axis_rom.sv
 
${PROJECT_DIR}/src/math/axis_mac.sv
 
/trunk/sim/tests/tb_xor/init_test.do
22,7 → 22,7
 
# vlog -f ./tb_pkg_files.f
vlog $env(LIB_BASE_DIR)/BFM/src/axis_video_frame/avf_pkg.sv
vlog $env(PROJECT_DIR)/sim/src/anf/anf_pkg.sv
vlog $env(LIB_BASE_DIR)/BFM/src/anf/anf_pkg.sv
 
vlog -f ./tb_files.f
 
/trunk/sim/tests/tb_xor/tb_top.sv
31,20 → 31,21
import tb_top_pkg::*;
 
// --------------------------------------------------------------------
wire clk_100mhz;
wire tb_clk = clk_100mhz;
wire tb_rst;
localparam realtime PERIODS[1] = '{10ns};
localparam CLOCK_COUNT = $size(PERIODS);
 
tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);
 
// --------------------------------------------------------------------
wire aclk = clk_100mhz;
wire tb_rst_s;
wire aresetn = ~tb_rst_s;
bit tb_clk[CLOCK_COUNT];
wire tb_aresetn;
bit tb_reset[CLOCK_COUNT];
 
sync_reset sync_reset(aclk, tb_rst, tb_rst_s);
tb_base #(.N(CLOCK_COUNT), .PERIODS(PERIODS)) tb(.*);
 
// --------------------------------------------------------------------
wire aclk = tb_clk[0];
wire aresetn = ~tb_reset[0];
 
// --------------------------------------------------------------------
axis_if #(.N(N), .U(U)) axis_in(.*);
axis_if #(.N(N), .U(U)) axis_out(.*);
axis_if #(.N(N), .U(U)) axis_stub(.*);
72,11 → 73,11
// repeat(16) @(posedge aclk);
// $stop;
end
 
// --------------------------------------------------------------------
int in_index = 0;
real in_data;
 
initial
fork
forever @(negedge aclk)
97,7 → 98,7
// --------------------------------------------------------------------
int out_index = 0;
real out_data;
 
initial
fork
forever @(negedge aclk)
/trunk/src/xor/xor.h5 Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
trunk/src/xor/xor.h5 Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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