URL
https://opencores.org/ocsvn/lattice6502/lattice6502/trunk
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- This comparison shows the changes necessary to convert path
/lattice6502/ispLeaver
- from Rev 3 to Rev 6
- ↔ Reverse comparison
Rev 3 → Rev 6
/65C02.vhd
5,14 → 5,17
-- |
-- This file is part of the Lattice 6502 project |
-- It is used to compile with Linux ghdl and ispLeaver. |
-- email author@kool.kor |
-- author EQU ichapman |
-- kool EQU videotron |
-- kor EQU ca |
-- |
-- |
-- To do |
-- Detailed test of all instructions. |
-- |
-- ************************************************************* |
-- Distributed under the GNU Lesser General Public License. * |
-- This can be obtained from www.gnu.org. * |
-- This can be obtained from www.gnu.org. * |
-- ************************************************************* |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
57,7 → 60,7
-- 1 DONE Update all address modes of cmp, cpx and cpy per #mode |
-- 2 DONE Add rol, ror, asl, lsr, per inc and dec |
-- 3 DONE Correct flags in all modes of item 2 |
-- 4 Update the stack instructions, I've it pushing up not down. |
-- 4 DONE Update the stack instructions, I've it pushing up not down. |
-- 5 Continue testing |
-- 6 DONE Get a kernel up to test each and every instruction |
-- 7 Test all instructions |
65,6 → 68,14
-- and ply are the most useful. |
------------------------------------------------------------------------------------ |
-- Revision history |
-- Dec 3, 2010 |
-- Interrupts BRK, IRQ and NMI checked out seem okay. |
-- Fixed stack to push down pull up. |
-- addressing (zero,x) corrected. |
-- CLV error corrected. |
-- rol, ror, asl and lsr shift instructions checked and fixed. |
-- Nov 17, 2010 |
-- Corrected BRK, IRQ, NMI and RTI due to error in status byte. |
-- Nov 4, 2010 |
-- Rationalized all flavours of cmp, cpy and cpx. |
-- Changed jsr to combine out_dat1 and out_dat2 into out_dat. |
111,7 → 122,7
signal flags_fg : unsigned(1 downto 0); |
|
|
signal reset_fg, irq_fg, nmi_fg, start_fg, pc_inc_fg, branch_fg: std_logic; |
signal reset_fg, irq_fg, nmi_ff1, nmi_ff2, nmi_req, nmi_fg, start_fg, pc_inc_fg, branch_fg: std_logic; |
signal pc_dec_fg, dat2pc_fg : std_logic; |
-- End of signal declarations |
|
129,7 → 140,8
dat_in1 <= data_rd; |
|
if cycle_ctr = x"0" then |
if irq = '0' or nmi = '0' or (reset = '1' and reset_fg = '0') then |
-- if (i_fg = '0' and (irq = '0' or nmi_req = '0')) or (reset = '1' and reset_fg = '0') then |
if (i_fg = '0' and irq = '0') or nmi_req = '0' or (reset = '1' and reset_fg = '0') then |
Instruction_in <= x"00"; |
else |
Instruction_in <= data_rd; |
148,7 → 160,8
reg_pc(15 downto 8) <= data_rd; |
reg_pc(7 downto 0) <= dat_in1; |
|
elsif (cycle_ctr = X"0" and not(irq = '0' or nmi = '0' )) or pc_inc_fg = '1' then |
-- elsif (cycle_ctr = X"0" and not(irq = '0' or nmi = '0' )) or pc_inc_fg = '1' then |
elsif cycle_ctr = X"0" or pc_inc_fg = '1' then |
reg_pc <= reg_pc + x"0001"; |
|
elsif pc_dec_fg = '1' then |
163,8 → 176,9
end if; |
end process Prog_ptr; |
|
addressing:process (clock, reset, reg_PC, add_fg) |
addressing:process (reset, proc_write, data_rd, dat_in1, dat_in2, reg_x, reg_y, reg_sp, add_hold, reg_PC, add_fg) |
begin |
|
if reset = '0' then |
address <= reg_pc; |
else |
206,7 → 220,7
address <= dat_in1 & dat_in2 + reg_x; |
end if; |
when x"6" => --Absolute, y |
address <= (data_rd & dat_in1) + reg_y; |
-- address <= (data_rd & dat_in1) + reg_y; |
|
if proc_write = '0' then |
address <= data_rd & dat_in1 + reg_y; |
230,7 → 244,7
when x"D" => --(zero,x) |
address(7 downto 0) <= dat_in1 + reg_x + "1"; |
address(15 downto 8) <= x"00"; |
when x"F" => --Hold address steady for INC etc |
when x"F" => --Hold addre nmi_ff1 <= '0';ss steady for INC etc |
address <= add_hold; |
when others => |
address <= reg_pc; |
252,11 → 266,12
if reset = '0' then |
data_wr <= (others => '0'); |
proc_write <= '0'; |
|
elsif rising_edge(clock) then |
proc_write <= wr_fg; |
if wr_fg = '1' then |
-- if wr_fg = '1' then |
data_wr <= dat_out; |
end if; |
-- end if; |
end if; |
end process memory_proc_write; |
|
274,17 → 289,19
reg_a <= (others => '0'); |
reg_x <= (others => '0'); |
reg_y <= (others => '0'); |
reg_s <= (others => '0'); |
reg_sp <= (others => '0'); |
reg_sp <= (others => '1'); |
n_fg <= '0'; |
v_fg <= '0'; |
b_fg <= '0'; |
d_fg <= '0'; |
i_fg <= '0'; |
i_fg <= '1'; |
z_fg <= '0'; |
reset_fg <= '0'; |
start_fg <= '0'; |
v_ff <= '0'; |
nmi_ff1 <= '1'; |
nmi_ff2 <= '1'; |
nmi_req <= '1'; |
nmi_fg <= '0'; |
irq_fg <= '0'; |
dat_out <= (others => '0'); |
291,6 → 308,12
|
elsif rising_edge(clock) then |
reset_fg <= reset; |
-- This is to generate a nmi_req from neg transition on nmi input |
nmi_ff1 <= nmi; |
nmi_ff2 <= nmi_ff1; |
if nmi_fg = '0' and nmi_ff2 = '1' and nmi = '0' then |
nmi_req <= '0'; |
end if; |
|
-- This section is to get started |
if reset = '1' and reset_fg = '0' then |
297,7 → 320,7
start_fg <= '1'; |
wr_fg <= '0'; |
add_fg <= x"8"; --get start up vectors FFFC FFFD |
cycle_ctr <= x"5"; --Jump into cycle 5 add_fg <= x'8' |
cycle_ctr <= x"7"; --Jump into cycle 7 add_fg <= x'8' |
-- end if; |
else |
|
325,12 → 348,10
|
if irq = '0' and i_fg = '0' then |
irq_fg <= '1'; |
b_fg <= '0'; |
pc_dec_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
elsif nmi = '0' and i_fg = '0' then |
elsif nmi_req = '0' then |
nmi_fg <= '1'; |
b_fg <= '0'; |
pc_dec_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
else |
345,22 → 366,21
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"08" => --PHP 1st part status onto stack |
pc_dec_fg <= '1'; |
pc_dec_fg <= '1'; --php needs extra cycle to propagate flags |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"68" => --PLA 1st part Pull Accumulator from Stack |
reg_sp <= reg_sp - "1"; |
reg_sp <= reg_sp + "1"; --plus |
pc_dec_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"28" => --PLP 1st part pull old status from stack |
reg_sp <= reg_sp - "1"; |
reg_sp <= reg_sp + "1"; --plus |
pc_dec_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"18" => --CLC clear carry |
reg_a(8) <= '0'; |
-- pc_dec_fg <= '1'; |
cycle_ctr <= x"0"; |
|
when x"38" => --SEC set carry |
390,7 → 410,6
cycle_ctr <= x"0"; |
when x"B8" => --CLV clear overflow flag |
v_fg <= '0'; |
pc_dec_fg <= '1'; |
cycle_ctr <= x"0"; |
when x"C8" => --INY increment Y reg |
reg_y <= reg_y + x"1"; |
632,7 → 651,7
add_fg <= x"2"; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"36" => --ROL zero,X 1st part |
add_fg <= x"1"; |
add_fg <= x"2"; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"45" => --EOR zero 1st part |
add_fg <= x"1"; |
806,31 → 825,26
-- ============================================================================== |
|
|
when x"4C" => --JMP abs first part |
when x"4C" => --JMP abs 1st part |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"6C" => --JMP indirect first part |
when x"6C" => --JMP indirect 1st part |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"20" => --JSR abs first part |
when x"20" => --JSR abs 1st part |
cycle_ctr <= cycle_ctr + x"1"; |
when x"60" => --RTS first part |
reg_sp <= reg_sp - "1"; |
when x"60" => --RTS 1st part |
reg_sp <= reg_sp + "1"; --plus |
add_fg <= x"7"; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"40" => --RTI 1st part pull old status from stack |
reg_sp <= reg_sp - "1"; |
reg_sp <= reg_sp + "1"; --plus |
add_fg <= x"7"; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"00" => --Break first part cyc 0 |
if irq_fg = '0' then --Start up, irq and nmi also use |
b_fg <= '1'; --this set of logic. |
else |
b_fg <= '0'; |
end if; |
pc_dec_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"00" => --Break 1st part cyc 0 |
pc_dec_fg <= '1'; --Start up, irq and nmi also use. |
cycle_ctr <= cycle_ctr + x"1"; --this set of logic. |
|
when others => |
cycle_ctr <= x"0"; |
1232,9 → 1246,12
add_fg <= x"5"; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"B9" => --LDA, Y abs 2nd part. |
|
|
add_fg <= x"6"; |
cycle_ctr <= cycle_ctr + x"1"; |
|
|
when x"2D" => --AND abs 2nd part. |
add_fg <= x"4"; |
cycle_ctr <= cycle_ctr + x"1"; |
1390,18 → 1407,16
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"60" => --RTS second part |
reg_sp <= reg_sp - "1"; |
reg_sp <= reg_sp + "1"; --plus |
cycle_ctr <= cycle_ctr + x"1"; |
when x"40" => --RTI second part pull old status from stack |
reg_sp <= reg_sp - "1"; |
reg_sp <= reg_sp + "1"; --plus |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"00" => --Break second part cyc 1 |
dat2pc_fg <= '0'; |
wr_fg <= '1'; --put dat_out onto stack |
dat_out <= reg_pc(15 downto 8); |
add_fg <= x"7"; |
pc_dec_fg <= '0'; |
when x"00" => --Break 2nd part cyc 1 |
if irq_fg = '0' and nmi_fg = '0' then --Start up, irq and nmi also use |
pc_dec_fg <= '0'; --this set of logic. |
end if; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when others => |
1419,7 → 1434,7
when x"48" => --PHA 3rd part accumulator onto stack |
pc_inc_fg <= '1'; |
add_fg <= x"0"; |
reg_sp <= reg_sp + "1"; |
reg_sp <= reg_sp - "1"; --neg |
cycle_ctr <= cycle_ctr + x"1"; |
when x"08" => --PHP 3rd part Status reg onto stack |
wr_fg <= '0'; |
1702,65 → 1717,64
cycle_ctr <= cycle_ctr + "1"; |
when x"F6" => --INC zero,X 3rd part |
dat_out <= data_rd + x"01"; |
|
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
|
when x"66" => --ROR zero 3rd part |
dat_out(6 downto 0) <= data_rd(7 downto 1); |
dat_out(7) <= reg_a(8); |
reg_a(8) <= data_rd(0); |
dat_out <= reg_a(8) & data_rd(7 downto 1); |
flags_fg <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
|
when x"76" => --ROR zero,X 3rd part |
dat_out(6 downto 0) <= data_rd(7 downto 1); |
dat_out(7) <= reg_a(8); |
reg_a(8) <= data_rd(0); |
dat_out <= reg_a(8) & data_rd(7 downto 1); |
flags_fg <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
|
when x"26" => --ROL zero 3rd part |
dat_out(7 downto 1) <= data_rd(6 downto 0); |
dat_out(0) <= reg_a(8); |
dat_out(7 downto 0) <= data_rd(6 downto 0) & reg_a(8); |
reg_a(8) <= data_rd(7); |
flags_fg <= "01"; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"36" => --ROL zero,X 3rd part |
dat_out(7 downto 1) <= data_rd(6 downto 0); |
dat_out(0) <= reg_a(8); |
dat_out(7 downto 0) <= data_rd(6 downto 0) & reg_a(8); |
reg_a(8) <= data_rd(7); |
flags_fg <= "01"; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"46" => --LSR zero 3rd part |
dat_out <= '0' & reg_a(7 downto 1); |
dat_out <= '0' & data_rd(7 downto 1); |
reg_a(8) <= data_rd(0); |
flags_fg <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"56" => --LSR zero,X 3rd part |
dat_out <= '0' & reg_a(7 downto 1); |
dat_out <= '0' & data_rd(7 downto 1); |
reg_a(8) <= data_rd(0); |
flags_fg <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"06" => --ASL zero 3rd part |
reg_a(8) <= data_rd(7); |
dat_out <= data_rd(6 downto 0) & '0'; |
flags_fg <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"16" => --ASL zero,X 3rd part |
reg_a(8) <= data_rd(7); |
dat_out <= data_rd(6 downto 0) & data_rd(0); |
wr_fg <= '1'; |
dat_out <= data_rd(6 downto 0) & '0'; |
flags_fg <= "01"; |
wr_fg <= '1'; wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
|
-- ============================================================================================= |
when x"A1" => --LDA (zero,x) 3rd part proto |
add_fg <= x"6"; |
add_fg <= x"4"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"B1" => --LDA (zero),y 3rd part proto |
add_fg <= x"6"; |
1767,7 → 1781,7
cycle_ctr <= cycle_ctr + "1"; |
|
when x"21" => --AMD (zero,x) 3rd part proto |
add_fg <= x"6"; |
add_fg <= x"4"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"31" => --AND (zero),y 3rd part proto |
add_fg <= x"6"; |
1774,7 → 1788,7
cycle_ctr <= cycle_ctr + "1"; |
|
when x"41" => --EOR (zero,x) 3rd part proto |
add_fg <= x"6"; |
add_fg <= x"4"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"51" => --EOR (zero),y 3rd part proto |
add_fg <= x"6"; |
1781,7 → 1795,7
cycle_ctr <= cycle_ctr + "1"; |
|
when x"01" => --OR (zero,x) 3rd part proto |
add_fg <= x"6"; |
add_fg <= x"4"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"11" => --OR (zero),y 3rd part proto |
add_fg <= x"6"; |
1788,7 → 1802,7
cycle_ctr <= cycle_ctr + "1"; |
|
when x"61" => --ADC (zero,x) 3rd part proto |
add_fg <= x"6"; |
add_fg <= x"4"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"71" => --ADC (zero),y 3rd part proto |
add_fg <= x"6"; |
1795,7 → 1809,7
cycle_ctr <= cycle_ctr + "1"; |
|
when x"E1" => --SBC (zero,x) 3rd part proto |
add_fg <= x"6"; |
add_fg <= x"4"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"F1" => --SBC (zero),y 3rd part proto |
add_fg <= x"6"; |
1802,7 → 1816,7
cycle_ctr <= cycle_ctr + "1"; |
|
when x"C1" => --CMP (zero,x) 3rd part proto |
add_fg <= x"6"; |
add_fg <= x"4"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"D1" => --CMP (zero),y 3rd part proto |
add_fg <= x"6"; |
2022,7 → 2036,7
wr_fg <= '1'; |
dat_out <= reg_pc(7 downto 0); |
cycle_ctr <= cycle_ctr + x"1"; |
when x"60" => --RTS third part |
when x"60" => --RTS 3rd part |
dat2pc_fg <= '1'; |
add_fg <= x"0"; |
cycle_ctr <= cycle_ctr + x"1"; |
2035,13 → 2049,19
i_fg <= data_rd(2); |
z_fg <= data_rd(1); |
reg_a(8) <= data_rd(0); |
reg_sp <= reg_sp - "1"; |
dat2pc_fg <= '1'; |
reg_sp <= reg_sp + "1"; --plus |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"00" => --Break third part cyc 2 |
dat_out <= reg_pc(7 downto 0); --put dat_out onto stack set up dat_out |
reg_sp <= reg_sp + "1"; |
when x"00" => --Break 3rd part cyc 2 |
if irq_fg = '0' and nmi_fg = '0' then --Start up, irq and nmi also use |
b_fg <= '1'; --this set of logic. |
else |
b_fg <= '0'; |
end if; |
wr_fg <= '1'; --put dat_out onto stack |
dat_out <= reg_pc(15 downto 8); |
add_fg <= x"7"; |
pc_dec_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when others => |
2091,7 → 2111,7
when x"08" => --PHP 4th part accumulator onto stack |
pc_inc_fg <= '1'; |
add_fg <= x"0"; |
reg_sp <= reg_sp + "1"; |
reg_sp <= reg_sp - "1"; --neg |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"48" => --PHA 4th part accumulator onto stack |
2106,7 → 2126,7
when x"28" => --PLP 4th part Pull Status from Stack |
n_fg <= data_rd(7); |
v_fg <= data_rd(6); |
-- b_fg <= data_rd(4); |
b_fg <= data_rd(4); |
d_fg <= data_rd(3); |
i_fg <= data_rd(2); |
z_fg <= data_rd(1); |
2398,53 → 2418,55
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"2E" => --ROL abs 4th part. |
dat_out(7 downto 1) <= data_rd(6 downto 0); |
dat_out(0) <= reg_a(8); |
dat_out(7 downto 0) <= data_rd(6 downto 0) & reg_a(8); |
reg_a(8) <= data_rd(7); |
flags_fg <= "01"; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"3E" => --ROL, x abs 4th part. |
dat_out(7 downto 1) <= data_rd(6 downto 0); |
dat_out(0) <= reg_a(8); |
dat_out(7 downto 0) <= data_rd(6 downto 0) & reg_a(8); |
reg_a(8) <= data_rd(7); |
flags_fg <= "01"; |
wr_fg <= '1'; |
cycle_ctr <= cycle_ctr + "1"; |
when x"6E" => --ROR abs 4th part. |
dat_out(6 downto 0) <= data_rd(7 downto 1); |
dat_out(7) <= reg_a(8); |
reg_a(8) <= data_rd(0); |
dat_out <= reg_a(8) & data_rd(7 downto 1); |
flags_fg <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"7E" => --ROR, x abs 4th part. |
dat_out(6 downto 0) <= data_rd(7 downto 1); |
dat_out(7) <= reg_a(8); |
reg_a(8) <= data_rd(0); |
dat_out <= reg_a(8) & data_rd(7 downto 1); |
flags_fg <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + x"1"; |
when x"4E" => --LSR abs 4th part. |
dat_out <= '0' & reg_a(7 downto 1); |
dat_out <= '0' & data_rd(7 downto 1); |
reg_a(8) <= data_rd(0); |
flags_fg <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"5E" => --LSR, x abs 4th part. |
dat_out <= '0' & reg_a(7 downto 1); |
dat_out <= '0' & data_rd(7 downto 1); |
reg_a(8) <= data_rd(0); |
flags_fg <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"0E" => --ASL abs 4th part. |
reg_a(8) <= data_rd(7); |
dat_out <= data_rd(6 downto 0) & data_rd(0); |
dat_out <= data_rd(6 downto 0) & '0'; |
flags_fg <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + x"1"; |
cycle_ctr <= cycle_ctr + "1"; |
when x"1E" => --ASL, x abs 4th part. |
reg_a(8) <= data_rd(7); |
dat_out <= data_rd(6 downto 0) & data_rd(0); |
dat_out <= data_rd(6 downto 0) & '0'; |
flags_fg <= "01"; |
wr_fg <= '1'; |
flags_fg <= "01"; |
cycle_ctr <= cycle_ctr + x"1"; |
cycle_ctr <= cycle_ctr + "1"; |
-- ............................................................................ |
-- ============================================================================== |
when x"A1" => --LDA (zero,x) 4th part proto |
2537,7 → 2559,7
cycle_ctr <= cycle_ctr + x"1"; |
when x"20" => --JSR indirect 4th part |
wr_fg <= '0'; |
reg_sp <= reg_sp + "1"; |
reg_sp <= reg_sp - "1"; --neg |
cycle_ctr <= cycle_ctr + x"1"; |
when x"60" => --RTS fourth part |
dat2pc_fg <= '0'; |
2545,14 → 2567,12
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"40" => --RTI forth part |
-- reg_sp <= reg_sp - "1"; |
add_fg <= x"7"; --Get 2nd PC byte |
dat2pc_fg <= '0'; |
dat2pc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"00" => --Break forth extra part cyc 3 |
dat_out <= n_fg & v_fg & '1' & b_fg & d_fg & i_fg & z_fg & reg_a(8); |
reg_sp <= reg_sp + "1"; |
when x"00" => --Break 4th part cyc 3 |
dat_out <= reg_pc(7 downto 0); --put dat_out onto stack set up dat_out |
cycle_ctr <= cycle_ctr + x"1"; |
|
-------------------------------------------------------------------------------------- |
2931,7 → 2951,7
when x"20" => --JSR 5th part |
pc_inc_fg <= '1'; |
add_fg <= x"0"; |
reg_sp <= reg_sp + "1"; |
reg_sp <= reg_sp - "1"; --neg |
cycle_ctr <= cycle_ctr + x"1"; |
when x"60" => --RTS fifth part |
dat2pc_fg <= '0'; |
2940,20 → 2960,14
when x"40" => --RTI fifth part |
-- reg_sp <= reg_sp + "1"; |
add_fg <= x"0"; |
-- dat2pc_fg <= '0'; |
dat2pc_fg <= '0'; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"00" => --Break fifth part cyc 4 |
wr_fg <= '0'; |
reg_sp <= reg_sp + "1"; |
if nmi_fg = '0' then |
add_fg <= x"9"; --Complete stacking start getting vector |
else |
add_fg <= x"A"; |
end if; |
when x"00" => --Break 5th extra part cyc 4 |
dat_out <= n_fg & v_fg & '1' & b_fg & d_fg & i_fg & z_fg & reg_a(8); |
reg_sp <= reg_sp - "1"; --neg |
cycle_ctr <= cycle_ctr + x"1"; |
|
|
when others => |
cycle_ctr <= cycle_ctr + x"1"; |
|
3055,6 → 3069,7
add_fg <= x"0"; |
cycle_ctr <= cycle_ctr + x"1"; |
-- ........................................................................................ |
|
when x"6C" => --JMP indirect 6th part |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
3064,8 → 3079,7
cycle_ctr <= x"0"; |
|
when x"40" => --RTI sixth part |
cycle_ctr <= cycle_ctr + x"1"; |
pc_inc_fg <= '1'; |
pc_inc_fg <= '1'; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when x"20" => --JSR 6th part |
3073,10 → 3087,9
cycle_ctr <= x"0"; |
|
when x"00" => --Break 6th part cyc 5 |
add_fg <= x"B"; |
irq_fg <= '0'; |
nmi_fg <= '0'; |
cycle_ctr <= cycle_ctr + "1"; |
wr_fg <= '0'; |
reg_sp <= reg_sp - "1"; --neg |
cycle_ctr <= cycle_ctr + x"1"; |
|
when others => |
|
3127,9 → 3140,14
cycle_ctr <= x"0"; |
|
when x"00" => --Break 7th part cyc 6 |
dat2pc_fg <= '1'; |
add_fg <= x"0"; |
cycle_ctr <= cycle_ctr + "1"; |
wr_fg <= '0'; |
reg_sp <= reg_sp - "1"; --neg |
if nmi_fg = '0' then |
add_fg <= x"9"; --Complete stacking start getting vector |
else |
add_fg <= x"A"; |
end if; |
cycle_ctr <= cycle_ctr + x"1"; |
|
when others => |
cycle_ctr <= x"0"; |
3149,15 → 3167,15
cycle_ctr <= x"0"; |
|
when x"00" => --Break 8th part cyc 7 |
if start_fg = '0' then --When starting don't mess with this |
i_fg <= '1'; --Break irq and start use this logic. |
add_fg <= x"B"; |
irq_fg <= '0'; |
nmi_fg <= '0'; |
nmi_req <= '1'; |
if irq_fg = '1' then |
i_fg <= '1'; |
end if; |
pc_inc_fg <= '1'; |
start_fg <= '0'; |
dat2pc_fg <= '0'; |
cycle_ctr <= cycle_ctr + "1"; |
|
|
when others => |
cycle_ctr <= x"0"; |
|
3165,25 → 3183,27
-- Cycle 7 |
when x"8" => |
case Instruction_in is |
when x"00" => --Break 9th part cyc 8 |
dat2pc_fg <= '1'; |
add_fg <= x"0"; |
cycle_ctr <= cycle_ctr + "1"; |
|
when x"00" => --Break 10th part cyc 8 |
pc_inc_fg <= '0'; |
when others => |
cycle_ctr <= x"0"; |
|
when others => |
cycle_ctr <= cycle_ctr + "1"; |
pc_inc_fg <= '0'; |
|
end case; --Cycle 8 |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
-- Cycle 9 |
when x"9" => |
case Instruction_in is |
when x"00" => --Break 10th part cyc 9 |
pc_inc_fg <= '1'; |
start_fg <= '0'; |
dat2pc_fg <= '0'; |
cycle_ctr <= cycle_ctr + "1"; |
|
when others => |
cycle_ctr <= cycle_ctr + "1"; |
pc_inc_fg <= '0'; |
|
cycle_ctr <= x"0"; |
end case; --Cycle 9 |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
-- Cycle A |
3190,8 → 3210,10
|
when x"A" => |
case Instruction_in is |
when x"00" => --Break 11th part cyc 10 |
pc_inc_fg <= '0'; |
cycle_ctr <= x"0"; |
|
|
when others => |
cycle_ctr <= cycle_ctr + "1"; |
pc_inc_fg <= '0'; |
/Processor.vhd
2,12 → 2,21
-- 6502 Top module. |
-- |
-- Copyright Ian Chapman October 28 2010 |
-- |
-- This file is part of the Lattice 6502 project |
-- email author@kool.kor |
-- author EQU ichapman |
-- kool EQU videotron |
-- kor EQU ca |
-- ****************************************************** |
-- Dec 12 2010 |
-- RAM increased to 2k 0 to $7ff for bigger test code |
-- sta irq and sta nmi trigger interrupts |
-- ****************************************************** |
-- This file is part of the Lattice 6502 project |
-- It is used to compile with ispLeaver not Linux ghdl. |
-- It is the address mapping and connecting the other modules. |
-- It is replaced by Processor.vhd when running ispLeaver. |
-- |
|
-- To do |
-- This will be work in process or replaced whatever |
-- project file is needed to control other modules. |
31,6 → 40,12
-- |
-- Processor.vhd |
------------------------------------------------------------------ |
-- Revision history |
-- Nov 411, 2010 |
-- To facilitate testing of NMI and IRQ. |
-- changed from I/O pins to signals |
-- IRQ and NMI address decoded so as to initiated the inerupt from |
------------------------------------------------------------------ |
library IEEE; --Use standard IEEE libs as recommended by Tristan. |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.numeric_std.all; |
49,8 → 64,8
-- u701 : out std_logic; |
u601 : out std_logic; |
rst_pin : in std_logic; |
irq_pin : in std_logic; |
nmi_pin : in std_logic; |
-- irq_pin : in std_logic; --disabled to test interrupts on fpga |
-- nmi_pin : in std_logic; |
RX_pin : in std_logic; |
-- PG_pin : in std_logic; |
TX_pin : out std_logic; |
105,7 → 120,7
ClockEn: in std_logic; |
Reset: in std_logic; |
WE: in std_logic; |
Address: in std_logic_vector(9 downto 0); |
Address: in std_logic_vector(10 downto 0); |
Data: in std_logic_vector(7 downto 0); |
Q: out std_logic_vector(7 downto 0)); |
end component; |
143,9 → 158,12
--signal clk_pin : std_logic; |
signal counter : unsigned(3 downto 0); |
signal ram_write : std_logic; |
signal irq_pin, nmi_pin : std_logic; |
|
-- I/O ports |
constant led_port : unsigned (15 downto 0) := x"4007"; |
--constant led_port : unsigned (15 downto 0) := x"4007"; |
constant irq : unsigned (15 downto 0) := X"4002"; |
constant nmi : unsigned (15 downto 0) := x"4003"; |
constant rs232_dat : unsigned (15 downto 0) := x"4000"; --input and output |
constant uart_stat : unsigned (15 downto 0) := x"4001"; --RX and TX state found here |
constant uart: unsigned (15 downto 0) := x"4000"; --starts the uart transmitting |
206,7 → 224,7
Reset => rst_bar, |
Clock => clk_pin, |
WE => ram_write, |
address(9 downto 0) => std_logic_vector(Address(9 downto 0)), |
address(10 downto 0) => std_logic_vector(Address(10 downto 0)), |
Data => std_logic_vector(data_wr), |
unsigned(Q) => ram_dat, ClockEn => one); |
|
217,6 → 235,10
one <= '1'; |
rst_bar <= not rst_pin; |
one <= '1'; |
--ram_write <= proc_write and not address(15) and not address(14) and not address(13) and not address(12) and not address(11) and not address(10); |
--ram_write <= proc_write and not address(15) and not address(14); |
--irq_pin <= '1'; --only used to test interrupts on fpga |
--nmi_pin <= '1'; |
--u601 <= cycle_mark; |
|
|
272,18 → 294,40
else |
csw_usart <= '0'; |
end if; |
end process; |
-- Only uded to test interrupts in the fpga |
-- These two processe let the SW fire NMI and IRG |
-- with a sta instruction. |
irq : process (rst_pin, proc_write, address, data_wr(0), clk_pin) |
begin |
if rst_pin = '0' then |
irq_pin <= '1'; |
elsif rising_edge(clk_pin) then |
if address = irq and proc_write = '1' then |
irq_pin <= data_wr(0); --set and hold bit 0 |
end if; |
end if; |
end process; |
|
|
|
relay : process (rst_pin, proc_write, address, data_wr(7), clk_pin) |
nmi : process (rst_pin, proc_write, address, data_wr(0), clk_pin) |
begin |
if rst_pin = '0' then |
Pwr_on_pin <= '0'; |
elsif rising_edge(clk_pin) and address = led_port and proc_write = '1' then |
Pwr_on_pin <= data_wr(7); |
nmi_pin <= '1'; |
elsif rising_edge(clk_pin) then |
if address = nmi and proc_write = '1' then |
nmi_pin <= data_wr(0); --set and hold bit 0 |
end if; |
end if; |
end process; |
|
--relay : process (rst_pin, proc_write, address, data_wr(7), clk_pin) |
--begin |
--if rst_pin = '0' then |
-- Pwr_on_pin <= '0'; |
-- elsif rising_edge(clk_pin) and address = led_port and proc_write = '1' then |
-- Pwr_on_pin <= data_wr(7); |
--end if; |
--end process; |
|
|
end structure; |