URL
https://opencores.org/ocsvn/lattice6502/lattice6502/trunk
Subversion Repositories lattice6502
Compare Revisions
- This comparison shows the changes necessary to convert path
/lattice6502
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/ghdl/kernel4.mem
680,16 → 680,90
45 |
46 |
A9 |
01 |
8D |
03 |
40 |
A9 |
4E |
20 |
0D |
FE |
A9 |
4D |
20 |
0D |
FE |
A9 |
49 |
20 |
0D |
FE |
A9 |
0D |
20 |
0D |
FE |
40 |
68 |
48 |
29 |
10 |
F0 |
17 |
A9 |
42 |
20 |
0D |
FE |
A9 |
52 |
20 |
0D |
FE |
A9 |
4B |
20 |
0D |
FE |
A9 |
0D |
20 |
0D |
FE |
4C |
F8 |
FE |
A9 |
01 |
8D |
02 |
40 |
A9 |
01 |
8D |
02 |
40 |
A9 |
49 |
20 |
0D |
FE |
A9 |
52 |
20 |
0D |
FE |
A9 |
51 |
20 |
0D |
FE |
A9 |
0D |
20 |
0D |
FE |
40 |
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938,80 → 1012,6
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4C |
0D |
FE |
1026,5 → 1026,5
FE |
00 |
FC |
A9 |
BD |
FE |
/ghdl/kernel4.asm
17,6 → 17,10
dat232 equ $4000 |
stat232 equ $4001 |
tx232 equ $4000 |
irq equ $4002 |
nmi equ $4003 |
break equ $10 |
intrpt equ $04 |
|
;dat232 equ $290 ;used to help debug |
;stat232 equ $291 |
398,7 → 402,10
txt2hex ldy #$0 |
sty hexword |
sty hexword + 1 |
|
irq equ $4002 |
nmi equ $4003 |
break equ $10 |
intrpt equ $04 |
loophex ldx txtpt |
lda inbuff,x ;input buffer |
jsr inctxt ;inc counter |
456,21 → 463,55
|
page ;All the start up stuff |
|
nmi_srv lda #"N" |
nmi_srv lda #$01 |
sta nmi |
lda #"N" |
jsr sendtxt |
lda #"M" |
jsr sendtxt |
lda #"I" |
jsr sendtxt |
lda #"\r" |
jsr sendtxt |
rti |
|
irq_srv lda #"I" |
irq_srv pla |
pha |
and #break |
beq irqish |
lda #"B" |
jsr sendtxt |
rti |
lda #"R" |
jsr sendtxt |
lda #"K" |
jsr sendtxt |
lda #"\r" |
jsr sendtxt |
jmp endish |
|
|
irqish lda #$01 |
sta irq |
lda #$01 |
sta irq |
lda #"I" |
jsr sendtxt |
lda #"R" |
jsr sendtxt |
lda #"Q" |
jsr sendtxt |
lda #"\r" |
jsr sendtxt |
endish rti |
|
* =$fff0 |
jmp sendtxt ;Links for usrcode |
jmp hex2txt |
dw back2 |
dw back2 ;jmp ($FFF6) in user code. |
|
* = $fff8 |
; |
indjmp dw main |
nmi dw nmi_srv |
nmi_int dw nmi_srv |
rst dw main ;Should be main, this is for test only |
irq dw irq_srv |
irq_int dw irq_srv |
/ghdl/usrcode.asm
2,21 → 2,359
cpu 6502 |
PAGE 40,120 |
; **************************************************************************************** |
; This is intended to be the template for the user code |
; This is intended to be the template for the user code **** |
; **************************************************************************************** |
; These flags are used for conditional assembly. |
; Just select the instructions to be tested. |
shiftfg equ 0 |
intfg equ 0 |
Xfg equ 0 |
Yfg equ 0 |
AddXfg equ 0 |
AddYfg equ 1 |
; ******************************************************** |
|
* = $290 ;user code starts at $290 |
return equ $fff6 ;jump to fcoo to return control and restart |
sendtxt equ $fff0 |
hex2txt equ $fff3 |
irq equ $4002 |
nmi equ $4003 |
break equ $10 |
intrpt equ $04 |
|
* = $0010 |
point dw table2 |
dw table2 + 1 |
dw table2 + 2 |
dw table2 + 3 |
dw table2 + 4 |
dw table2 + 5 |
dw table2 + 6 |
dw table2 + 7 |
dw table2 + 8 |
; |
table3 db $00 |
bittbl1 db $1, $2, $4, $8, $10, $20, $40, $80 |
nottbl1 db $fe, $fd, $fa, $f7, $ef, $df, $bf, $7f |
|
main ldy #$55 |
ldx #$aa |
lda #$7e |
* = $290 ;user code starts at $290 |
|
main clc |
clv |
cli |
|
IF shiftfg |
; ***************************************************** |
; Shift instruction to be tested follows |
; Table2 abs and abs,x |
; Table2 zero and zero,x |
ldy #$a5 |
ldx #$03 |
lda #$5a |
|
sta table2 + 3 ;ror and rol test |
lda #$00 |
clc |
adc #$6 ;9-3=6 carry=0 |
php |
rol table2,x |
clc |
rol table2 + 3 |
sec |
rol table2 + 3 |
sec |
rol table2,x |
lda table2 + 3 |
|
sta table3 + 3 ;test asl lsr |
lda #$00 |
lsr table3,x |
lsr table3 + 3 |
lsr table3 + 3 |
lsr table3,x |
lda table3 + 3 |
; ***************************************************** |
lsr ;test all shift instruction implied |
lsr ;ie shift reg_a |
lsr |
lsr |
ENDC |
|
; ***************************************************** |
|
IF intfg |
; ***************************************************** |
; Testing of Interrupts |
; Comment in or out interrupt as required |
lda #$fe |
sta nmi |
|
; lda #$fe |
; sta irq |
|
; brk |
; **************************************************** |
ENDC |
|
IF Xfg |
; ***************************************************** |
ldx #$03 ;lda & eor test with reg_x |
ldy #1 ;First test zero and zero,x |
lda bittbl1 + 3 |
eor bittbl1,x ;should be 0 |
bne failtst |
ldy #2 |
lda bittbl1,x |
eor bittbl1 + 3 |
bne failtst |
|
ldx #$04 |
ldy #3 ;then abs |
lda bittbl2 + 4 |
eor bittbl2,x ;should be 0 |
bne failtst |
ldy #4 |
lda bittbl2,x |
eor bittbl2 + 4 |
bne failtst |
|
ldy #5 ;ora & and test with reg_x |
ldx #$05 ;First test zero and zero,x |
ora bittbl1 +5 ;set a bit |
and nottbl1,x ;clear it |
bne failtst |
ldy #6 |
ora bittbl1,x |
and nottbl1 + 5 |
bne failtst |
|
ldy #7 ;again using abs and abs,x |
ldx #$05 |
ora bittbl2 + 5 ;set a bit |
and nottbl2,x ;clear it |
bne failtst |
ldy #8 |
ora bittbl2,x |
and nottbl2 + 5 |
bne failtst |
|
passx lda #"P" |
jsr sendtxt |
lda #"a" |
jsr sendtxt |
lda #"s" |
jsr sendtxt |
lda #"s" |
jsr sendtxt |
lda #" " |
jsr sendtxt |
lda #"X" |
jsr sendtxt |
lda #"\r" |
jsr sendtxt |
|
jmp (return) |
|
ENDC |
; ***************************************************** |
IF Yfg |
; ***************************************************** |
ldy #$03 ;lda & eor test with reg_x |
ldx #1 ;First test zero and zero,y |
lda bittbl1 + 3 |
eor bittbl1,y ;should be 0 |
bne failtst |
ldx #2 |
lda bittbl1,y |
eor bittbl1 + 3 |
bne failtst |
|
ldy #$04 |
ldx #3 ;then abs |
lda bittbl2 + 4 |
eor bittbl2,y ;should be 0 |
bne failtst |
ldx #4 |
lda bittbl2,y |
eor bittbl2 + 4 |
bne failtst |
|
ldx #5 ;ora & and test with reg_x |
ldy #$05 ;First test zero and zero,y |
ora bittbl1 +5 ;set a bit |
and nottbl1,y ;clear it |
bne failtst |
ldx #6 |
ora bittbl1,y |
and nottbl1 + 5 |
bne failtst |
|
ldx #7 ;again using abs and abs,y |
ldy #$05 |
ora bittbl2 + 5 ;set a bit |
and nottbl2,y ;clear it |
bne failtst |
ldx #8 |
ora bittbl2,y |
and nottbl2 + 5 |
bne failtst |
|
passy lda #"P" |
jsr sendtxt |
lda #"a" |
jsr sendtxt |
lda #"s" |
jsr sendtxt |
lda #"s" |
jsr sendtxt |
lda #" " |
jsr sendtxt |
lda #"Y" |
jsr sendtxt |
lda #"\r" |
jsr sendtxt |
|
jmp (return) |
|
ENDC |
; ***************************************************** |
|
IF AddXfg |
; ***************************************************** |
ldx #$03 ;adc & sbc test with reg_x |
ldy #1 ;First test zero & zero,x |
clc |
lda #0 |
adc bittbl1 + 3 |
sbc bittbl1,x ;should be 0 |
bne failtst |
ldy #2 |
clc |
lda #0 |
adc bittbl1,x |
sbc bittbl1 + 3 |
bne failtst |
|
ldx #$04 |
ldy #3 ;then abs |
clc |
lda #0 |
adc bittbl2 + 4 |
sbc bittbl2,x ;should be 0 |
bne failtst |
ldy #4 |
clc |
lda #0 |
adc bittbl2,x |
sbc bittbl2 + 4 |
bne failtst |
|
ldy #5 ;ora & cmp test with reg_x |
ldx #$05 ;First test zero & zero,x |
ora bittbl1 +5 ;set a bit |
cmp bittbl1,x ;clear it |
bne failtst |
ldy #6 |
ora bittbl1,x |
cmp bittbl1 + 5 |
bne failtst |
|
ldy #7 ;again using abs cmp abs,x |
ldx #$05 |
ora bittbl2 + 5 ;set a bit |
cmp bittbl2,x ;clear it |
bne failtst |
ldy #8 |
ora bittbl2,x |
cmp bittbl2 + 5 |
bne failtst |
|
passx lda #"P" |
jsr sendtxt |
lda #"a" |
jsr sendtxt |
lda #"s" |
jsr sendtxt |
lda #"s" |
jsr sendtxt |
lda #" " |
jsr sendtxt |
lda #"A" |
jsr sendtxt |
lda #"\r" |
jsr sendtxt |
|
jmp (return) |
ENDC |
|
IF AddYfg |
; ***************************************************** |
ldy #$03 ;adc & sbc test with reg_x |
ldx #1 ;First test zero & zero,y |
clc |
lda #0 |
adc bittbl1 + 3 |
sbc bittbl1,y ;should be 0 |
bne failtst |
ldx #2 |
clc |
lda #0 |
adc bittbl1,y |
sbc bittbl1 + 3 |
bne failtst |
|
ldy #$04 |
ldx #3 ;then abs |
clc |
lda #0 |
adc bittbl2 + 4 |
sbc bittbl2,y ;should be 0 |
bne failtst |
ldx #4 |
clc |
lda #0 |
adc bittbl2,y |
sbc bittbl2 + 4 |
bne failtst |
|
ldy #5 ;ora & cmp test with reg_x |
ldx #$05 ;First test zero & zero,y |
ora bittbl1 +5 ;set a bit |
cmp bittbl1,y ;clear it |
bne failtst |
ldx #6 |
ora bittbl1,y |
cmp bittbl1 + 5 |
bne failtst |
|
ldx #7 ;again using abs cmp abs,y |
ldy #$05 |
ora bittbl2 + 5 ;set a bit |
cmp bittbl2,y ;clear it |
bne failtst |
ldx #8 |
ora bittbl2,y |
cmp bittbl2 + 5 |
bne failtst |
|
passx lda #"P" |
jsr sendtxt |
lda #"a" |
jsr sendtxt |
lda #"s" |
jsr sendtxt |
lda #"s" |
jsr sendtxt |
lda #" " |
jsr sendtxt |
lda #"C" |
jsr sendtxt |
lda #"\r" |
jsr sendtxt |
|
jmp (return) |
ENDC |
|
|
failtst php |
pha |
txa |
pha |
85,9 → 423,9
plp |
php |
beq clear3 |
lda #"1" |
lda #"0" |
jmp cont3 |
clear3 lda #"0" |
clear3 lda #"1" |
cont3 jsr sendtxt |
lda #" " |
jsr sendtxt |
97,15 → 435,70
lda #"=" |
jsr sendtxt |
plp |
php |
bpl clear4 |
lda #"1" |
jmp cont4 |
clear4 lda #"0" |
cont4 jsr sendtxt |
lda #" " |
jsr sendtxt |
|
lda #"I" ;Display Interrupt flag |
jsr sendtxt |
lda #"=" |
jsr sendtxt |
pla |
pha |
and #intrpt |
beq clear5 |
lda #"1" |
jmp cont5 |
clear5 lda #"0" |
cont5 jsr sendtxt |
lda #" " |
jsr sendtxt |
|
lda #"B" ;Display Break flag |
jsr sendtxt |
lda #"=" |
jsr sendtxt |
pla |
and #break |
beq clear6 |
lda #"1" |
jmp cont6 |
clear6 lda #"0" |
cont6 jsr sendtxt |
|
|
lda #"\r" |
jsr sendtxt |
jmp (return) |
|
bittbl2 db $1, $2, $4, $8, $10, $20, $40, $80 |
nottbl2 db $fe, $fd, $fa, $f7, $ef, $df, $bf, $7f |
|
* = $03e0 |
table2 db 0 |
db 1 |
db 2 |
db 3 |
db 4 |
db 5 |
db 6 |
db 7 |
db 8 |
db 9 |
db 10 |
db 11 |
db 12 |
db 13 |
db 14 |
db 15 |
|
* = $07ff |
nop ;I need this to mark end of bin code. |
|
|
; end of program |
/ghdl/ram2k.mem
0,0 → 1,2054
#Format=Hex |
#Depth=2048 |
#Width=8 |
#AddrRadix=3 |
#DataRadix=3 |
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/ghdl/ghdl_processor.vhd
14,7 → 14,7
-- |
-- ************************************************************* |
-- Distributed under the GNU Lesser General Public License. * |
-- This can be obtained from “www.gnu.org”. * |
-- This can be obtained from www.gnu.org. * |
-- ************************************************************* |
-- This program is free software: you can redistribute it and/or modify |
-- it under the terms of the GNU General Public License as published by |
50,8 → 50,8
-- u701 : out std_logic; |
u601 : out std_logic; |
rst_pin : in std_logic; |
irq_pin : in std_logic; |
nmi_pin : in std_logic; |
-- irq_pin : in std_logic; |
-- nmi_pin : in std_logic; |
RX_pin : in std_logic; |
-- PG_pin : in std_logic; |
TX_pin : out std_logic; |
138,20 → 138,22
signal rx_dat : unsigned(7 downto 0); |
signal proc_write : std_logic; |
signal one, RX_rdy, csw_usart, csr_usart, tx_rdy : std_logic; |
-- signal cycle_mark : std_logic |
signal rst_bar : std_logic; |
signal ram_write : std_logic; |
|
--signal clk : std_logic; |
--signal clk_pin : std_logic; |
signal counter : unsigned(3 downto 0); |
|
signal nmi_pin, irq_pin : std_logic; |
|
-- I/O ports |
|
constant led_port : unsigned (15 downto 0) := x"4007"; |
constant rs232_dat : unsigned (15 downto 0) := x"4000"; --input and output |
constant uart_stat : unsigned (15 downto 0) := x"4001"; --RX and TX state found here |
constant uart: unsigned (15 downto 0) := x"4000"; --starts the uart transmitting |
|
constant Kirq : unsigned (15 downto 0) := X"4002"; --interrpt testing only |
constant Knmi : unsigned (15 downto 0) := x"4003"; |
|
begin |
|
U1 : P65C02 port map( |
209,11 → 211,15
-- WE => ram_write, |
-- address(9 downto 0) => std_logic_vector(Address(9 downto 0)), |
-- Data => std_logic_vector(data_wr), |
-- unsigned(Q) => ram_dat, ClockEn => one); |
-- unsigned(Q) => ram_dat |
-- ClockEn => one); |
|
one <= '1'; |
rst_bar <= not rst_pin; |
one <= '1'; |
|
ram_write <= proc_write and not address(15) and not address(14); |
|
--one <= '1'; |
--u601 <= cycle_mark; |
|
|
227,14 → 233,14
end if; |
end process; |
|
ram_address : process (proc_write, address(15 downto 14)) |
begin |
if proc_write = '1' and address(15 downto 14) = "00" then |
ram_write <= '1'; |
else |
ram_write <= '0'; |
end if; |
end process; |
--ram_address : process (proc_write, address(15 downto 14)) |
--begin |
-- if proc_write = '1' and address(15 downto 14) = "00" then |
-- ram_write <= '1'; |
-- else |
-- ram_write <= '0'; |
-- end if; |
--end process; |
|
|
|
275,14 → 281,36
|
|
|
relay : process (rst_pin, proc_write, address, data_wr(7), clk_pin) |
begin |
if rst_pin = '0' then |
Pwr_on_pin <= '0'; |
elsif rising_edge(clk_pin) and address = led_port and proc_write = '1' then |
Pwr_on_pin <= data_wr(7); |
end if; |
end process; |
--relay : process (rst_pin, proc_write, address, data_wr(7), clk_pin) |
--begin |
--if rst_pin = '0' then |
-- Pwr_on_pin <= '0'; |
-- elsif rising_edge(clk_pin) and address = led_port and proc_write = '1' then |
-- Pwr_on_pin <= data_wr(7); |
--end if; |
--end process; |
|
--irq : process (rst_pin, proc_write, address, data_wr(0), clk_pin) |
--begin |
--if rst_pin = '0' then |
-- irq_pin <= '1'; |
-- elsif rising_edge(clk_pin) then |
-- if address = Kirq and proc_write = '1' then |
-- irq_pin <= data_wr(0); --set and hold bit 0 |
-- end if; |
--end if; |
--end process; |
|
--nmi : process (rst_pin, proc_write, address, data_wr(0), clk_pin) |
--begin |
--if rst_pin = '0' then |
-- nmi_pin <= '1'; |
-- elsif rising_edge(clk_pin) then |
-- |
-- if address = Knmi and proc_write = '1' then |
-- nmi_pin <= data_wr(0); --set and hold bit 0 |
-- end if; |
--end if; |
--end process; |
|
end structure; |