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Description: +
LCD Driver that we want to designed is a CMOS LCD driver capable of +driving a multiplexed display of up to 128 segments ( 16 columns by 8 backplanes +). The number of backplanes being driven is programmable from one to eight. +Data to be displayed is sent to the chip serially and stored in an internal +RAM. An external resistor and capasitor control the frequency of the driving +signals to the LCD. The displayed data may also be read serially from the +on-chip RAM. +
Specifications: +
-
+
- +Operates on 22-bits (five bits first is address, the next bit is read and +write flags, and 16 bits data ) + +
- +Can be programmed to accept oscillator output + +
- +Can be programmed to backplane signals of another LCD Driver for cascading +purposes. + +
- +Can driving a multiplexed display + +
- +For backplane capacitance under 2000 pF LCD driver guarantees an offset +of less than 10 mV. + +
- +Power supply of VDD is 5 V - 15 V. +
+Design Stages: +
-
+
- +Make core specifications + +
- +Design the behavioral and structural VHDL using Alliance tools + +
- +Implementation to symbolic layout + +
- +Full verifications + +
- +Converting to real layout + +
- +Make full report +
-
+
- +Make the behavioral and structural VHDL using Alliance tools + +
- +To know a little bit about Alliance, click this + +
- +You can download our work documentation (Alliance VHDL code) here. +
LCD Driver development team +
current members:
+
+
+
-
+
- +Kharisma Sinung P + +
- +Hendra Gunawan + +
- +Nurhadi Wiyono + +
- +Sarwono Sutikno +
A Little Bit about +Alliance
++
A. Introduction
+Alliance is a Computer Aided Design System for Very Large +Scale Integrated Circuits (VLSI) design. Alliance is a non-commercial +software developed by Équipe Achitecture des Systèmes et Micro-Électronique, +Laboratoire d'Informatique de Paris 6,Université Pierre et Marie Curie, +France. So, if you are interested in Alliance, you can get the software +and more information at http://www-asim.lip6.fr +. We usually run this software under Linux Operating Systems (we use Red +Hat Linux 6.2).
+The ALLIANCE VHDL is dedicated to digital +synchronous circuits design, which is usually used for: +-
+
- logic simulation +
- logic synthesis +
- functional abstraction +
- formal proof +
The ALLIANCE VHDL is fully compatible with the IEEE VHDL +standard Ref. 1076 (1987). That means that a VHDL description using the ALLIANCE +subset can be simulated with any full-VHDL commercial compiler-simulator.
+The VHDL description of a circuit is made of two separate +parts: the external view and the internal view. +
The external view defines the name of the circuit and its +interface. The interface of a circuit is a list of ports. Each port is specified +by its name, its mode, its type, its constraint for an array and, its kind. +
The mode of a port depends only on the manner the port is used
+inside the circuit (in the internal view of the circuit). If the value of a port
+is to be read in the view of the description, the port must be declared with the
+mode IN
. If the value of a port is to be written by the internal
+view, the port must be declared with the mode OUT
. If both above
+conditions are satisfied the port must be declared with the mode INOUT
.
+Only structural and behavioural data flow are supported as
+internal view.
+
A circuit, a subcircuit, or a cell can have two different +descriptions: +
-
+
- a structural view may be defined in a file with a
.vst
+ extension + - a behavioural data flow description may be defined in a
+ file with a
.vbe
extension.
+
+
B. Starting Using Alliance
+We can start using Alliance by linking our workspace to the +source of Alliance by typing :
++source /home/cad/alliance/share/etc/alc_env.csh
+here we assume that the Alliance is located in directory +/home/cad.
+The next step is to set the environment of Alliance. We
+usually use logic gates from sclib to develop a circuit. So, we
+must set the environment by typing :
+
setenv +MBK_CATA_LIB .:/home/cad/alliance/archi/Linux/cells/sclib
+We must know the symbolic name of gate that we use by seeing +manual of sclib. To see manual of all about command we want to know, we +can type
++man name_of_command
+After that, we can start our design by typing the source code +in the text editor. Our design can be from behavioural data flow +description or logic circuit description. We can write our comment like +this :
++/* our_comment */
+If our design comes from behavioural data flow description, we +save it with a .vbe extension. You can see examples of +behavioural D-Flip Flop design here.
+If our design comes from logic circuit description, we save it +with a .c extension. In +order to write this file, we must follow the syntax below :
+/*
+genlib.h is required for all genlib programs.
+it defines the set of functions we will use for schematic capture
*/
+#include <genlib.h>
+
/*
+decoder.c is to become the `core' executable program. So we must
+define a main procedure main()
*/
main()
+{
+DEF_LOFIG("decoder"); /* decoder.c is our file
+name */
+
/* define inputs and outputs of our system */
++
/*
+We start with the input terminals.
+Only signals and connectors can be vectorized.
*/
LOCON("x", IN, "x" );
+/* define input */
+LOCON("res", IN, "res" );
+/* define reset input, if we need it */
+LOCON("ck", IN, "ck" );
+/* define clock input */
LOCON("z", INOUT, "z" +); /* define an output of a gate +but acts as input of another gate */
++
/*
+Then, the output terminals.
*/
+LOCON("y[0:1]", OUT, "y[0:1]" );
+ /* define output consists of 2
+bits*/
+
+
/*
+Then the supplies.
+They are inputs, but we like them better at the end of the
+description.
*/
LOCON("vdd", IN, "vdd"
+); /* define vdd input */
+LOCON("vss", IN, "vss" );
+/* define vss input */
+
+....
+
/* define all components that we use to +develop our system */
++
LOINS("a2_y", "a1", +"x", "m", "z", "vdd", "vss",0);
++
/* a2_y is a simbolic name for 2 +inputs and gate */
+/* a1 is our given name for +this component where there must be no same name in the same file */
+/* x and m is inputs of a1 */
+/* z is the output of a1 */
++
....
++
SAVE_LOFIG();
+exit(0);
+/* necessary for the proper run of the Makefile */
}
+
+
Here +we can see the example .c file of 4-bit counter.
++
C. Basic Alliance +Tools
++
After that, we are +now ready to actually design the chip and use the Alliance tools. The design +flow for this little example is composed of 5 main steps:
+-
+
-
+
behavioral capture + and simulation
+ -
+
netlist capture + and validation
+ -
+
physical layout + generation
+ -
+
design validation
+ -
+
symbolic to real + conversion.
+
First of all, we must make a structural file (.vst). +We can get structural view from our behavioural data flow description (.vbe) +file or from our .c file. Here are the basic Alliance tools :
+(i) +genlib
+By
+using this tool, we can change our logic circuit description file (.c)
+into structural file (.vst) which more useful in next process.
+ + +genlib .c_file_name +
+(ii)
+scmap
Our
+behavioural data flow description file (.vbe) can be changed into
+structural file (.vst) by using this tool. The command is :
+
+ +scmap .vbe_ file_name .vst_file_name +
+We +can see the structural file (.vst) generated from the previous +behavioural D-Flip Flop design here. +
+(iii) +asimut
+This +tool is usually used to simulate our design by giving some inputs. We can +see simulation results, which can be compared to our expected outputs. We +must create a test pattern file (.pat) contains some inputs we will +use in the simulation. You can see the example of test pattern file here. +The command is :
+
+ asimut .vst_file_name test_pattern_file_name
+simulation_results_file_name
(iv)
+xsch
We +can see logic circuit of our structural file by using this tools.
+(v)
+xpat
(vi)
+scr
Our
+structural file can be extracted into symbolic layout using scr.
+The command is :
+
+
+
+scr -sclib -p -r file_name
This
+symbolic layout result (.ap) can be viewed by graal tool.
(vii) +s2r
+Our
+symbolic layout can be changed into real layout by using s2r. The
+command is :
+
+s2r file_name
This +real layout (.cif) can be viewed by using dreal tool.
+(viii)
+lynx
Our +real layout can be changed into new structural file (.al) by using lynx. +First, we must set the environmet by the command :
++setenv MBK_OUT_LO al
+then +we type the command :
++lynx -v .ap_file_name output_file_name -f
+After +this, we can do simulation post-layout on the old (.vst) and new (.al) +structural file by using lvx. The command is :
++lvx vst al .vst_file_name .al_file_name
+Another way to compare the result is using asimut.
+We can simulate the new structural file (.al) with the previous test
+pattern file using asimut. But first, we must set the environment :
+
+setenv MBK_IN_LO al
+then using asimut :
++asimut .al_file_name testpattern_file_name result_file_name
+After that we can compare the new simulation result with the +previous simulation result. We expect to get the same result.
+ ++ +
To know more about Alliance and find tutorials, you can +visit http://www-asim.lip6.fr
+ + + + Index: lcd/web_uploads/decoderc.shtml =================================================================== --- lcd/web_uploads/decoderc.shtml (nonexistent) +++ lcd/web_uploads/decoderc.shtml (revision 6) @@ -0,0 +1,199 @@ + + +
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Example of +Test Pattern file
++
in vdd;
in vss;
in x;
in res;
in ck;
out y(1 to 0);
begin
pat_1 : 1 0 +1 1 0 +?**; /* 1st bit representation +of vdd
+
+
+2nd bit respresentation of vss
+3rd bit respresentation of x
++ +4th bit respresentation of res
++ +5th bit respresentation of ck
+
+
+** respresentation of y(1 to 0)
+*/ +
+pat_2 : 1 0
+1 0 1
+?**;
pat_3 : 1 0
+1 0 0
+?**;
pat_4 : 1 0
+1 0 1
+?**;
pat_5 : 1 0
+1 0 0
+?**;
pat_6 : 1 0
+0 0 1
+?**;
pat_7 : 1 0
+0 0 0
+?**;
pat_8 : 1 0
+0 0 1
+?**;
pat_10 : 1 0
+1 1 0
+?**;
pat_11 : 1 0
+0 0 1
+?**;
pat_12 : 1 0
+1 0 0
+?**;
pat_13 : 1 0
+1 0 1
+?**;
pat_14 : 1 0
+0 0 0
+?**;
pat_15 : 1 0
+1 0 1
+?**;
pat_16 : 1 0
+1 0 0
+?**;
pat_17 : 1 0
+0 0 1
+?**;
pat_18 : 1 0
+1 0 0
+?**;
pat_19 : 1 0
+1 0 1
+?**;
pat_20 : 1 0
+0 0 0
+?**;
pat_21 : 1 0
+1 0 1
+?**;
pat_22 : 1 0
+0 0 0
+?**;
pat_23 : 1 0
+1 1 1
+?**;
pat_24 : 1 0
+1 0 0
+?**;
pat_25 : 1 0
+0 0 1
+?**;
end;
+ + + + Index: lcd/web_uploads/counter.shtml =================================================================== --- lcd/web_uploads/counter.shtml (nonexistent) +++ lcd/web_uploads/counter.shtml (revision 6) @@ -0,0 +1,94 @@ + + + + + + +.c file of 4-bit counter
++
#include <genlib.h>
+
main()
+{
++DEF_LOFIG("counter");
++
+LOCON("E", +IN, "E");
++LOCON("ck", +IN, "ck");
++LOCON("res", +IN, "res");
++LOCON("vdd", +IN, "vdd");
++LOCON("vss", + IN, "vss");
++LOCON("A[0:3]", +INOUT, "A[0:3]");
++LOCON("q_c", +OUT, "q_c");
+
LOINS("a2_y","an00", +"E","A[0]", "c_1", "vdd" ,"vss",0);
+LOINS("a2_y","an01", +"c_1","A[1]", "c_2", "vdd" ,"vss",0);
+LOINS("a2_y","an02", +"c_2","A[2]", "c_3", "vdd" ,"vss",0);
+LOINS("a2_y","an03", +"c_3","A[3]", "q_c", "vdd" ,"vss",0);
+
LOINS("xr2_y","xr00", +"E","A[0]", "d_1", "vdd" ,"vss",0);
+LOINS("xr2_y","xr01", +"c_1","A[1]", "d_2", "vdd" ,"vss",0);
+LOINS("xr2_y","xr02", +"c_2","A[2]", "d_3", "vdd" ,"vss",0);
+LOINS("xr2_y","xr03", +"c_3","A[3]", "d_4", "vdd" ,"vss",0);
+
LOINS("dffres", +"dff0", "d_1", "ck","res","A[0]","vdd","vss",0);
+LOINS("dffres", +"dff1", "d_2", "ck","res","A[1]","vdd","vss",0);
+LOINS("dffres", +"dff2", "d_3", "ck","res","A[2]","vdd","vss",0);
+LOINS("dffres", +"dff3", "d_4", "ck","res","A[3]","vdd","vss",0);
+
+SAVE_LOFIG();
++exit(0);
+}
+ + + + Index: lcd/web_uploads/dflipflop.shtml =================================================================== --- lcd/web_uploads/dflipflop.shtml (nonexistent) +++ lcd/web_uploads/dflipflop.shtml (revision 6) @@ -0,0 +1,127 @@ + + + + + + +Behavioural +data flow description for D-Flip Flop
++
ENTITY dffres IS
+PORT (
+input : in bit;
+
+clk : in
+bit;
+reset : in bit;
+output : out bit;
+
+vdd : in
+bit;
+vss : in
+bit
+);
END dffres;
ARCHITECTURE VBE OF
+dffres IS
+SIGNAL dffres_reg : REG_BIT REGISTER;
+
+
BEGIN
+ASSERT ((vdd and not (vss)) = '1')
+REPORT "power supply is missing on dffres"
+SEVERITY WARNING;
+
+
+dff : BLOCK ( ( clk AND NOT (clk'STABLE)) = '1' )
+BEGIN
+dffres_reg <= GUARDED '1' WHEN (reset = '1') else NOT input;
+END BLOCK dff;
+
+output <= NOT dffres_reg ;
+
END ;
+ + + + Index: lcd/web_uploads/ramc.shtml =================================================================== --- lcd/web_uploads/ramc.shtml (nonexistent) +++ lcd/web_uploads/ramc.shtml (revision 6) @@ -0,0 +1,543 @@ + + +
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Description: +
LCD Driver that we want to designed is a CMOS LCD driver capable of +driving a multiplexed display of up to 128 segments ( 16 columns by 8 backplanes +). The number of backplanes being driven is programmable from one to eight. +Data to be displayed is sent to the chip serially and stored in an internal +RAM. An external resistor and capasitor control the frequency of the driving +signals to the LCD. The displayed data may also be read serially from the +on-chip RAM. +
Specifications: +
-
+
- +Operates on 22-bits (five bits firts is address, the next bit is read and +write flags, and 16 bits data ) + +
- +Can be programmed to accept oscillator output + +
- +Can be programmed to backplane signals of another LCD Driver for cascading +purposes. + +
- +Can driving a multiplexed display + +
- +For backplane capacitance under 2000 pF LCD driver guarantees an offset +of less than 10 mV. + +
- +Power supply of VDD is 5 V - 15 V. +
-
+
- +Make core specifications + +
- +Design the behavioral and structural VHDL using Alliance tools + +
- +Implementation to symbolic layout + +
- +Full verifications + +
- +Converting to real layout + +
- +Make full report +
-
+
- +Make the behavioral and structural VHDL using Alliance tools +
LCD Driver development team +
current members: +
-
+
- +Hendra Gunawan + +
- +Nurhadi Wiyono + +
- +Kharisma Sinung P + +
- +Sarwono Sutikno +
D-Flip Flop structural file generated from D-Flip Flop +Behvioural File
++
-- VHDL structural
+description generated from `dffres`
--
+date : Thu Dec 7 16:20:50
+2000
-- Entity
+Declaration
ENTITY dffres IS
+PORT (
+input : in BIT;
+-- input
+clk : in BIT;
+-- clk
+reset : in BIT;
+-- reset
+output : out BIT; --
+output
+vdd : in BIT;
+-- vdd
+vss : in BIT
+-- vss
+);
END dffres;
-- Architecture
+Declaration
ARCHITECTURE VST OF
+dffres IS
+COMPONENT ndrvp_y
+port (
+i : in BIT;
+-- i
+f : out BIT;
+-- f
+vdd : in BIT;
+-- vdd
+vss : in BIT
+-- vss
+);
+END COMPONENT;
+COMPONENT o2_y
+port (
+i0 : in BIT;
+-- i0
+i1 : in BIT;
+-- i1
+t : out BIT;
+-- t
+vdd : in BIT;
+-- vdd
+vss : in BIT
+-- vss
+);
+END COMPONENT;
+COMPONENT no2_y
+port (
+i0 : in BIT;
+-- i0
+i1 : in BIT;
+-- i1
+f : out BIT;
+-- f
+vdd : in BIT;
+-- vdd
+vss : in BIT
+-- vss
+);
+END COMPONENT;
+COMPONENT msdp2_y
+port (
+di : in BIT;
+-- di
+ck : in BIT;
+-- ck
+t : out BIT;
+-- t
+vdd : in BIT;
+-- vdd
+vss : in BIT
+-- vss
+);
+END COMPONENT;
+SIGNAL auxsc3 : BIT;
+-- auxsc3
+SIGNAL auxsc4 : BIT;
+-- auxsc4
+SIGNAL auxsc5 : BIT;
+-- auxsc5
+SIGNAL auxreg1 : BIT;
+-- auxreg1
BEGIN
+output : ndrvp_y
+PORT MAP (
+vss => vss,
+vdd => vdd,
+f => output,
+i => auxreg1);
+auxsc5 : ndrvp_y
+PORT MAP (
+vss => vss,
+vdd => vdd,
+f => auxsc5,
+i => clk);
+auxsc4 : o2_y
+PORT MAP (
+vss => vss,
+vdd => vdd,
+t => auxsc4,
+i1 => auxsc3,
+i0 => reset);
+auxsc3 : no2_y
+PORT MAP (
+vss => vss,
+vdd => vdd,
+f => auxsc3,
+i1 => input,
+i0 => reset);
+dffres_reg : msdp2_y
+PORT MAP (
+vss => vss,
+vdd => vdd,
+t => auxreg1,
+ck => auxsc5,
+di => auxsc4);
end VST;
+ + + + Index: lcd/web_uploads/mcv.shtml =================================================================== --- lcd/web_uploads/mcv.shtml (nonexistent) +++ lcd/web_uploads/mcv.shtml (revision 6) @@ -0,0 +1,158 @@ + + +
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