URL
https://opencores.org/ocsvn/lcd162b_behavior/lcd162b_behavior/trunk
Subversion Repositories lcd162b_behavior
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/lcd162b_behavior/trunk/testbench.vhd
0,0 → 1,36
library ieee; |
use ieee.std_logic_1164.all; |
|
entity testbench is |
end entity testbench; |
|
architecture RTL of testbench is |
|
component lcd162b is |
port ( |
rs : in std_logic; |
rw : in std_logic; |
e : in std_logic; |
db : inout std_logic_vector(7 downto 0); |
|
line1 : out string(1 to 16); |
line2 : out string(1 to 16) |
); |
end component lcd162b; |
|
signal disp1 : string(1 to 16); |
signal disp2 : string(1 to 16); |
|
begin |
|
uut : lcd162b |
port map( |
rs => '0', |
rw => '0', |
e => '0', |
db => open, |
line1 => disp1, |
line2 => disp2 |
); |
|
end architecture RTL; |
/lcd162b_behavior/trunk/lcd162b.vhd
0,0 → 1,23
library ieee; |
use ieee.std_logic_1164.all; |
|
entity lcd162b is |
port ( |
rs : in std_logic; |
rw : in std_logic; |
e : in std_logic; |
db : inout std_logic_vector(7 downto 0); |
|
line1 : out string(1 to 16); |
line2 : out string(1 to 16) |
); |
end entity lcd162b; |
|
architecture RTL of lcd162b is |
|
begin |
|
line1(1 to 5) <= "hallo"; |
line2(1 to 2) <= "du"; |
|
end architecture RTL; |